JPH0876708A - D class vertical output amplifier - Google Patents

Abstract

PURPOSE: To decrease through-current and to save electric power by surely and operating two transistors(TRs) on and off alternately. CONSTITUTION: Saw tooth input signals are converted by a comparator 3 into pulse signals which are respectively supplied to first and second output TRs Q1, Q2. These output TRs Q1, Q2 amplify the pulse signals by making switching operation. The amplified signals are thereafter integrated by a choke coil L1 and are supplied to a vertical deflection coil DL. In such a case, first and second comparators 4, 5 discriminate the periods indicating the upper half and lower half of the screen based on the input signals and output the results of discrimination to turn on and off TRs Q4, Q5 as switching means based on the results of the discrimination. As a result, the output TRs Q1, Q2 do not turn on simultaneously and further, the first and second comparators 4, 5 have the operation range where the comparators do not operate near the screen center based on the input signals and, therefore, the comparators operate more surely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical deflection circuit of a television receiver, and more particularly to a class D vertical output amplifier suitable for power saving used in the vertical deflection circuit.

[0002]

2. Description of the Related Art Generally, in a vertical and horizontal deflection circuit of a television receiver, a sawtooth-like current (hereinafter referred to as a deflection current) is applied to horizontal and vertical deflection coils attached to a neck portion of a picture tube. ) Is applied to control the electron beam direction by the generated magnetic field.

The vertical deflection circuit is usually composed of a vertical oscillation circuit, a vertical drive circuit, and a vertical output circuit. The vertical oscillation circuit is a circuit for generating a deflection current that changes in a sawtooth shape and is for vertical scanning. As a result, a deflection current of about 59.94 Hz is created. The vertical drive circuit is a circuit that shapes and amplifies the generated deflection current. The vertical output circuit is a circuit that further amplifies the amplified deflection current and supplies it to the vertical deflection coil.

By the way, the vertical output circuit is provided with an amplifier for further amplifying the sawtooth deflection current shaped and amplified by the drive circuit. This amplifier has
Classifying according to the operating point of the transistor, there are a class A amplifier circuit, a class B amplifier circuit, etc., and a signal for vertical output (vertical deflection) is conventionally amplified.

The class A amplifier circuit has a good distortion factor and a large power gain because the operating point is selected at the substantially center of the load line so that the output current flows continuously, but the operating efficiency is poor. Further, since the class B amplifier circuit operates with a substantially zero bias between the base and the emitter, it has better linearity and operating efficiency than the class A amplifier circuit.

Further, the class A amplifier circuit has a large power loss because a current always flows when an input signal is input, whereas the class B amplifier circuit has a structure in which a current flows only when a signal is input. Therefore, the power loss is
Less than a class amplifier circuit.

Recently, a so-called class D amplifier circuit has been put into practical use, which has improved operation efficiency more than the above-described class A and class B amplifier circuits and theoretically has no power loss.

The class D amplifier circuit will be briefly described. As is well known, the class D amplifier circuit is composed of a push-pull circuit, and two transistors perform a switch operation. A class D amplifier circuit usually converts an input signal into a pulse, amplifies it, and then integrates the pulse to reproduce the signal. That is, the amplitude of the signal is converted into the duty of the pulse. Like this
The class amplifier circuit uses a PWM (pulse width modulation) format. Therefore, when an amplifier (hereinafter, referred to as an amplifier) is configured by using a class D amplifier circuit, the amplifier amplifies a pulse, so that the amplifier can be configured by a simple switch and has very good linearity and extremely high linearity. An efficient amplifier can be configured. Further, if an amplifier with high operation efficiency is realized in this way, it is expected that heat generation can be suppressed when it is integrated into an IC, for example, so that a heat sink is not required and power can be saved.

An example of the circuit configuration of a class D vertical output amplifier using such a class D amplifier circuit is shown in FIG.

In FIG. 4, a sawtooth signal (deflection current) is input to the input terminal 1. This signal is supplied to the positive terminal of a comparator (hereinafter referred to as a comparator) 2.
The deflection current is finally amplified and the sawtooth-shaped deflection current supplied to the vertical deflection coil DL is fed back to the negative terminal of the comparator 2. The comparator 2 acts as a differential amplifier,
The signal supplied from the input terminal 1 and the signal supplied from the negative terminal are compared and output as a positive / negative output signal. This output signal is supplied to the positive terminal of the other comparator 3.

A reference signal is supplied to the negative terminal of the comparator 3, and the comparator 3 compares the output signal from the comparator 2 with the reference signal to pulse-width-modulate the sawtooth signal waveform. A waveform (hereinafter referred to as a PWM signal) is converted and output. This PWM signal is supplied to the bases of two output transistors Q1 and Q2, which are switching elements, via capacitors C1 and C2, respectively. As shown in FIG. 4, a PNP transistor is used as the output transistor Q1 in the upper stage, and the emitter is connected to the power supply voltage Vcc. On the other hand, an NPN type transistor is used as the lower output transistor Q2, and the collector of the output transistor Q1 is connected to the collector of the output transistor Q2. The emitter of the output transistor Q2 is grounded.

Diodes D1 and D2 are connected in parallel between the emitters and collectors of the output transistors Q1 and Q2, respectively. A choke coil L1 is connected to the collectors of the output transistors Q1 and Q2,
The choke coil L1 is a vertical deflection coil DL and a resistor R.
It is grounded through 1. In addition, the vertical deflection coil DL
The base end side of is connected to the negative terminal of the comparator 2 in order to supply the deflection current supplied to the vertical deflection coil DL to the comparator 2 as described above.

In the class D vertical output amplifier having such a configuration, the sawtooth signal which is the input signal is converted into the PWM signal by the comparator 3, and the PWM signal is supplied to the bases of the output transistors Q1 and Q2. , PWM
The two transistors Q1 and Q2 alternately perform a switching operation so that the output transistor Q1 turns on on the positive side of the signal and one output transistor Q2 turns on on the negative side. As a result, the PWM signal is amplified by the switching by the transistors Q1 and Q2, and then this PWM signal is supplied to the choke coil L1 and integrated. The sawtooth-shaped deflection current thus amplified is supplied to the vertical deflection coil DL, and vertical deflection is performed based on the input signal.

However, since a switching circuit using two transistors is used in the output stage in order to amplify the sawtooth-shaped deflection current as an input signal and supply it to the vertical deflection coil DL, the class D vertical Considering the efficiency of the output amplifier, the influence of the operation of this switching circuit is considered.

For example, in this case, the output transistor Q
There is a switching loss due to 1 and Q2. That is, this is a case where power is lost due to a through current and a case where power is lost due to the saturation voltage (Vcesat) of the collector-emitter. In particular, the problem with power saving is
The power loss due to the through current has a great influence.

Generally, the input sawtooth deflection current is
The positive side means vertical deflection based on the upper half of the screen, and the negative side means vertical deflection based on the lower half of the screen. Therefore, it is desirable that the output transistors Q1 and Q2 perform a switching operation so as to be alternately turned on / off based on the sawtooth deflection current in order to perform optimum vertical deflection. However, actually, when the sawtooth deflection current changes from positive to negative or from negative to positive, the output transistors Q1 and Q2 are alternately turned on / off due to the influence of storage time (storage time in the storage time). There are cases where they are turned on at the same time without being turned on. In this case, in the class D vertical output amplifier shown in FIG. 4, since there is no current limiting resistance between the output transistor Q1 and the output transistor Q2, no load is applied to the power supply voltage Vcc to the ground level (hereinafter referred to as GND). (Abbreviation) current will flow, that is, this will be a through current. Therefore,
There is a problem that the power loss increases when the through current flows.

Further, this problem does not become a particular problem if the switching speed of the output transistors Q1 and Q2 is sufficiently fast. However, these output transistors Q1 and Q2 are generally transistors for large output (referred to as power transistors), and are configured to have a high breakdown voltage for driving vertical deflection. For this reason, in a class D vertical output amplifier using a transistor for high output, the switching speed is slow, and the power loss due to the influence of the shoot-through current is particularly remarkable.

[0018]

As described above, in the conventional class D vertical output amplifier, two transistors may be turned on at the same time due to the influence of storage time.
At this time, a through current flows from the power supply to the GND (ground) with no load. Therefore, there is a problem that power loss occurs due to the influence of the through current, and as a result, power saving cannot be achieved.

Therefore, the present invention has been made in view of the above problems, and it is ensured that two transistors are alternately turned on and off.
It is an object of the present invention to provide a class D vertical output amplifier suitable for power saving by reducing the shoot-through current by controlling the off operation to suppress power loss.

[0020]

A class D vertical output amplifier according to the present invention according to claim 1 is a pulse signal generating means for pulse-width modulating a sawtooth input signal to output a pulse signal, and the pulse signal generating means. A pulse signal from each of the means is supplied, and switching operation is alternately performed based on the pulse signal to supply a current from the power supply voltage to the output stage or to draw the current to the ground level. Means for integrating the output signals of the output transistor and the first and second output transistors to generate a deflection current, supplying the deflection current to the vertical deflection coil, and generating the deflection current by passing it through a negative feedback resistor. Voltage is supplied respectively, and this voltage is compared with a voltage value to which different voltage values are respectively set in advance, and at a certain point, the first and second output transistors are Or a period for supplying current from the source voltage, or to determine a period to withdraw the current to the ground level, first and second outputs a determination result
Discriminating means and the discrimination results by the first and second discriminating means are respectively supplied, and a switching operation is performed so as to alternately turn on and off the first and second output transistors based on these discrimination results. And first and second switch means.

A class D vertical output amplifier according to a second aspect of the present invention is the class D vertical output amplifier according to the first aspect, wherein the first and second discriminating means are respectively composed of comparators. Therefore, the first comparator determines whether or not the state of the amplifier at a certain time is a period for supplying the power supply voltage current to the vertical deflection coil, and the second comparator is a period for drawing the current to the ground level. It is characterized by determining that there is.

A class D vertical output amplifier according to the present invention according to claim 3 is the class D vertical output amplifier according to claim 2, wherein the first comparator and the second comparator are the first and the second comparators. In order to prevent the two output transistors from operating at the same time, the amplifier has an operating range in which it does not react during the switching period between the period of supplying current from the power supply voltage and the period of drawing current to the ground level. To do.

[0023]

According to this structure, the sawtooth-shaped input signal is converted into the pulse signal by the pulse signal generating means and supplied to the first and second output transistors, respectively.
The first and second output transistors perform a switching operation such that they are alternately turned on and off based on the supplied pulse signal, and amplify and output the pulse signal.
The amplified signal is integrated and supplied as a deflection current to the vertical deflection coil to perform vertical deflection based on the input signal. In this case, the switching operation of the first and second output transistors is reliably performed by using the first and second discriminating means and the first and second switching means. For example, in the upper half of the screen, when the comparator as the first discriminating means exceeds a predetermined voltage value, it outputs a high-level signal to turn on the transistor of the corresponding first switch means, and at the same time, the second Cut off the output transistor of. On the contrary, in the lower half of the screen, when the comparator as the second discriminating means exceeds a predetermined voltage value, it outputs a high level signal to turn on the transistor of the corresponding second switch means and at the same time, Cut off the output transistor of 1. Since the first and second comparators have an operation range that does not operate near the center of the screen based on the input signal,
There is no malfunction such that the first and second output transistors operate at the same time, and therefore the switching operation can be reliably performed, so that the shoot-through current can be reduced. As a result, power loss due to a through current can be prevented, and power saving can be achieved.

[0024]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the concept of a class D vertical output amplifier according to an embodiment of the class D vertical output amplifier according to the present invention. The same components as those of the amplifier shown in FIG. 4 are designated by the same reference numerals.

In FIG. 1, a sawtooth signal (deflection current) is input to the input terminal 1 as in the conventional case. This signal is supplied to the positive terminal of the comparator 2. The deflection current is finally amplified and the sawtooth-shaped deflection current supplied to the vertical deflection coil DL is fed back to the negative terminal of the comparator 2. The comparator 2 plays the role of a differential amplifier, compares the signal supplied from the input terminal 1 with the signal supplied from the negative terminal, and outputs it as a positive / negative output signal. This output signal is supplied to the positive terminal of the other comparator 3.

A reference signal (sawtooth wave) is supplied to the negative terminal 3a of the comparator 3, and the comparator 3 compares the output signal from the comparator 2 with the reference signal to generate a sawtooth wave. Signal width is pulse width modulation waveform (PW
(M signal) and output. This PWM signal is supplied to the bases of two output transistors Q1 and Q2, which are switching elements, via capacitors C1 and C2, respectively. The upper output transistor Q1 shown in FIG.
Is a PNP transistor, and its emitter is connected to the power supply voltage Vcc. On the other hand, an NPN type transistor is used for the lower output transistor Q2,
The collector of the output transistor Q1 is connected to the collector of the output transistor Q2. The emitter of the output transistor Q2 is grounded.

Diodes D1 and D2 are connected in parallel between the emitters and collectors of the output transistors Q1 and Q2, respectively. A choke coil L1 is connected to the collectors of the output transistors Q1 and Q2,
The choke coil L1 is a vertical deflection coil DL and a resistor R.
It is grounded through 1. In addition, the vertical deflection coil DL
The base end side of is connected to the negative terminal of the comparator 2 in order to supply the deflection current supplied to the vertical deflection coil DL to the comparator 2.

On the other hand, in the class D vertical output amplifier of the present invention, the circuit group 10 including the two comparators 4 and 5 and the two transistors Q3 and Q4 is provided as a means for surely performing the switching operation alternately. Has been. The positive terminals of the comparators 4 and 5 are connected to the base end side of the vertical deflection coil DL via capacitors C3 and C4, respectively, and a deflection current flowing in the vertical deflection coil DL is supplied. Further, power supplies having different potentials are connected to the negative terminals of the comparators 4 and 5, respectively, so that the voltage V1 is supplied to the comparator 4 and the voltage V2 is supplied to the comparator 5. The voltages V1 and V2 are
For example, as shown in FIG. 2, there is a predetermined voltage difference, which is near the sawtooth-shaped deflection current, that is, near the center of the screen (a period when no current is flowing in the vertical deflection coil DL).
This is to prevent the comparators 4 and 5 from malfunctioning. That is, the comparators 4 and 5 have a non-operation range (dead zone) in which a malfunction does not occur in a predetermined period near the central amplitude of the input signal.

The output side of the comparator 4 is connected to the base of a transistor Q3 whose collector is connected to the base of the output transistor Q2.
The emitter of is grounded. The output side of the other comparator 5 is connected to the base of a transistor Q4 whose collector is connected to the base of the output transistor Q1, and the emitter of this transistor Q4 has a power supply voltage Vc.
It is connected to c.

For example, when a sawtooth signal is supplied to the class D vertical output amplifier, the comparators 4 and 5 cause the upper half of the screen (current flows from the amplifier to the vertical deflection coil DL).
Or the lower half (current is drawn from the vertical deflection coil DL to the amplifier), and the determination results are supplied to the transistors Q3 and Q4, respectively. Two transistors Q3, Q
4 turns on or off the output transistors Q1 and Q2 of the output stage based on the discrimination result by the comparators 4 and 5. That is, the transistors Q3 and Q4 are switching means for surely switching the two output transistors Q1 and Q2 alternately. Further, since the comparators 4 and 5 have the dead zone near the center of the screen as described above, the output transistors Q1 and Q2 can be surely supplied with the determination result because the output transistors Q1 and Q2 can be supplied with a reliable result. And Q2 do not turn on at the same time.

In the class D vertical output amplifier having such a configuration, as in the conventional circuit shown in FIG. 4, the two output transistors Q1 and Q2 in the output stage alternately turn on and off to output a pulse. These output transistors Q1,
As described above, the shoot-through current is generated when Q2 is turned on at the same time. Focusing on the supply path of the deflection current to the vertical deflection coil DL of the class D vertical output amplifier, in the upper half of the screen, that is, when a current is passed from the amplifier to the vertical deflection coil DL, during the period when the output transistor Q1 is on, A current is supplied from the power supply voltage Vcc through the output transistor Q1. Also, the output transistor Q2
Since the current does not change abruptly under the influence of the vertical deflection coil DL during the period when is on, in this case GND
From D2 via D2.

On the other hand, conversely to the above, when a current is drawn from the lower half of the screen, that is, from the vertical deflection coil DL to the amplifier, at the same time, the output transistor Q2 is turned on during the ON period.
Current is drawn to the output via the output transistor Q2. In addition, since the current does not change abruptly under the influence of the vertical deflection coil DL while the output transistor Q1 is on, the current is extracted to Vcc through D1 in this case. In other words, the output transistor Q2 is not required in the upper half of the screen, and the output transistor Q1 is not required in the lower half of the screen.
Therefore, it does not matter if the output transistor Q2 is not turned on in the upper half of the screen and Q1 is not turned on in the lower half of the screen.

Therefore, in this embodiment, the input signals are input to the comparators 4 and 5 after the direct current is cut by the capacitors C3 and C4, and the comparators 4 and 5 accurately detect the zero cross and do not malfunction. Furthermore, the comparator 4,
Since the dead zone 5 is provided at the center, the determination result can be supplied to the transistors Q3 and Q4 so that the input signal is properly switched between the first half and the second half. Thereafter, as shown in FIG. 2, the transistor Q3 is turned on in the first half of the screen to output the output transistor Q2 of the output stage.
Forcibly lower the base potential of to prevent it from turning on.
Therefore, the path of the through current in the first half of the screen can be cut off. The transistor Q4 is turned on in the latter half of the screen so that the base current of the output transistor Q1 is not supplied. Therefore, the path of the through current in the latter half of the screen can be cut off. In addition, the comparator 4,
The sawtooth deflection current input to 5 uses the voltage of the feedback resistor R1 of the vertical circuit as shown in FIG. 1, and this signal corresponds to the state of the screen on a one-to-one basis. The determination result can be output.

As described above, by adding the two comparators 4 and 5 and the two transistors Q3 and Q4 as the switch means to the conventional circuit (see FIG. 4), the two output transistors Q1 in the output stage are connected. Q2
It is possible to prevent and from turning on at the same time. Therefore, the period in which the through current flows can be significantly shortened, so that power loss due to the through current can be suppressed and power saving can be achieved.

FIG. 3 is a circuit diagram showing a concrete example of the class D vertical output amplifier shown in FIG.

In FIG. 3, a sawtooth signal (deflection current) is input to the input terminal 1 as in the case shown in FIG.
This signal is supplied to the positive terminal of the comparator 2, and the comparator 2 compares this signal with the signal supplied from the negative terminal and outputs it to the positive terminal of the comparator 3 as a positive / negative output signal. A sawtooth signal serving as a reference is supplied to the negative terminal 3a of the comparator 3 and is supplied to the negative terminal 3a.
The comparator 3 compares this reference signal with the signal from the comparator 2, converts the sawtooth signal waveform into a pulse width modulation waveform (PWM signal), and outputs it. The PWM signal is supplied via resistors to the bases of transistors Q1, Q5, Q6 and Q8 arranged to amplify the input signal. The transistors Q1 to Q9 including the transistors Q2, Q3, Q4, Q7, and Q9 shown in FIG. 3 are for amplifying an input signal. Among these, the transistors Q7 and Q9 are switching elements ( Output transistor).

Thus, the PWM signal is transmitted to the transistor Q1.
Through Q9, the signal is amplified and integrated by the choke coil L1 as in the circuit operation shown in FIG. After that, the amplified current is supplied to the vertical deflection coil DL, the direct current component is cut by the capacitor C1, and then negatively fed back via the feedback resistor R1. Then, the voltage across the feedback resistor R1 is used to cut the direct current component by using the capacitors C2 and C3, thereby surely detecting the zero cross and inputting it to the positive input ends of the comparators 4 and 5. Voltages having different voltage differences are supplied to the negative input terminals of the comparators 4 and 5 as in the case shown in FIG. The outputs of the comparators 4 and 5 are supplied to the transistors Q10 and Q11 provided as switching means, respectively, and the transistors Q10 and Q11 are provided.
Reference numeral 11 operates so as to be alternately switched by output pulses from the comparators 4 and 5. At this time, in the upper half of the screen, that is, when the sawtooth wave is higher than the zero cross, the transistor Q10 is turned on. Then, the base current of the transistor Q8 is forcibly reduced, so that the transistor Q9 in the output stage is not turned on. On the contrary, in the lower half of the screen, that is, when the sawtooth wave is lower than the zero cross, the transistor Q11 is turned on. Then, the base current of the transistor Q5 is forcibly reduced, so that the current mirror of the transistors Q2 and Q4 does not flow current. Therefore, the transistor Q7 in the output stage does not turn on. Therefore, by setting the reference voltage of the comparators 4 and 5 to an appropriate voltage, the dead zone can be provided in the center of the screen, and it is possible to avoid malfunction due to the loop being broken in an unstable state near the center of the screen. That is, it is possible to prevent the two transistors Q7 and Q9 in the output stage from being turned on at the same time. Therefore, it is possible to reduce the period during which the through current flows, and thus it is possible to reduce the power loss due to the through current, that is, to save the power.

[0038]

As described above, according to the present invention, 2
By providing one comparator and two transistors as switching means, the switching operation by the two output transistors in the output stage can be alternately and surely performed, so that the power loss due to the through current can be reduced. Moreover, the efficiency of the class D vertical output amplifier can be maximized and the power consumption can be saved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing the concept of a class D vertical output amplifier according to the present invention.

FIG. 2 is an explanatory diagram for explaining the operation in FIG.

FIG. 3 is a circuit configuration diagram showing a specific circuit configuration of the class D vertical output amplifier shown in FIG.

FIG. 4 is a circuit diagram showing a circuit configuration of a conventional class D vertical output amplifier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2, 3 ... Comparator, 4 ... 1st discrimination | determination means (comparator), 5 ... 2nd discrimination means, (comparator), Q1, Q2 ... Output transistor, Q3 ... 1st switch means (transistor) ), Q4 ... Second switch means (transistor), D1, D2 ... Diode,
L1 ... Choke coil, DL ... Vertical deflection coil, Vcc
... power supply voltage, I ... through current.

Claims (4)

[Claims] 1. A pulse signal creating means for pulse width modulating a sawtooth input signal to output a pulse signal, and a pulse signal from said pulse signal creating means are respectively supplied, and switching operation is alternately performed based on this pulse signal. The output signals of the first and second output transistors and the first and second output transistors for supplying the current from the power supply voltage to the output stage or extracting the current to the ground level are integrated. Means for generating a deflection current and supplying the deflection current to the vertical deflection coil, and a voltage generated by flowing the deflection current through the negative feedback resistor are respectively supplied, and this voltage and a different voltage value are respectively set in advance. The voltage values are compared with each other, and at a certain time, the first and second output transistors are in a period for supplying current from the power supply voltage or to the ground level. The first to output the determination result by determining whether it is the period for drawing the current
And the second discriminating means and the discrimination results by the first and second discriminating means are respectively supplied, and based on these discrimination results, the first and second discriminating means are supplied.
And a second switching means for performing a switching operation so as to alternately turn on and off the output transistor of 1., and a class D vertical output amplifier. 2. The first and second discriminating means are each configured by a comparator, and the state of the amplifier at a certain point in time of the first comparator supplies a power supply voltage current to the vertical deflection coil. Determine whether it is a period,
The second comparator determines that it is a period for drawing a current to the ground level.
A vertical output amplifier of class D according to item 1. 3. The first comparator and the second comparator include a period during which the amplifier supplies a current from a power supply voltage and a ground level so that the first and second output transistors do not operate simultaneously. 3. The class D vertical output amplifier according to claim 2, wherein the class D vertical output amplifier has an operation range that does not react during a switching period between a period for drawing out a current to the vertical direction and a period for switching. 4. The first and second switch means are configured by using first and second transistors, and the first transistor has a high level in the determination result of the first comparator. Signal of 2 turns on the first output transistor and cuts off the second output transistor, and the second transistor turns off the second transistor.
If the determination result of the comparator is a high-level signal, the second output transistor is turned on, and
The class D vertical output amplifier according to claim 1, wherein the class D vertical output amplifier is switch-operated so as to cut off the first output transistor.