JPH087583A - Storing method and reading method for analog quantity and semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory which can accurately write data of analog quantity with simple constitution. CONSTITUTION:Sources of memory cells A11-C1n, C21-C2n are grounded through a resistor RW, input data Ain is impressed to drains. Storage voltage VW is applied to control gates 25 of each memory cells C11-C1n, C21-C2n. And electric charges stored in floating gates 24 of each memory cells C11-C1n, C21-C2n are extracted toward the control gates 25, when a potential difference DELTAV between a potential of the control gate 25 and a potential of the floating gate 24 is made the prescribed value, each memory cells C11-C1n, C21-C2n are turned off, and extraction of electric charges is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of storing and reading an analog amount, and a semiconductor memory device, and more particularly, to a nonvolatile memory (EEPROM: Electrically Erasable Program) capable of storing and reproducing the analog amount.
mmable Read Only Memory).

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory device (hereinafter referred to as a memory) is provided with memory cells arranged in a matrix, and "0" or "" is provided for each memory cell.
1 "information can be stored. There is a case where an analog amount of a voice signal or the like that changes with time is to be stored in this memory. In this case, the voice signal has a predetermined time. An analog amount is obtained for the sampled voice signal sampled at intervals, and an analog-digital converter (hereinafter referred to as an A / D converter) is used to convert the analog amount at each time into a resolution. Is converted into digital data consisting of a plurality of bits (for example, 8 bits) according to the
The audio signal is stored by storing each bit of the digital data in the memory cell. The stored digital data can be reproduced into the original audio signal by converting it into an analog amount using a digital-analog converter (hereinafter referred to as a D / A converter).

However, the above-mentioned method requires a plurality of memory cells for one sampled analog amount. Therefore, if an audio signal is to be stored for a long time, an enormous memory is required. Moreover, since an A / D converter and a D / A converter are required, the circuit configuration becomes large and complicated.

Therefore, a method using a non-volatile memory for directly storing the analog amount has been proposed.
This non-volatile memory is composed of memory cells composed of MOS transistors having a floating gate. The threshold value of this MOS transistor changes when charge is taken in and out of the floating gate, and this is changed to "1" of information.
Alternatively, electrical writing and erasing can be performed in correspondence with "0". In addition, the MOS transistor is
The analog amount can be stored by changing the amount of accumulated charge stored in the floating gate in response to erasing.

That is, when the write voltage of the MOS transistor is changed, charges are taken in and out of the floating gate according to the change, and the threshold value is changed according to the charges. Then, at the time of reading, according to this threshold value, M
The drain current of the OS transistor changes. Therefore,
Since the analog amount can be stored in one memory cell (MOS transistor) of the nonvolatile memory, it is possible to store a large number of analog amounts as compared with the method using the A / D converter described above.

However, in this method, even if the same write voltage is applied, the amount of charges stored in the floating gate varies from memory cell to memory cell due to variations in the memory cells. I can't.
Therefore, a method has been proposed in which the write voltage is adjusted and written for each memory cell. (Japanese Patent Publication Sho 57-1077
The analog memory write circuit described in each of the above publications includes a circuit for generating an analog amount to be written in the memory and a write pulse train whose envelope is a sawtooth wave. Generating circuit. When writing an analog amount, the source of the memory element having a floating gate is opened, the control gate is grounded, and a write pulse having a predetermined peak value is applied to the drain. After applying the write pulse, the source is grounded and a negative power source is supplied to the control gate and drain to read the written analog amount from the memory element. The read analog amount and the analog amount to be written are compared, and if the read analog amount and the analog amount to be written do not match, a new write pulse with a high crest value is applied to the memory element. That is, writing and reading are repeated a plurality of times, and when the analog amount read from the memory element and the analog amount to be written match, application of a new write pulse to the memory cell is stopped.

[0007]

However, since writing / reading must be repeated a plurality of times with respect to the memory, writing takes time depending on the analog amount. Therefore, it is necessary to lengthen the sampling time, which is not suitable for storing a continuously changing analog amount such as a voice signal. Therefore, there has been proposed a method of shortening the apparent writing time by simultaneously writing a plurality of analog amounts by using a sample hold circuit that stores a plurality of samplings in the same analog amount.

However, since the sample-hold circuit is provided, there is a problem that the number of memory cells is reduced with respect to the size of the device and the storage time is shortened. Further, since it is necessary to write the sampled and held analog quantity all at once, there is a problem that the circuit becomes complicated.

Further, since it is necessary to repeat writing / reading, a circuit for alternately switching between writing / reading is required, and the circuit becomes large in scale and complicated as well.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide an analog amount storage method capable of writing an analog amount at a high speed and with high precision with a simple structure. To aim. Moreover, it aims at providing the reading method of the analog amount memorize | stored by such a method. It is another object of the present invention to provide a semiconductor memory device using such an analog amount storage method and read method.

[0011]

According to a first aspect of the present invention, there is provided a storage method for storing an analog amount in a memory cell constituted by a transistor having a double gate structure including a floating gate and a control gate. After a certain amount of charge is injected into the floating gate from the channel side of the transistor and accumulated, the charge is extracted from the floating gate to the control gate side according to the analog amount to be stored, and the charge accumulated in the floating gate. The amount of is associated with the analog amount.

According to a second aspect of the present invention, in a storage method for storing an analog amount in a memory cell composed of a transistor having a double gate structure including a floating gate and a control gate, the drain of the memory cell transistor is grounded. After applying the first and second erase voltages to the control gate and the source to inject a certain amount of charge from the channel side to the floating gate and accumulate the charges, the source of the memory cell transistor is grounded through the current limiting element. Then, a write voltage is applied to the control gate, and a voltage according to the analog amount to be stored is supplied to the drain to extract the charge from the floating gate to the control gate side, and the amount of charge accumulated in the floating gate. Is associated with the analog amount.

According to a third aspect of the present invention, a memory cell composed of a transistor having a double gate structure consisting of a floating gate and a control gate is stored in association with the amount of charges accumulated in the floating gate. In the reading method for reading the analog amount, the resistance value generated between the source and the drain when a predetermined reproduction voltage is applied to the control gate of the memory cell transistor is taken out as a voltage value or a current value.

According to a fourth aspect of the present invention, a memory cell composed of a transistor having a double gate structure consisting of a floating gate and a control gate is stored in association with the amount of charges accumulated in the floating gate. In the reading method for reading the analog amount, the first reproduction voltage is applied to the control gate of the memory cell transistor, the source is grounded, and the second reproduction voltage is applied to the drain through a resistor having a constant resistance value. The analog amount corresponding to the amount of charges accumulated in the floating gate is read from between the drain and the resistor.

According to a fifth aspect of the present invention, a memory element having a floating gate, first erase voltage supply means for applying a preset first erase voltage to a control gate of the memory element, and Second erasing voltage supply means for applying a preset second erasing voltage to the source of the memory element, voltage supply means for applying a preset storage voltage to the control gate of the memory element, and the memory Data input means for supplying an analog signal according to the analog amount to be stored in the memory element to the drain of the element.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the fifth aspect, first reproduction voltage supply means for applying a first reproduction voltage to the control gate of the memory element, and the memory. It is composed of a second reproducing voltage supply means for applying a second reproducing voltage to the drain of the element via a resistor.

According to a seventh aspect of the present invention, a memory element having a floating gate and arranged in an array, and a case where the memory element is selected and an analog amount is stored in the selected memory element Applies a storage voltage to the control gate, applies a first reproduction voltage to the control gate when reading the stored analog amount, and applies a first reproduction voltage to the control gate when the stored analog amount is erased. A first voltage supply unit for applying a first erase voltage and a memory element selected, and in the case of storing an analog amount with respect to the selected memory element, the source is grounded through a resistor and the drain is connected. When the analog signal according to the analog amount to be stored in the memory is supplied and the stored analog amount is read out, the source is grounded and the drain is connected to the second reproduction voltage via the resistor. In the case of applying and erasing the stored analog quantity, the drain is grounded and the source is connected to the second voltage supply means for applying the second erase voltage, and the first and second voltage supply means. And a voltage generation circuit that generates the storage voltage, the first and second reproduction voltages, and the first and second erase voltages.

[0018]

Therefore, according to the first aspect of the present invention, a fixed amount of charge is injected from the channel side and accumulated in the floating gate of the memory cell transistor. After that, the charge accumulated in the floating gate is extracted to the control gate side according to the analog amount to be stored, and the amount of the charge accumulated in the floating gate and the analog amount are associated with each other.

According to the second aspect of the invention, the drain of the memory cell transistor is grounded, and the first and second erase voltages are applied to the control gate and the source, respectively.
A certain amount of charge is injected and accumulated from the channel side to the floating gate. After that, the source of the memory cell transistor is grounded via the current limiting element, the write voltage is applied to the control gate, and the voltage according to the analog amount to be stored is supplied to the drain, and the floating gate is applied to the control gate side. The electric charge is extracted, and the amount of electric charge accumulated in the floating gate is associated with the analog amount.

According to the third aspect of the invention, a predetermined reproduction voltage is applied to the control gate of the memory cell transistor, and the resistance value generated between the source and the drain is taken out as a voltage value or a current value.

According to the fourth aspect of the present invention, the first reproduction voltage is applied to the control gate of the memory cell transistor, the source is grounded, and the drain is connected to the second gate via a resistor having a constant resistance value. Is applied. Then, an analog amount corresponding to the amount of charges accumulated in the floating gate is read out between the drain and the resistor.

According to the fifth aspect of the invention, the memory cell has a floating gate, and the drain is grounded. First
The voltage supply means applies a preset first erase voltage to the control gate of the memory cell, and the second voltage supply means applies a preset second erase voltage to the source of the memory cell. , Store charge in the floating gate. The voltage supply means applies a preset storage voltage to the control gate of the memory cell, and the data input means supplies the analog signal according to the analog amount to be stored in the memory cell to the drain of the memory cell, and the analog amount. The electric charge according to is extracted from the floating gate.

According to the invention described in claim 6, the first voltage supply means applies the first reproduction voltage to the control gate of the memory cell, and the second voltage supply means applies a resistance to the drain of the memory cell. A second reproduction voltage is applied via the. Then, an analog signal corresponding to the electric charge stored in the floating gate is output from between the drain and the resistor.

According to the invention of claim 7, the memory cells have floating gates and are arranged in an array. The first voltage supply unit selects a memory cell and applies a storage voltage to the control gate of the selected memory cell when storing an analog amount. In addition, when reading the stored analog quantity, the first
The reproduction voltage of is applied. Further, when erasing the stored analog quantity, a first erase voltage is applied to its control gate. The second voltage supply means selects a memory cell,
When storing an analog amount to the selected memory cell, the source is grounded via a resistor and an analog signal corresponding to the analog amount to be stored is supplied to the drain. When reading the stored analog amount, the source is grounded and the second reproduction voltage is applied to the drain through the resistor. Further, when erasing the stored analog amount, the drain is grounded and the second erase voltage is applied to the source. The voltage generation circuit is connected to the first and second voltage supply means and generates and supplies the storage voltage, the first and second reproduction voltages, and the first and second erase voltages.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment in which the present invention is embodied in an audio storage / playback apparatus.

The voice storage / playback apparatus includes a microphone 1
Is provided. The microphone 1 inputs a voice, converts the voice into an electric signal, and outputs the electric signal. An amplifier 2 is connected to the microphone 1. Amplifier 2
Inputs an electric signal from the microphone 1, amplifies the electric signal, and outputs it as input data Ain. The input data Ain is input to the memory 3. The memory 3 is composed of a plurality of memory cells C, and the input data Ain for each predetermined time interval (sampling interval) is stored in each memory cell C.

The electric signal read from the memory 3 is output to a low-pass filter (hereinafter referred to as LPF) 4 as an analog signal. The LPF 4 inputs the analog signal output from the memory 3. The LPF 4 removes high frequency components of the input analog signal, and the amplifier 5
Output to. The amplifier 5 amplifies the input analog signal and outputs it to the speaker 6. Then, the speaker 6 converts the input analog signal into voice and outputs it.

A mode selection circuit 7 is connected to the memory 3. The mode selection circuit 7 outputs a signal according to the user's operation to the memory 3. That is, when the audio signal is to be stored in the memory 3, the user selects the storage mode. The mode selection circuit 7 generates a storage signal WR corresponding to the storage mode and outputs it to the memory 3. When the storage signal WR is input, the memory 3 stores the input data Ain input from the amplifier 2 as analog data. For example, when the input data Ain shown in FIG. 2A is to be stored, the memory 3 samples the input data Ain at every sampling interval as shown in FIG. Sin is stored in memory cell C.

On the other hand, when reproducing the audio signal stored in the memory, the user selects the reproduction mode. The mode selection circuit 7 generates a reproduction signal RD according to the reproduction mode and outputs it to the memory 3. When receiving the reproduction signal RD, the memory 3 outputs the analog sampling data Sin stored in each memory cell C to the LPF 4 as output data Aout, as shown in FIG. 2C. The LPF 4 removes the high frequency component of the output data Aout, and outputs an output signal Siut as shown in FIG. 2D to the speaker 6 via the amplifier 5. The speaker 6 receives the output signal Sout and reproduces a voice signal.

When the user wants to erase the voice signal stored in the memory, the user selects the erase mode. The mode selection circuit 7 generates an erase signal ER according to the erase mode and outputs it to the memory 3. The memory 3 uses the erase signal ER
Is inputted, the stored analog sampling data Sin is erased.

A clock generation circuit 9 and an address counter 8 are connected to the memory 3. The clock generation circuit 9 generates a clock signal CK with a predetermined pulse interval and outputs it to the address counter 8. The address counter 8 counts the pulses of the input clock signal CK, and generates and outputs the address signal ADR according to the count. The memory 3 is provided with memory cells arranged two-dimensionally and receives the input address signal A
One memory cell is determined by designating a row and a column based on DR. The address signal ADR is generated by the pulse count of the clock signal CK. That is, each memory cell is sequentially designated for each pulse of the clock signal CK. Then, the memory 3 is adapted to sequentially store the audio signal at each sampling interval by the clock signal CK, that is, the input data Ain in the memory cell.

Next, the structure of the memory 3 will be described with reference to FIG. A cell array 11 is provided in the memory 3. The cell array 11 includes a plurality of memory cells C11 to C1.
n, C21 to C2n are provided. Each memory cell C11-
C1n and C21 to C2n are MOS transistors having a floating gate, and are capable of storing analog data depending on the amount of charges accumulated in the floating gate.

The drains of the memory cells C11 to C1n are connected to the drain line D, and the sources are connected to the source line S1 to form a cell column L1. The drains of the memory cells C21 to C2n are connected to the drain line D,
The source is connected to the source line S2 to form a cell row L2. The control gates of the memory cells C11 and C21 are connected to the gate line G1 to form a row. Similarly,
The control gates of the memory cells C12 and C22 are gate lines G2.
, The control gates of the memory cells C13 and C23 are connected to the gate line G3, and the control gates of the memory cells C1n and C2n are connected to the gate line Gn, each forming a row.

The memory 3 is provided with a row decoder 12 and a column decoder 13. The gate lines G1 to Gn are connected to the row decoder 12, and the source lines S1 and S2 and the drain line D are connected to the column decoder 13.
Is connected. The row decoder 12 receives the address signal ADR and sequentially selects the gate lines G1 to Gn according to the address signal ADR. Similarly, the column decoder 13 receives the address signal ADR and selects the source lines S1 and S2 according to the address signal ADR. The memory cells C11 to C1 at the intersections of the selected gate lines G1 to Gn and the source lines S1 and S2.
n, C21 to C2n are sequentially selected. That is, the memory cells C11, C12, and C13 are first selected in this order. Then, after the memory cell C1n is selected, the memory cell C21 is selected. Then, up to the memory cell C2n is selected. Therefore,
The memory cells C11 to C1n and C21 to C2n are sequentially and continuously selected.

A voltage generation circuit 14 is connected to the row decoder 12. The voltage generation circuit 14 stores
A control signal corresponding to each mode of reproduction and erase is input, and the storage voltage VW and the reproduction voltages VR1 and VR are input based on the control signal.
2. Generate erase voltages VE1 and VE2. Then, the voltage generation circuit 14 outputs the generated voltages VW, VR1 and VE1 to the row decoder 12. Further, the voltage generating circuit 14 outputs the generated voltages VR2 and VE2 to the column decoder 13. A control signal corresponding to each mode is input from the input circuit 15.

The input circuit 15 inputs the memory signal WR, the reproduction signal RD and the erase signal ER, and inputs the respective signals WR, RD and ER.
The control signal according to is output. In the storage or reproduction mode, that is, the row decoder 12 receives the control signal according to the mode at that time and sequentially selects the gate lines G1 to Gn based on the address signal ADR. Then, the storage voltage VW and the reproduction voltage VR1 corresponding to the storage and reproduction modes are applied to the selected gate lines G1 to Gn. Therefore, the memory cells C11 to C1n, C21 to C2n
The storage voltage VW or the reproduction voltage VR1 is sequentially applied to the control gate of the.

On the other hand, in the erase mode, that is, when the row decoder 12 inputs the control signal according to the erase signal ER,
All gate lines G1 to Gn are selected at once. Therefore, the row decoder 12 applies the erase voltage VE1 to all the gate lines G1 to Gn. As a result, all memory cells C11 to C
Erase voltage V is simultaneously applied to the control gates of 1n and C21 to C2n.
E1 is applied.

The column decoder 13 has an input circuit 1
5 is connected, and the storage signal W
A control signal corresponding to R, the reproduction signal RD, and the erase signal ER is input.

The column decoder 13 has a resistor RR.
Is connected to one end, and the other end of the resistor RR is connected to the voltage generating circuit 14
And a reproduction voltage VR2 is supplied. Further, one end of the resistor RW is connected to the column decoder 13 and the resistor R
The other end of W is connected. Further, the column decoder 13
Is directly connected to the voltage generation circuit 14 and inputs the erase voltage VE2.

When the storage signal WR is input, the column decoder 13 sequentially selects the source lines S1 and S2 based on the input address signal ADR, and grounds the selected source lines S1 and S2 via the resistor RW. Has become. Further, the column decoder 13 has a drain line D
The input data Ain is applied to.

When the reproduction signal RD is input, the column decoder 13 sequentially selects the source lines S1 and S2 based on the input address signal ADR, and grounds the selected source lines S1 and S2. Further, the column decoder 13 applies the reproduction voltage VR2 to the drain line D via the resistor RR. Then, the column decoder 13 reads the input data Ain stored in the memory cells C11 to C1n and C21 to C2n via the drain line D and outputs it as output data Aout.

In the present embodiment, the memory 3 has all the memory cells C when erasing the stored analog signal.
11 to C1n and C21 to C2n are selected, and the analog data is collectively erased to form a batch erase type configuration. That is,
The memory cells C11 to C1n and C21 to C2n are sequentially selected in the storage or reproduction mode to store analog data.
The reproduction is sequentially performed, and in the erase mode, the analog data are erased by selecting them collectively. Therefore, the erasing can be performed at a higher speed than that in which the memory cells C11 to C1n and C21 to C2n are sequentially selected and erased.

Next, the structure of the memory cell C11 will be described with reference to FIG. The structure of the memory cells C12 to C1n and C21 to C2n is the same as that of the memory cell C11, and the description thereof is omitted.

FIG. 4 is a sectional view of the memory cell C11.
The semiconductor substrate 21 is an N-type semiconductor substrate, and a P-type drain region 22 and a source region 23 are formed on the semiconductor substrate 21. A channel is formed between the drain region 22 and the source region 23. A floating gate 24 is formed above the source region 23 and the channel via an insulating layer. The floating gate 24 has one end formed on the source region 23 and the other end formed so as to cover almost half of the channel. The floating gate 24 is formed so that its end portion projects higher than the center.

A control gate 25 is formed on the drain region 22 and the channel via an insulating layer. The control gate 25 is formed so as to cover almost half of the floating gate 24. The control gate 25 of the memory cell C11 is formed together with the control gate of the memory cell C21 to form the gate line G1. Similarly, the control gates of the memory cells C12 to C1n and C22 to C2n are formed together to form the gate lines G2 to Gn.

Contactors 26 are formed in the drain region 22 and the source region 23, respectively. The contactors formed in the drain regions of the memory cells C11 to C2n are connected to each other to form the drain line D. The source line S1 is formed by forming the source regions 23 of the memory cells C11 to C1n so as to be continuous in the column direction, and the source regions 23 of the memory cells C21 to C2n are formed so as to be continuous in the column direction. By doing so, the source line S2 is formed.

Next, the operations of the memory cells C11 to C1n and C21 to C2n in the erasing, storing and reproducing modes will be described in order. Since the memory cells C11 to C1n and C21 to C2n have the same structure, they operate similarly in each mode. Therefore, the operation of the memory cell C11 will be described below.
The description of the operations of 12 to C1n and C21 to C2n is omitted.

First, the operation in the erase mode will be described. FIG. 5 is a schematic diagram of the memory cell C11 for explaining the operation in the erase mode. As described above, the erase voltage VE1 is applied to the control gate 25 of the memory cell C11, and the erase voltage VE2 is applied to the source region 23. The drain region 22 of the memory cell C11 is grounded. Each voltage applied at this time is, for example, the erase voltage VE1.
(= 2V) and erase voltage VE2 (= 12V), the potential VFG of the floating gate 24 rises to a potential corresponding to the erase voltage VE2 (presumed to be about 10V in this embodiment). At this time, the channel directly below the floating gate 24 is turned on, and the channel immediately below the control gate 25 is turned on slightly. As a result, a high electric field is applied only to the central portion of the channel directly below the gates 24 and 25, and electric charges (hot electrons) are injected and stored in the floating gate 24.
As a result, a predetermined resistance value is obtained between the source region 23 and the drain region 22. In this embodiment, the resistance value of the memory cell C11 when charges are injected into the floating gate 24 in the erase mode is set to the resistance value RC, and the resistance value is set to 4 KΩ, for example.

Next, the operation of the storage mode will be described. FIG. 6 is a schematic diagram of the memory cell C11 for explaining the operation in the storage mode. As described above, the storage voltage VW is applied to the control gate 25 of the memory cell C11, and the source region 23 is grounded via the resistor RW. The input data Ain to be stored is input to the drain region 22 of the memory cell C11.

At this time, the potential of the source region 23 becomes a potential obtained by dividing the potential of the input data Ain applied to the drain region 22 by the resistance value RC of the memory cell C11 and the resistance RW connected to the source region 23. . As a result, floating gate 2
The potential VFG of 4 has a value proportional to the potential Vs of the source region 23.

For example, the memory voltage VW applied to the control gate 25 is 16V, and the resistance value RC of the memory cell C11 is 4K.
Ω, resistance RW = 1 KΩ, and the potential Vd of the input data Ain to be stored in the memory cell C11 is 5 V, the potential Vs of the source region 23 is Vs = Vd. (RW / (RC + RW)) (1) Therefore, Vs = 1V. And floating gate 2
The potential VFG of No. 4 is proportional to the potential VS of the source region 23 and becomes VFG = K.Vs = K.Vd. (RW / (RC + RW)) (2). Here, K is a coefficient, and in this embodiment, K =
If the value is 2, the potential VS of the source region 23 is 1V, so the potential VFG of the floating gate 24 is 2V.

The electric charge stored in the floating gate 24 is extracted toward the control gate 25 according to the potential difference ΔV between the potential VW of the control gate 25 and the potential VFG of the floating gate 24. That is, when the potential difference ΔV is equal to or larger than the predetermined potential difference, the charge is extracted and the resistance value RC of the memory cell C11 decreases. Then, when the potential difference ΔV reaches a predetermined potential,
The extraction of electric charge is stopped. Then, the extraction of the electric charges is completed in a time shorter than the pulse interval of the clock signal CK.

In this case, if the electric potential difference ΔV when the electric charge extraction is stopped is, for example, 13 V, the electric potential difference ΔV becomes 14 V, so that the electric charge extraction is performed. Due to the progress of charge extraction, the resistance value R of the memory cell C11
When C decreases, the potential VS of the source region 23, that is, the potential VFG of the floating gate 24, increases in accordance with the decrease of the resistance value RC.
Rises. Then, the floating gate 24 and the control gate 25
When the potential difference ΔV from and becomes 13 V, the extraction of the electric charge is stopped. At this time, the potential difference ΔV = 13V between the floating gate 24 and the control gate 25 is equal to the potential V of the control gate 25.
Since W = 16V, the floating gate VFG = 3V.
Then, from the equation (2), the potential VS of the source region 23 is = 1.
It becomes 5V.

At this time, the potential Vs of the source region 23 is 1.
Since it is 5V, the resistance value RC of the memory cell C11 is RC = RW. ((Vd-Vs) / Vs) (3), so that the resistance value RC of the memory cell C11.apprxeq.2.3 K.OMEGA.
Becomes

On the other hand, when the potential Vd of the input data Ain is 3 V, the potential Vs of the source region 23 is Vs from the equation (1).
= 0.6V, and the potential VFG of the floating gate 24 becomes VFG = 1.2V from the equation (2). As a result, the potential difference ΔV between the potential VW (= 16V) of the control gate 25 and the potential VFG of the floating gate 24 is ΔV = 14.8V. Therefore, the potential difference ΔV is the potential difference (=
13 V), the charge is extracted.

Then, when the resistance value RC of the memory cell C11 decreases due to the progress of charge extraction, the potential VS of the source region 23 rises in accordance with the decrease of the resistance value RC. Then, when the potential difference ΔV becomes 13 V, the extraction of the electric charge is stopped.

At this time, the potential VFG of the floating gate 24 is 3V.
Therefore, the potential VS of the source region 23 becomes 1.5V. Then, the resistance value RC of the memory cell C11 is calculated by the equation (3).
Therefore, RC becomes 1 KΩ.

That is, when the potential Vd of the input data Ain is 5V, the resistance value RC of the memory cell C11 is approximately 2.3 KΩ, and when the potential Vd is 3V, the resistance value R of the memory cell C11 is R.
C becomes 1KΩ. Therefore, the resistance value R of the memory cell C11
C has a potential Vd, that is, a value corresponding to the input data Ain.

Next, the operation in the reproduction mode will be described. FIG. 7 is a schematic diagram of the memory cell C11 for explaining the operation in the reproduction mode. As described above, the reproduction voltage VR1 (4 V in this embodiment) is applied to the control gate 25 of the memory cell C11, and the source region 23 is grounded.
Then, the reproduction voltage VR2 (2 V in this embodiment) is applied to the drain region 22 of the memory cell C11 via the resistor RR so that the output data Aout is output from between the drain region 22 and the resistor RR. It has become.

That is, assuming that the resistance value of the memory cell C11 corresponding to the stored analog data is RC, the output data A
out is the reproduction voltage VR2 and the resistance value of the resistance RR and the resistance value RC.
The voltage is divided by and and becomes a voltage according to the resistance value RC. The resistance value RC has a value corresponding to the input data Ain depending on the storage mode. Therefore, the output data Aou
t becomes a voltage according to the input data Ain.

Further, each memory cell C11 to C1n, C21 to C
The resistance value RC of 2n is the input data A stored in each.
Since it corresponds to in, each memory cell C11 to C1n, C21
The output data Aout respectively output from C2n corresponds to the input data Ain. Therefore, the audio signal can be stored and reproduced regardless of the variations in the memory cells C11 to C1n and C21 to C2n. Next, the operation of the audio storage / playback apparatus configured as described above will be described with reference to FIG.

First, the user operates the mode selection circuit 7 to select the erase mode. Then, the mode selection circuit 7
Is an erase signal E according to the erase mode, as shown in FIG.
Output R to the memory 3. When the erase signal ER is input to the memory 3, the memory 3 selects all the memory cells C11 to C1n and C21 to C2n, and applies the erase voltage VE1 to the gate lines G1 to Gn of the memory cells C11 to C1n and C21 to C2n and the source line S1.
, S2 is applied with the erase voltage VE2, and the drain line D is grounded. Then, each memory cell C11 to C1n, C21 to C
In 2n, charges are injected into the floating gates 24 and turned on, and the erase mode ends.

Next, the user operates the mode selection circuit 7 to store the voice signal and selects the storage mode. Then, the mode selection circuit 7, as shown in FIG.
Output R to the memory 3. At this time, the voice signal is converted into an electric signal by the microphone 1 and input to the memory 3 as input data Ain via the amplifier 2.

When the storage signal WR is input to the memory 3, the gate lines G1 to Gn, based on the address signal ADR,
Select the source lines S1 and S2. At this time, the address signal ADR changes based on the clock signal CK from the clock generation circuit 9. Then, first, the gate line G1 and the source line S1 are selected.

Then, the column decoder 13 of the memory 3 grounds the selected source line S1 through the resistor RW,
Input data Ain is applied to the drain line. And
The storage voltage VW is applied to the memory cell C11 via the gate line G1 selected by the row decoder 12. Then
Electric charges are extracted from the floating gate 24 of the memory cell C11 according to the input data Ain, and the memory cell C11 has a resistance value RC corresponding to the input data A11. As a result, a charge corresponding to the input data A11 at that time is stored in the floating gate 24 of the memory cell C11.

At the next sampling timing, the gate line G2 is selected on the basis of the new address signal ADR, and the storage voltage VW is applied to the control gate 25 of the memory cell C12.
Is applied. Then, similarly to the memory cell C11, the memory cell C12 has a resistance value RC corresponding to the input data A12. As a result, the charge corresponding to the input data A12 at that time is stored in the floating gate 24 of the memory cell C12.

The gate lines G3 to Gn are selected one after another at each sampling timing, and the charges corresponding to the input data A13 to A1n at that time are stored in the memory cells C13 to C1n.
Is stored in

When the input data Ain is stored in the memory cell C1n, the column decoder 13 next grounds the source line S2 via the resistor RW. Then, the input data Ain
In the same manner as the above-mentioned memory cells C11 to C1n, the electric charges corresponding to the input data A21 to A2n at that time are stored in the memory cell C21.
It is sequentially stored in ~ C2n. When the data is stored in the memory cell C2n, the storage mode ends.

Next, the user selects a reproduction mode to reproduce the audio signal. Then, the mode selection circuit 7 outputs the reproduction signal RD to the memory 3. When the reproduction signal is input, the memory 3 receives the address signal ADR as in the storage mode.
Based on the gate lines G1 to Gn and the source line S1
, S2. At this time, the address signal ADR
Changes according to the clock signal CK from the clock generation circuit 9. Then, first, the gate line G1 and the source line S1 are selected.

Then, the column decoder 13 of the memory 3
Connects the selected source line S1 to ground and applies the reproduction voltage VR2 to the drain line via the resistor RR. Then, the reproduction voltage VR2 is applied to the gate line G1 selected by the row decoder 12. Then, a voltage corresponding to the resistance value RC of the memory cell C11 is output as output data Aout between the drain and the resistance RR.

At the next sampling timing, the gate line G2 is selected based on the new address signal ADR, and the reproduction voltage VR2 is applied to the control gate 25 of the memory cell C12.
Is applied. Then, like the memory cell C11, a voltage corresponding to the resistance value RC of the memory cell C12 is output as output data Aout from between the drain and the resistance RR. Then, the output data Aout is output to the speaker 6 via the LPF 4 and the amplifier 5, and converted into voice.

The gate lines G3 to Gn are selected one after another at each sampling timing, and the resistance value RC of the memory cells C13 to C1n is read out and output as output data Aout. Then, the output data Aout is sequentially output to the speaker 6 via the LPF 4 and the amplifier 5, and converted into voice.

Then, when the resistance value RC of the memory cell C2n is read out and output as the output data Aout, the reproduction mode ends. As described above, according to this embodiment, the sources of the memory cells C11 to C1n and C21 to C2n are connected to the resistor RW.
The input data Ain is applied to the drain. A memory voltage VW is sequentially applied to the control gate 25 of each of the memory cells C11 to C1n and C21 to C2n so that each memory cell C11
The electric charges stored in the floating gates 24 to C1n and C21 to C2n are extracted toward the control gate 25.

The withdrawal of electric charges is stopped when the potential difference ΔV between the potential VW of the control gate 25 and the potential VFG of the floating gate 24 reaches a predetermined value, so that the memory cells C11 to C11.
The resistance values RC of C1n and C21 to C2n are values corresponding to the input data Ain. Therefore, each memory cell C11 to C1n, C
Input data A with high accuracy regardless of variations between 21 and C2n
Can remember in.

Further, each memory cell C11 to C1n, C21 to C
2n has a resistance value RC corresponding to the input data Ain and can directly memorize the analog amount. Therefore, an A / D converter is not required, and the input data corresponding to the audio signal can be accurately constructed with a simple structure. Ain can be stored. Further, since the writing and reading of the input data Ain are not repeated, the input data Ain can be stored at high speed.

Further, the gate lines G1 to Gn and the source lines S1 and S2 are selected at each sampling timing to input the input data Ain to the memory cells C11 to C1n and C21 to C2n.
Since it is stored, a circuit for sampling is not required and a simple circuit configuration can be obtained.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) In the above embodiment, the embodiment is applied to the audio storage / playback apparatus, but it is applied to the storage / playback apparatus that stores an analog amount other than audio.

2) In the above embodiment, the cell array 11
Is composed of columns L1 and L2, but the number of columns is increased. With this configuration, the number of memory cells is increased, and the time for storing the input data Ain can be lengthened.

3) Although the memory cells C11 to C1n and C21 to C2n are connected to the source line S, the source lines are separately provided and selected by the column decoder 13 according to the address signal ADR.

4) The pulse interval of the clock signal CK generated by the clock generation circuit 9 is appropriately changed according to the change of the analog amount to be stored. 5) In the above embodiment, each mode was selected by the user's operation, but the mode may be appropriately changed depending on the purpose of use. For example,
When used for storing an answering machine message, the erase / playback mode is selected by the user's operation. Then, the storage mode is selected based on the call received from the outside, and the message is stored as the input data Ain.

Further, each mode is selected by another device. 6) In the above embodiment, continuous analog signals such as voice are sequentially stored in the memory cells C11 to C2n.
One or a plurality of analog signals may be selected and stored in the memory cells C11 to C2n.

7) In the above embodiment, when the analog signal is erased, all memory cells C11 to C2n are selected and collectively erased, but the memory cell 11 is composed of a plurality of blocks. It may be divided into blocks and erased in block units.

8) In the above embodiment, the resistor RW connected to the source region 23 at the time of storing the analog signal can be a constant current resistor of a MOS transistor in addition to a normal resistance element. The resistance value of the MOS transistor with respect to the current does not have to be linear even if it has no linearity.

9) In the above embodiment, when reading an analog signal, any means can be used as long as it can take out the resistance value RC of the memory cells C11 to C2n as a voltage value or a current value. It is not limited.

Although the embodiments of the present invention have been described above, technical ideas other than the claims which can be understood from the embodiments will be described below together with their effects. 8. The semiconductor memory device according to claim 5, wherein the analog amount is a voice signal. With this configuration, the audio signal can be stored in real time.

[0086]

As described above in detail, according to the present invention, it is possible to provide an analog amount storage method capable of writing an analog amount at a high speed and with a high precision with a simple structure. It is also possible to provide a method of reading the analog quantity stored by such a method. Further, it is possible to provide a semiconductor memory device using such an analog amount storage method and read method.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment in which the present invention is embodied in an audio storage / playback device.

FIG. 2 is a waveform diagram for explaining storage and reproduction of voice.

FIG. 3 is a block circuit diagram illustrating a configuration of a memory.

FIG. 4 is a cross-sectional view illustrating the structure of a memory cell.

FIG. 5 is a schematic diagram of a memory cell in an erase mode.

FIG. 6 is a schematic diagram of a memory cell in a storage mode.

FIG. 7 is a schematic diagram of a memory cell in a reproduction mode.

FIG. 8 is a timing chart in each part of the memory.

[Explanation of symbols]

12 storage voltage supply means, first erase voltage supply means, row decoder as first reproduction voltage supply means 13 data input means, second erase voltage supply means, second reproduction voltage supply means Column decoder 14 Voltage generation circuit 22 Drain region 23 Source region 24 Floating gate 25 Control gate Ain Input data as analog signal C11 to C1n, C21 to C2n Memory cell RR, RW Resistance as current limiting element VW Storage voltage VE1 First Erase voltage VE2 Second erase voltage VR1 First reproduction voltage VR2 Second reproduction voltage

Claims (7)

[Claims] 1. A storage method for storing an analog amount in a memory cell composed of a transistor having a double gate structure including a floating gate and a control gate, wherein a fixed amount of charge is applied from the channel side of the memory cell transistor to the floating gate. After injecting and accumulating, the charge is extracted from the floating gate to the control gate side according to the analog amount to be stored, and the amount of charge accumulated in the floating gate is associated with the analog amount. How to store analog quantities. 2. In a storage method for storing an analog amount in a memory cell composed of a transistor having a double gate structure composed of a floating gate and a control gate, the drain of the memory cell transistor is grounded and the control gate and the source are respectively connected. After applying the first and second erase voltages and injecting and storing a certain amount of charges from the channel side to the floating gate, the source of the memory cell transistor is grounded via the current limiting element and the write voltage is applied to the control gate. And applying a voltage corresponding to the analog amount to be stored in the drain to extract the charge from the floating gate to the control gate side, and associate the amount of charge accumulated in the floating gate with the analog amount. A method of storing analog quantities characterized by. 3. A reading method for reading an analog amount stored in association with an amount of charges accumulated in a floating gate from a memory cell including a transistor having a double gate structure including a floating gate and a control gate. 2. A method of reading an analog quantity, wherein the resistance value generated between the source and the drain when a predetermined reproduction voltage is applied to the control gate of the memory cell transistor is extracted as a voltage value or a current value. 4. A reading method for reading an analog amount stored in association with an amount of charges accumulated in a floating gate from a memory cell including a transistor having a double gate structure including a floating gate and a control gate. At the control gate of the memory cell transistor
The reproducing voltage is applied, the source is grounded, and the second reproducing voltage is applied to the drain through a resistor having a constant resistance value, and the amount of charge accumulated in the floating gate from between the drain and the resistor. A method for reading an analog amount, which is characterized in that the analog amount according to the above is read. 5. A memory cell (C11) having a floating gate (24) and a first erase voltage (VE1) applied to a control gate (25) of the memory cell (C11). An erase voltage supply means (12), a second erase voltage supply means (13) for applying a preset second erase voltage (VE2) to the source (23) of the memory cell (C11), and A memory voltage supply means (12) for applying a preset memory voltage (VW) to the control gate (25) of the memory cell (C11) and a drain (22) of the memory cell (C11). An analog signal (A
A semiconductor memory device comprising a data input means (13) for supplying (in). 6. The semiconductor memory device according to claim 5, wherein the first reproduction voltage supply means (12) applies a first reproduction voltage (VR1) to the control gate (25) of the memory cell (C11). ) And a resistor (R) to the drain (22) of the memory cell (C11).
A semiconductor memory device comprising a second reproducing voltage supply means (13) for applying a second reproducing voltage (VR2) via R). 7. A memory cell (C11-1n, C21-C2n) having a floating gate (24) and arranged in an array, and a row of the memory cell (C11-1n, C21-C2n) are selected. , The selected memory cell (C11 to 1n, C21 to C2n)
On the other hand, when the analog amount is stored, the storage voltage (VW) is applied to the control gate, and when the stored analog amount is read, the first reproduction voltage (VR1) is applied to the control gate. , A row decoder (12) for applying a first erase voltage (VE1) to its control gate when erasing the stored analog amount, and a column of the memory cells (C11-1n, C21-C2n) The selected memory cell (C11 to 1n, C21 to C2n)
On the other hand, when storing an analog amount, the source is grounded via a resistor (RW) and an analog signal (Ain) corresponding to the analog amount to be stored is supplied to the drain,
When reading the stored analog quantity, the source is grounded and the drain is connected to the second via a resistor (RR).
And a column decoder (13) for applying a second erase voltage (VE2) to the source and applying a reproduction voltage (VR2) to the source to erase the stored analog amount. The storage voltage (VW), the first and second reproduction voltages (VR1, VR2), the first and second erase voltages (VE1, VE) are connected to the column decoders (12, 13).
A semiconductor memory device comprising a voltage generation circuit (14) for generating 2).