JPH0870325A - Decoding circuit for biphase bpsk signal - Google Patents

Abstract

PURPOSE: To provide the decoding circuit of biphase BPSK signals strong to noise by circuit constitution not using a capacitor. CONSTITUTION: Clocks corresponding to the half bit of a first half among two half bits for forming the data pair of biphase signals are prepared from the biphase signals outputted from a BPSK demodulator 1 by a pair judgement circuit 3 and a clock reproduction circuit 2 and a carrier pulse immediately after the clock is obtained by a carrier extraction circuit 5. Then, the biphase signals are AD converted in an AD conversion circuit 8 with the carrier pulse and the carrier pulse for which the pulse is delayed for the half bit period as sampling clocks. Then, by inputting timewisely sequential two pieces of the data values of the AC conversion output to a subtraction circuit 10, the subtracted result of the data pairs of the biphase signals is obtained and thus, the code judgement of the biphase signals is performed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to RDS (Radio Data Sys
tem) for decoding the bi-phase BPSK signal.

[0002]

2. Description of the Related Art A bi-phase BPSK signal is used for RDS broadcasting in which data is frequency-multiplexed and transmitted to FM broadcasting, and a bi-phase signal can be obtained by demodulating this bi-phase BPSK signal.

This bi-phase signal is as shown in FIG.
4 is used as an example of a decoding circuit for a bi-phase BPSK signal, which is a signal in which "1" is represented by "10" and "0" is represented by "01". , In the figure, the bi-phase BPSK signal is BPSK.
It is input to the demodulator 1, the BPSK demodulator 1 outputs the biphase signal of FIG. 5 (a), and the clock of FIG. 5 (b) is output from the biphase signal (a) by the clock recovery circuit 2. Is played.

On the other hand, the biphase signal (a) output from the BPSK demodulator 1 is used as a shift register in the pair determination circuit 3.
It is sequentially input to 31. Further, the clock reproduced by the clock reproduction circuit 2 is delayed by the delay circuit 37 in the pair determination circuit 3. This delay time is shorter than the clock cycle as shown in FIG. The shift register 3 in the pair determination circuit 3 is driven by the clock delayed by the delay circuit 37.
The 1 and hexadecimal counters 38 are operated. Then, two consecutive half bits of the bi-phase signal (a) sequentially input to the shift register 31 are compared every two bits.
Then, the half bit data a0 in the shift register 31,
Of a1 and a2, if a0 and a1 are the same, the output of the sukuru-shibuno age 32 is 1, and if a1 and a2 are different, the output of the quisle-shivu agate 33 is also 1,
The output of the AND gate 34 becomes 1. As a result, the RS flip-flop 36 is reset, the output of this flip-flop becomes 0, it is determined that a1 and a2 are a pair, and the delay circuit 37 is switched by the selector 39 which is switched by the output of this flip-flop 36. The LSB output of hexadecimal counter 38, which counts the delayed clock, is selected. On the other hand, if a0 and a1 are different, the output of the exclusive-sibnoage 32 is 0, and if a1 and a2 are the same, the output of the exclusive-sig oag 33 is also 0 and the output of the NOR gate 35 is 1 Becomes As a result, the RS flip-flop 36 is set, the output of this flip-flop becomes 1, and it is determined that a0 and a1 are a pair, and the selector 39 inverts the LSB output of the hexadecimal counter 38 by the inverter 30. Output is selected. Therefore, it becomes 1 when the half bit a0 in the first half of a0 and a1 which is determined to be a pair, and becomes 0 when the half bit a1 in the latter half.
The pair determination output as shown in (d) is output from the selector 39.

Next, the bi-phase signal (a) output from the BPSK demodulator 1 is integrated by the integrating circuit 4. At this time, the output (b) of the clock regeneration circuit 2 and the output (e) of the AND gate 5 which receives the output (d) of the pair determination circuit 3 become the reset signal of the integration circuit 4, and the clock signal The output (f) of the AND gate 6 that receives the reproduction output (b) and the inverted signal of the output (d) of the pair determination circuit 3 is input to the integration circuit 4
Becomes a stop signal to control the integrating circuit 4. As a result, as shown in FIG. 5 (g), if the biphase signal (a) output from the BPSK demodulator 1 is "10", the integration is performed in the positive direction, and if it is "01", the integration is performed in the negative direction. Integration is done. As a result, if the output of the integrating circuit 4 is positive,
The sign of the phase signal is 1, and the sign of the biphase signal is determined to be 0 if the output is negative.

As described above, the biphasic signal decoding method using the integrating circuit can decode even demodulated data having DC noise as shown in FIG. 5 (h), and has a high noise removing capability. is there.

[0007]

However, in the decoding circuit as described above, since the integration action of the capacitor is utilized, a large capacity capacitor is required, and the IC
There was a problem that it hindered the change.

In view of the above drawbacks, therefore, the present invention does not use a capacitor and is resistant to noise.
An object is to provide a decoding circuit for PSK signals.

[0009]

[MEANS FOR SOLVING THE PROBLEMS] A buffet according to the present invention.
Signal decoding circuit includes BPSK including carrier reproducing means.
Demodulation means, clock recovery means for recovering a clock corresponding to the half bit of the biphase signal from the output of the BPSK demodulation means, and one half bit of the data pair of the biphase signal in the output of the clock recovery means. A clock extracting means for extracting a clock corresponding to, a carrier extracting means for extracting one carrier pulse temporally after the clock output of the clock extracting means, and an output of the carrier extracting means for outputting the biphase signal. Carrier delay means for delaying a half bit period, AD conversion means for AD-converting the output of the carrier extraction means and the output of the carrier delay means as a sampling clock, and the biphase signal output of the BPSK demodulation means, and the AD conversion means. Subtracts two data values that precede and follow the output of Consisting of the calculation means.

[0010]

[Advantage] According to the above configuration of the present invention, even if noise is generated because the reproduced carrier pulse selected as the sampling clock of the AD conversion means is out of phase, the selected carrier pulse is half-converted. The phase shift of the sampling clock that is generated by delaying the bit period also becomes the same amount as the phase shift of the sampling clock of the reproduction carrier pulse, and similar noise is generated. Will be offset and removed. Similarly, the DC noise is also removed by the subtracting means.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIG. The numbers 1-3 and 31 in the figure
30 to 30 have the same configurations as the same numbers in the conventional example shown in FIG. 6, respectively, the description thereof will be omitted.

In FIG. 1, the biphase BPSK signal is input to the BPSK demodulator 1, and the BPSK demodulator 1 outputs the biphase signal of FIG. 2 (a). This biphasic signal (a) is used to generate this signal in the clock recovery circuit 2.
The clock of FIG. 2 (b) synchronized with (a) is reproduced.

On the other hand, as described above, the half-bit data a0, a1, a2 in the shift register 31 of the pair determination circuit 3 becomes 1 when the first half-bit of the two half-bits forming the data pair. , The delay circuit 37 outputs the pair determination output as shown in FIG. 2 (d) which becomes 0 in the latter half bit.
Is output from the selector 39 in synchronization with the clock (c) from. The output (d) of the pair judging circuit 3 and the clock (b) are input to the AND gate 4 to output the clock (e) corresponding to the first half bit of the data pair.

The output (e) of the AND gate 4 becomes a set input of the RS flip-flop 51 in the carrier extraction circuit 5, and the output (g) of the RS flip-flop 51 and the BP.
The carrier output (f) from the SK demodulator 1 is used as an input to the AND gate 52, and the output of the AND gate 52 is used to output the RS signal.
By resetting the flip-flop 51, the carrier pulse immediately after the clock (e) can be obtained as the output of the AND gate 52 as shown in FIG. 2 (h).

The carrier pulse (h) thus extracted from the carrier extraction circuit 5 is input to the delay circuit 6,
Create pulse (i) delayed by a half bit period. This pulse (i) and the output pulse (h) of the carrier extraction circuit 5 are input to the OR gate 7 to obtain the sampling clock (j) of the AD conversion circuit 8. The biphasic signal output (a) of the BPSK demodulator 1 is AD-converted by this sampling clock to obtain digital data (k).

On the other hand, the output data (k) of the AD conversion circuit 8 is latched by the latch circuit 9 which uses the output (i) of the delay circuit 6 as a latch pulse, and the latched data (l) and the A
By inputting the output data (k) of the D conversion circuit 8 to the subtraction circuit 10, the output of the subtraction circuit 10 is output as the section t of FIG.
The subtraction result of the half-bits of the biphase pair can be obtained like 0 to t1 or t2 to t3. Where the BPS
If the bi-phase signal output (a) of the K demodulator 1 is "01", the subtraction result in the above section is "-1", and the code is determined to be 0. If the biphase signal output (a) of the BPSK demodulator 1 is "10", the subtraction result in the above section is "1", and the code is determined to be 1. And this subtraction circuit 10
2 (n) is generated by further delaying the latch pulse (i) by the delay circuit 11 and is latched by the next latch circuit 12. Therefore, the decoded data as shown in FIG. 2 (o) is finally obtained from the latch circuit 12. If the output of the subtraction circuit 10 is not based on the subtraction of the half-bits of the biphase pair as in the section t1 to t2 of FIG. 2 (m), the above-mentioned sign determination is not performed.

The delay amount of the delay circuit 6 is f / B = 2n (n is an integer) when the bit rate of the biphase BPSK signal is B and the carrier frequency is f. Since there is always a carrier every 1 / (2B) of the time, 1 / (2B) is set.

[0018]

As described above, according to the present invention,
Since a capacitor is not used, it can be easily integrated into an IC, is resistant to noise, and can also remove noise having the same frequency as the input carrier frequency. Therefore, it is possible to reduce the size and reliability of the decoding circuit for the bi-phase BPSK signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bi-phase BPSK signal decoding circuit according to the present invention.

FIG. 2 is an operation time chart of each part of the above embodiment.

FIG. 3 is a diagram showing a bi-phase signal.

FIG. 4 is a block diagram showing a conventional bi-phase BPSK signal decoding circuit.

FIG. 5 is an operation time chart of each part of the conventional circuit.

[Description of symbols] 1 ... BPSK demodulator 2 ... Clock recovery circuit 4 ... And gate 6 ... Delay circuit 5 ... Carrier extraction circuit 8 ... AD conversion circuit 10 ... Subtraction circuit

Claims (1)

[Claims] 1. A BPSK demodulating means including a carrier reproducing means, a clock reproducing means for reproducing a clock corresponding to a half bit of a biphase signal from an output of the BPSK demodulating means, and a bi-phase output of the clock reproducing means. -Clock extracting means for extracting a clock corresponding to one half bit of the data pair of the signal, carrier extracting means for extracting one carrier pulse temporally after the clock output of the clock extracting means, and this carrier Carrier delay means for delaying the output of the extracting means by a half bit period of the bi-phase signal, and bi-phase of the BPSK demodulating means using the outputs of the carrier extracting means and the carrier delay means as sampling clocks.
A decoding circuit for a bi-phase BPSK signal, which includes AD conversion means for AD-converting the output of the binary signal and subtraction means for subtracting two data values which are before and after the output of the AD conversion means.