JPH0869698A - Memory system - Google Patents

Abstract

PURPOSE: To provide a memory system efficiently rewritable without retreating the data in an erase area at a rewriting time. CONSTITUTION: Memory chips CH1-CHk capable of simultaneously writing the data in plural pieces of memory cells on one word line by using a sense latch circuit, and an interface means 100 interfacing them with the outside are adopted, and one word line is defined one sector similarly to erasure, and the write in sector is attained. Since the unit of the write coincides with the same of the erasure, the temporarily keeping work of the data required when the data are rewritten and a retreat area for it are eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system using a non-volatile semiconductor memory device having an electric rewriting function, and more particularly to a technique effective when applied to a file memory system.

[0002]

2. Description of the Related Art Conventional nonvolatile semiconductor memory devices include, for example, Japanese Patent Laid-Open No. 62-276878 and Japanese Patent Laid-Open No. 3-276878.
A storage device called an electrical batch erase type NOR flash memory shown in No. 219496 has been developed.

FIG. 7 shows a schematic sectional view of a conventional NOR flash memory cell and its operation. In a conventional NOR flash memory cell, a gate oxide film 2, a floating gate 3, an interlayer insulating film 4, and a control gate 5 are formed on a p-type silicon substrate 1, and an n-type impurity layer 22 and a drain terminal are provided on the source terminal side. It has a floating gate field effect transistor structure in which an n-type impurity layer 23 and a p-type impurity layer 24 are formed.

In a conventional NOR flash memory, the memory cells are arranged in a matrix, the drain terminals of the memory cells are connected to data lines, the source terminals are connected to a common source line, and the control gates are connected to word lines. Was.

The control gate 5 erases the memory cell data.
By applying a negative voltage to the source impurity layer 22 and applying a positive voltage to the source impurity layer 22. At this time, a high electric field is applied to the gate oxide film 2, an electron tunnel phenomenon occurs, and the electrons accumulated in the floating gate 3 are extracted to the source impurity layer 22 side. This erase reduces the threshold voltage of the memory cell.

Data is written in the memory cell by applying a positive voltage to the drain impurity layer 23 and the control gate 5. At this time, hot electrons are generated near the surface of the drain junction and are injected into the floating gate 3.
By this writing, the threshold voltage of the memory cell becomes high.

The conventional NOR flash memory cell described above has a function of collectively erasing the entire chip or a certain fixed group of memory cells, and one transistor can constitute one memory cell. The area has been reduced by adopting a circuit configuration in which all bits are common.

On the other hand, in the conventional NOR flash memory cell described above, Fo is used for injecting and releasing electrons into the floating gate.
There is a nonvolatile semiconductor memory device using a wler-Nordheim (FN) tunnel phenomenon.

The non-volatile semiconductor memory device may be, for example, IEE Journal of Solid State Circuits, 1991 VOL SC.
-17, pp. 484-491 (IEEE JOURN
AL OF SOLID-STATE CIRCUIT
S, VOL SC-17, pp. 484-491, 19
91) Advanced Contactless E.
EP ROM (ACEE (Advanced Co
ntactless EEPROM)). ACE
The transistor used for E is a transistor having a thin oxide film region for the FN tunnel phenomenon only in the overlapping portion of the floating gate and the source, and the oxide film thickness of the transistor region is larger than that of the tunnel region. It is set thick. Also, the memory cells are arranged in a matrix, the drain terminals of the memory cells are connected to the data lines made of the impurity layers, and the source terminals are connected to the source lines made of different impurity layers. Further, the impurity layer data line and the impurity layer source line to which a plurality of memory cells are connected are respectively connected to the data line and the common source line via a MOS transistor (selection transistor).

The operation is as follows. In erasure,
A negative voltage (-11V) is applied to the selected control gate to turn on the source side select transistor, and a positive voltage (5V) is applied to the common source terminal to pass through the tunnel region on the source side of the selected memory cell. Emitting electrons from the floating gate. In writing, the drain-side selection transistor is turned on, the source-side selection transistor is turned off, the selected control gate is a positive voltage (18 V), and the non-selection control gate is a positive voltage that is not written. By applying (7V), the data line is set to 0V, the voltage on the source side is set to 0V through the memory cell in which the data line is common but the writing is not performed, and writing is performed by using the FN tunnel phenomenon. Electrons are injected from the tunnel region on the source side of the memory cell to the floating gate. Further, 7V is applied to the data line to the memory cell in which the control gate is shared with the memory cell to be written but the writing is not performed, to relax the electric field applied to the tunnel region on the source side.

In ACEE, FN is used for writing / erasing operations.
Since the tunnel phenomenon is used, the current consumption per bit is small, so that it is possible to use a booster circuit having a small current supply capability inside the chip, and a single power supply of 5 V is possible.

Further, as a non-volatile semiconductor device using the FN tunnel phenomenon, there is JP-A-4-14871. This nonvolatile semiconductor device is a floating gate type field effect transistor structure sum memory cell, the drains of a predetermined number of memory cells are connected by a sub-bit line, and the sub-bit line is connected by a sub-bit line via a MOS transistor, The source terminal is connected to the source line and commonly connected.

In erasing memory cell data, a positive voltage Vp (for example, 22V) is applied to the control gate, and the source terminal and the drain terminal are grounded to accumulate electrons in the floating gate. Further, in writing, the control gate of the selected memory cell is grounded, and the drain impurity layer is applied with a positive voltage V.
Add p. To prevent writing, Vp / 2 is applied to the drain terminal. As a result, in the selected memory cell, electrons are emitted from the floating gate to the drain impurity layer by using the tunnel phenomenon.

The nonvolatile semiconductor device using the FN tunnel phenomenon is effective in reducing power consumption because it rewrites data by using a very small current called a tunnel current.

However, in the NOR type flash memory cell shown in FIG. 7, although the memory cell structure is minute, the current consumption during writing is large and it is difficult to operate with a single power supply. That is, since the operation of writing data to the floating gate is performed by the hot carrier injection method, it is necessary to supply a current of about 500 μA per bit as a drain current for a drain voltage of 3.3 V or higher. In addition, it was necessary to guarantee the operation at the minimum power supply voltage of 2.7 V with a single 3 V power supply, and the drain terminal voltage condition for writing could not be satisfied. Further, even if the 3.3V stabilized power supply is formed by using the booster circuit in the chip, it is necessary to increase the area of the booster circuit necessary for supplying a large current for hot carriers, which is an obstacle to the reduction of the chip area. Was there.

On the other hand, the non-volatile semiconductor device using the FN tunnel phenomenon rewrites data using a very small current called a tunnel current, and is therefore effective in reducing power consumption.

However, the conventional ACEE described above is provided with the impurity layer wiring structure capable of reducing the number of contact holes per bit of the memory cell, and the memory array area is reduced, but the memory cell is reduced. It itself requires two regions, that is, a transistor region and a dedicated tunnel oxide film region that causes an FN tunnel phenomenon, and it is difficult to avoid an increase in memory cell area.

Here, let us consider a case where the floating gate field effect transistor structure described in JP-A-4-14871 is applied to the circuit configuration of ACEE in order to avoid an increase in the memory cell area. Then, in the operation shown in the above-mentioned conventional example ACEE, since the control gate selected at the time of writing data to the memory cell is 18V and the data line is 0V, the memory cell is in the inverted state, and the floating gate is formed using the entire surface of the channel. Electrons will be injected into. Therefore, it was found that the data writing time is increased as compared with the case where the transistor having the original dedicated tunnel region is used.

Further, in the operation shown in the above-mentioned conventional example ACEE, 7 V is applied to the data line to prevent writing, and the source line is charged through the unselected memory cell, but the radio wave for charging the source line is not selected. Since the current flows from the drain terminal to the source terminal of the memory cell, hot electrons are easily injected into the floating gate, and electrons are written into the non-selected memory cell. Although this is called the disturb phenomenon, it has been found that this disturb phenomenon causes a problem that the threshold voltage rises in the non-selected memory cells.

Further, it has been found that when the floating gate field effect transistor structure is used for ACEE, it is necessary to suppress variations in threshold voltage (low threshold voltage) at the time of erasing. In the erase operation, a positive voltage is applied to the source terminal and a negative voltage is applied to the control gate, so that electrons are extracted from the floating gate to the source impurity layer by a tunnel phenomenon. Since the source impurity layer region becomes the tunnel region, variations in the source impurity layer forming process lead to variations in the tunnel current. The variation in the tunnel current is larger than that in the structure in which the tunnel region is dedicated. As a result, when trying to erase all the memory cells on the same word line at the same time, the erase time varies due to the variation of the tunnel current, and the erase voltage is applied excessively to the memory cell erased earliest. , The threshold voltage might become negative. It has been found that it is difficult to realize a large-scale memory array because the variation in the source impurity layer forming process, which causes the increase, increases as the size of the memory array increases.

As described above, although the circuit configuration of ACEE is effective, there is a problem in realizing ACEE simply by using the floating gate type field effect transistor structure in terms of write characteristics, disturb characteristics, and large-scale memory array. It was revealed by the inventor's examination that there is.

Further, considering the non-volatile semiconductor device described in Japanese Patent Laid-Open No. 4-14871, although it has the possibility of high integration and high-speed reading, the following problems occur in terms of large scale memory array. I knew it was.

In order to promote miniaturization, a sub-bit line structure of silicide or refractory metal is used.
Since it is necessary to provide one contact region for each bit, it is necessary to reduce the effective memory cell area.

Since the erase operation is performed by applying a positive voltage Vp to the control gate and grounding the source terminal and the drain terminal, the write operation is performed by grounding the control gate and applying the positive voltage Vp to the drain impurity layer. The deterioration of the tunnel oxide film near the source region is severe,
The radio wave driving capability β of the memory cell is greatly reduced. More specifically, when the control gate of the write operation is grounded and a positive voltage Vp is applied to the drain diffusion layer, among the electron-hole pairs generated at the drain end, holes are formed in the gate oxide film according to the direction of the electric field. Injected. When the number of rewrites is small, the amount of injected holes is small, and the deterioration is only at the drain end, which does not decrease β of the memory cell, but when the number of rewrittens increases, the amount of injected holes also increases. And the deterioration spreads from the drain edge to the vicinity of the source. Therefore, it is difficult to guarantee the rewriting operation of 10 ⁵ times or more, which is required in the large capacity file memory.

In view of the above circumstances, the present inventor provides an electrically rewritable nonvolatile semiconductor memory device which consumes less power, operates at high speed, and has a reduced effective cell area. For that purpose, a nonvolatile semiconductor memory device having the device structure shown in FIG. 1, for example, was previously proposed.

The content of the proposal is, as shown in FIG. 1, that the semiconductor substrate has a source region 6 and a drain region 7 which are provided separately from each other, and has a uniform film thickness from the surface of the source region to the surface of the drain region 7. An element of the MOSFET 1 including a floating gate electrode 3 formed by starting the gate insulating film 2 having the above and a control gate 5 formed on the floating gate electrode 3 via an interlayer insulating film 4 is used as a memory cell. A non-volatile semiconductor memory device includes a memory array in which a plurality of memory cells are arranged in a matrix of rows and columns, and drain regions of the plurality of memory cells on the same column are connected to data lines formed in each column. The control gates of the memory cells connected to the same row are connected to the word line formed for each row and electrically rewritable. When performing the write operation, a voltage of the first polarity is applied to the semiconductor substrate 1 in the drain region 7 of the memory cell which is the target of the write operation, and the control gate 5 of the memory cell is also used.
Is applied to the semiconductor substrate 1 with a voltage having a second polarity different from the first polarity to make the source region 6 of the memory cell have the same potential as the substrate potential. A voltage of the first polarity is applied to the semiconductor substrate 1 to the control gates 5 of a plurality of target memory cells, and all the other electrodes and the semiconductor substrate 1 have the same potential.

This technique achieves low power consumption by the writing and erasing method using the tunnel phenomenon. On the other hand, the miniaturization of the memory cell area is achieved by the memory cell structure shown in FIG.

In erasing, a voltage of the first polarity is applied to the control gate 5 to bring the source region 6 and the drain region 7 to the same potential as the substrate, so that F-N is passed through the gate oxide film 2.
A tunnel phenomenon occurs and electrons are injected into the floating gate 3 from the entire surface of the memory cell channel. This raises the threshold voltage of the memory cells on the same row. Further, by selecting a plurality of word lines at once, the memory cells whose control gates are connected to the plurality of word lines can be erased collectively. In the main erase, unlike the above-mentioned ACEE write operation, since the source line is not charged through the memory cell in which the data line is not written by applying the voltage having the first polarity, the charge current of the source line, etc. There is no problem of hot carrier deterioration due to.

In writing, a voltage of the second polarity is applied to the control gate 5, a voltage of the first polarity is applied to the drain region 7, and the source region 6 is made to have the same potential as the substrate potential, whereby the gate oxide film is formed. F-N tunnel phenomenon occurs through 2 and electrons are emitted from the floating gate 3 to the drain diffusion layer side by using the overlap region of the drain diffusion layer 7 and the floating gate 3 (hereinafter, referred to as drain diffusion layer edge region). , The threshold voltage of the memory cell is low. Writing is performed in word line units, and the voltage of the data line connected to the memory cell to be written is set to the voltage of the first polarity, and the memory cell not to be written is connected to it. By setting the voltage of the data line to be the same as the substrate potential, the desired memory cell is written.

At the time of reading, the selected word line is set to the first
And the non-selected word line has the same potential as the substrate potential. A written memory cell is turned on and a current flows, but a memory cell not written is turned off and a current does not flow. Therefore, the on / off state of the memory cell can be obtained by observing the current or voltage flowing through the data line using the sense amplifier connected to the data line.

[0031]

The above-mentioned contents proposed by the inventor of the present invention enable writing and erasing in units of word lines. In the NOR flash memory, the erase unit is larger than the write unit. Focusing on this point, the present inventor has studied how to apply the previously proposed nonvolatile semiconductor memory device to a file memory system to realize high-speed rewriting operation and physical circuit scale reduction.

An object of the present invention is to provide a memory system capable of efficiently rewriting data in the erase area without temporarily saving it in an external buffer area when rewriting. Another object of the present invention is to provide a memory system capable of realizing its function with a general-purpose microprocessor without requiring a complicated interface even when applied to a file memory system in which data is managed in sector units. It is in. Another object of the present invention is to provide a memory system capable of realizing a data cache function at the time of rewriting and reading in order to speed up data processing.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0034]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of semiconductor memory chips (CH1, CH2, ...) And control means (10) connected to these chips for controlling the operation of the chips.
0; 200) and an electrically erasable and writable non-volatile semiconductor memory system is shown below.
With the configuration of. A plurality of memory blocks (BLK1, BLK) having a plurality of semiconductor memory cells arranged in rows and columns, respectively.
2, ...) divided into memory cell arrays (31) in which each memory cell has a source and drain region formed on a semiconductor substrate, and a gate insulation formed on the semiconductor substrate between the source and drain regions. film,
A plurality of memory cells on one column including an insulated gate field effect transistor structure having a floating gate formed on the gate insulating film and a control gate formed on the gate insulating film via an interlayer insulating film , The drain region of the transistor structure is connected to one data line (D), the control gates of the transistor structures of a plurality of memory cells on one row are connected to one word line (W), The source regions of the transistor structures of the memory cells on a column are connected to each other. A plurality of common source lines (1) provided on the memory block, extending in the row direction and formed on the substrate.
7). A first selection transistor having a plurality of source and drain regions formed in a semiconductor substrate and a gate electrode formed between the source and drain regions via an insulating film on the semiconductor substrate in a row direction. A plurality of selection insulating field effect transistor rows (16, 19) are provided, and one of these first selection insulating field effect transistor rows is provided to each of the memory blocks. A transistor is provided for each column of a memory block and corresponds to the commonly connected source region of the transistor structures of the memory cells of that column.
It is connected to the common source line of the book. A second selection transistor having a source and drain region formed in the semiconductor substrate, and a plurality of selection transistors each having a gate electrode formed between the source and drain regions on the semiconductor substrate via an insulating film in a row direction. A plurality of selection insulating field effect transistor rows (15, 20) are provided, and one of these second selection insulating field effect transistor rows is provided for each of the memory blocks. A transistor is provided for each column of a memory block, and a transistor corresponding to a drain region of a transistor structure of a plurality of memory cells in a column is provided.
The connection with the data line of the book is made. In order to collectively write to a plurality of memory cells connected to one word line which is a target of batch erasing, 1-bit write / read data on each data line is controlled as described above. A plurality of latch circuits for storing under the control of the means, each of which is separately connected to a respective data line (3
3) is provided.

In order to control the rewriting sequence by an externally applied command or instruction to reduce the control load of the external host system, each semiconductor memory chip has an internal controller (CTRL) which responds to the output of the control means. ) Is provided, the memory cell unit area of the memory cell array for the batch write operation is equal to the memory cell unit area of the memory cell array for the batch erase operation, and the batch write operation and the batch erase operation are controlled by the internal controller. It is better to let them do it below.

In order to facilitate the memory interface with the host system, the control means transfers the write / read data to the semiconductor memory chips (CH1, CH2, ...).
A data bus transceiver (10
1) and an address decoder (1023) for selecting one of the memory chips may be further provided, which interface means may be constituted by a microprocessor (200).

In order to shorten the occupied time of the system bus and the host system at the time of rewriting, a plurality of memory cells connected to one selected word line are supplied via the latch circuit (33). Write data buffer memory (11) for storing write data to be written.
0) is further provided, and this write data buffer memory is set to 1
The memory interface means itself is provided with a data cache function by having a storage capacity substantially equal to n times (n is a positive integer) the storage capacity of a plurality of memory cells connected to one word line. Good to realize. Further, if the data cache function during read operation is also considered, read / write for storing read / write data
A write data buffer memory (110) is provided, and this read / write data buffer memory is supplied to a plurality of memory cells connected to one selected word line via the latch circuit (33). For storing write data to be written is provided with a storage area having a storage capacity substantially equal to n times (n is a positive integer) the storage capacity of a plurality of memory cells connected to one word line. It is desirable to do. The write data buffer memory (11
0), when the current write data is transferred to the latch circuit (33), stores the next write data under the control of the control means regardless of whether the current write data has already been written. Can be arranged as

[0039]

According to the above-mentioned means, the latch circuit provided in the chip is provided so as to have a size comparable to the erase / write data size. In other words, the write and erase units are matched. Therefore, the temporary storage work of the data, which was required at the time of rewriting the data, is unnecessary. This realizes the omission of the buffer memory therefor and further enables the continuous operation of erasing and writing. In other words, since the erasing unit is larger than the writing unit in the past, it was necessary to temporarily save the data in the erasing area to the external buffer area in order to rewrite the data. Since the unit and the writing unit are the same, it is not necessary to save the erase area data. as a result,
Erasing / writing can be performed on one word line by one-time address input and data transfer. This also makes it possible to convert the rewriting operation into one command.

Since the size of the sector buffer composed of the latch circuit is at least the same as the size of erase / write, it is sufficient to transfer the data of the system bus to the sector buffer in the chip, and an easy interface by a one-chip microcomputer. Allow control. Utilizing such a microprocessor for the interface means reduces the number of parts on the card when the present memory system is deployed on the card.

The use of a buffer memory capable of prefetching data (successive rewriting) allows the addresses and data for a plurality of chips to be sent in advance and latched and stored, while the external bus is opened to the host side. On the other hand, it enables another work. Further, parallel rewriting is also possible for mutually different chips, which contributes to an increase in rewriting speed.

[0042]

【Example】

<< Memory Cell Device and Flash Memory >> First, before describing the memory system according to the present invention, a nonvolatile semiconductor memory device used therein and a memory cell device for constituting the same will be described.

The device structure (transistor structure) of the memory cell described first is shown in FIG. 1, FIG. 2 shows its circuit configuration, FIG. 3 shows the block configuration of a non-volatile semiconductor device, and FIG. Is a plan view of the memory cell configuration,
5 is a sectional structure view taken along the line AA ′ in the plan view of FIG. 4, and FIG. 6 is a sectional structure view taken along the line BB ′ in the plan view of FIG.

It should be understood that FIG. 1 described above is a simplified diagram of the transistors in the region surrounded by the broken line shown in FIG. 5 for explaining the operation of the memory cell described here. The actual memory cell structure of FIG. 5 will be described. FIG. 5 shows a 2-bit memory cell having the same word line. A gate insulating film 53 having a uniform film thickness of about 7 nm is formed on the p-type semiconductor substrate 52. A first floating gate electrode 54 is formed on the gate oxide film 53, and an insulating film 55 is formed on the side surface of the first floating gate electrode 54. A second floating gate electrode 56 that is electrically connected to the first floating gate electrode is formed. A control gate 58, which becomes a word line, is formed on the second floating gate electrode 56 via an interlayer insulating film 57. About 15n in terms of silicon oxide film for the interlayer insulating film
m insulating film is used. The second floating gate electrode 56 is designed to have a larger area than the first floating gate electrode 54,
The capacitance between the second floating gate 56 and the control gate 58 is increased. The first floating gate electrode 54 is patterned to the gate length of the memory cell. An n-type source region 62 and a drain region 61 are formed in self-alignment with the first floating gate electrode 54. Source area 6
2, a p-type diffusion layer region 64 is formed deeper than the n-type impurity diffusion layer forming the source region 62, and an n-type impurity region 63 for diffusion layer wiring in the source region is formed.
In the p-type diffusion layer region 64, the gate length of the memory cell is 0.4.
It functions as a punch-through stopper required in the micron or less and is used for adjusting the threshold voltage of the thermal equilibrium state of the memory cell. Since electrons are tunnel-emitted using the overlapping region (drain diffusion layer edge) between the drain region 61 and the floating gate 54, the impurity concentration of the n-type impurity diffusion layer forming the drain region 61 is set to n forming the source region 62. It is set higher than the impurity concentration of the type impurity diffusion layer. For example, the drain region 61 is formed by arsenic ion implantation and has a surface concentration of 10 ²⁰ / cm 2.
It is set to ³ or more.

FIG. 2 shows a basic circuit of two blocks with n (for example, 16 to 128) word lines as one unit. Here, n memory cells form one group 11 and one word line is connected to memory cells corresponding to m data lines, and m × n memory cells form one block. Function. The data line and the memory cell are connected to the data line by forming a contact hole region 12 for each group. That is, the memory cells are connected in parallel, and the drain and source terminals of the memory cells are the first common wiring formed by the n-type impurity region, that is, the drain diffusion layer wiring 13 and the second common wiring that are the source diffusion layers. The wiring 14 is used for connection. Each data line 18 is wired by a metal having a low resistance value, and is connected to the drain diffusion layer wiring (sub-data line) 13 in the block via the row of the selection transistors 15 and 20 formed of n-type MOS transistors (IGFET). . The drain terminals of the n memory cells are connected to the drain diffusion layer wiring 13 and the source terminals thereof are connected to the source diffusion layer wiring (sub-source line) 14. Here, the resistance value of the drain and source diffusion layer wiring is, for example, 50 to 500 ohms / square. Source diffusion layer wiring 1
Reference numeral 4 is connected to a common source line 17 through a row of selection transistors 16 and 19 each composed of an n-type MOS transistor (IGFET).

The number m of data lines connected to one word line is, for example, a multiple of 512. Because
This is because, if an alternative application of the current fixed storage device is considered, it is easy to handle a multiple of one input / output device (I / O). The number n of word lines largely depends on the electrical characteristics of the memory cells to be formed and the resistance value of the diffusion layer wiring. When the number of word lines connected to the data lines is 8192, for example, the number of select transistors is 8
Since 192 / n × 2 pieces are required, the area occupied by the selection transistors can be suppressed as n is increased. But,
When n becomes large, the resistance value of the diffusion layer wiring cannot be ignored, and the read characteristic of the memory cell is deteriorated. Here, 32-128 are used as n.

By arranging the memory cells in an array as shown in FIG. 2, reduction of the chip area can be promoted.

The block configuration of the nonvolatile semiconductor memory device chip will be described with reference to FIG. On the non-volatile semiconductor memory device chip, a data array latch circuit 33 is connected to the memory array section 31 and each data line 32 connected to the memory array shown in FIG. To be done. The common data line is connected to the input / output circuit. Although not shown, an external input power supply terminal having a single voltage level is provided on the same substrate. It should be noted that a latch circuit, a decoder, a common data line, and an input / output circuit can be provided for other memory arrays formed in the same chip. Reference numeral 39 denotes a sense latch circuit, which includes the latch circuit 33 and an amplifier (not shown) that detects and amplifies the read data.

The drive lines of the select transistors for selecting the word lines and blocks connected to each memory block are connected to the decoders 35 and 36, respectively. The decoders 35 and 36 include a high voltage generation circuit (boost circuit) 37.
And a negative voltage generating circuit 38 are connected. Thus, the high voltage from the booster circuit 37 is selectively applied to the selected word line at the time of erasing, and the negative voltage generating circuit 3 at the time of writing.
A negative voltage from 8 is applied to the selected word line.

Boosting circuit 37 and negative voltage generating circuit 38
Is composed of, for example, a charge pump type voltage conversion circuit, and can generate a high voltage or a negative voltage from a single power supply voltage of 3.3 V or less.

With reference to FIG. 18, the voltage relationship of the signal line in each operation of data erasing, writing and reading in this embodiment will be described. FIG. 8 shows an example of erasing, writing and reading for the word line W12 of FIG. The erased state means that the threshold voltage of the memory cell is in a high state such as 3.3 V or higher, and the written state means that the threshold voltage is in the range of 0.5 to 1.5 V, for example. .

First, for erasing, it is necessary to activate the block 1 (BLK1) including the word line W12. In order to turn on at least one of the selection transistors 15 and 16, SD1 and SS1 are set to 3.3V. At this time, the signal lines SD2 and SS of the other blocks
2 is 0V. With respect to the word line in the selected block, 12V is applied to W12 and all other word lines are set to 0V. At this time, set the voltage of all data lines to 0V
As a result, 6 to 8 V, which is a voltage obtained by capacitively dividing the control gate voltage and the channel voltage, is applied to the floating gates of all the memory cells connected to W12. As a result, a high electric field is applied to the gate oxide film between the floating gate and the channel region, an FN tunnel current flows, electrons are injected into the floating gate, and the threshold voltage of the memory cell is set to 3.
Can be 3V or higher. The erase time is about 1 millisecond. Since the memory cells on other word lines are not erased, only the memory cells on one word line can be erased, and for example, 512-byte unit erase (sector erase) can be performed. Also, by simultaneously selecting a plurality of word lines, it is possible to simultaneously erase multiple sectors.

For writing, first, data is transferred from the input / output circuit to the latch circuit 33 (included in the sense latch circuit 39 of FIG. 3) provided on each data line. Then W
In order to activate the block 1 (BLK1) including 12, SD1 is set to a voltage of 3.3 V or higher. At this time,
SS1 is set to 0V to electrically isolate the source line in the block from the common source line 17. Non-selected block (BLK
SD2 and SS2 in 2) are set to 0V to disconnect the non-selected block (BLK2) from the data line. For the word line in the selected block (BLK1), W12 is -7V
And all other word lines to, for example, 3.3 of the power supply voltage.
V. The diffusion layer wiring in the block has 0 V according to the information in the latch circuit 33 connected to each data line.
Or, for example, 3.3V is applied. When the drain terminal of the memory cell is 3.3V, a high electric field is applied to the gate oxide film between the drain diffusion layer and the floating gate, electrons in the floating gate are extracted to the drain terminal, and the threshold voltage of the memory cell is increased. Can be 1 V or less. When the drain terminal is 0 V, the absolute value of the floating gate voltage calculated from the capacitive coupling is small, the tunnel phenomenon through the gate oxide film does not occur, and the threshold voltage of the memory cell does not change. Here, all the word line voltages of the non-selected blocks are 0V
However, the present invention is not limited to this, and for example, a power supply voltage of 3.3 V may be applied.

In this writing operation, the time for extracting electrons, that is, the writing time is divided into, for example, 30 and the threshold voltage of the memory cell is verified every time writing is performed, and the latch circuit provided for each data line is provided. Compare with the data in.
If the threshold value is less than a predetermined value (for example, 1V), the data in the latch circuit is rewritten (from 3.3V to 0).
V), so that subsequent writing is not performed. Further, if the threshold value is equal to or more than a predetermined value (for example, 1V), further 1
Add write once. That is, when the threshold voltage of the memory cell reaches the predetermined low threshold voltage state, the voltage of the latch circuit 33 becomes 0V, so that in the subsequent writing, the voltage of the drain diffusion layer 7 becomes 0V, and the electron The tunnel phenomenon does not occur. By repeating this flow, it is possible to write data in all the memory cells existing on one word line and requiring writing without variation. As a result, the threshold voltage of the memory cell can be controlled to 0.5 to 1.5 V, and low threshold voltage variations can be suppressed even when writing is performed simultaneously on multiple bits. As a result, the influence of the variation on the low threshold voltage as shown in ACEE can be avoided in this embodiment.

As described above, the threshold voltage can be lowered only for the memory cell to which 3.3V is applied to the data line, and the data writing is performed. The time required for the writing is about 1 millisecond. The voltage applied to the data line is determined from the disturb characteristics for the memory cells that are not programmed on the same word line. That is,
In a cell in which programming is not performed, 0 V is applied to the drain terminal and -7 V is applied to the word line, so that electrons are gradually emitted from the floating gate. In order to suppress the emission of electrons in the non-written cell, it is necessary to increase the difference in drain voltage between the written cell and the non-written cell. In this embodiment, 3.3V is used, but 3.V is used.
By using a voltage of 3 V or higher, the absolute value of the word line negative voltage can be reduced, and the decrease in the threshold voltage in the non-written cells can be suppressed.

In this embodiment, the word lines (W11, W1 in FIG. 12) of the non-selected memory cells in the selected block at the time of writing are written.
A voltage of 3.3V is applied to n). This is to improve the operation margin of the memory cell. The voltage applied to the unselected word line is determined depending on the number of times of rewriting of the memory cell. When a non-selected memory cell has a high threshold voltage, a very small tunnel current flows from the floating gate to the drain terminal, electrons are extracted from the floating gate, and as a result, the threshold voltage drops and erases. You may not be able to hold the level. The total rewrite time received by an unselected memory cell is 31 when all other word lines in the same block are rewritten 1,000,000 times.
1 million times x 1 millisecond = 31,000 seconds (n = 3
2 is assumed). It is necessary that the data in the memory cell be retained at least within the above time. When the threshold voltage of the memory cell in the thermal equilibrium state is high, the data is retained even if the voltage of the non-selected word line is set to 0V. In this case, in order to reduce the electric field between the floating gate and the drain terminal, it is necessary to set the voltage of the non-selected word line to 1 V or higher. As described above, it is necessary to apply a positive voltage to the non-selected word line in order to expand the design range of the threshold voltage in the thermal equilibrium state of the memory cell. 3.3V is used.

Since the voltage applied to the non-selected word lines is 3.3 V as described above, it is necessary to separate the source line for each data line in the nonvolatile semiconductor memory device of the present invention. Because the group 1 of the memory cells shown in FIG.
When the threshold voltage of the memory cell connected to the non-selected word line in 1 is low, the non-selected word line is turned on because it is 3.3 V, and is applied to the drain terminal (drain side diffusion layer wiring). Voltage is supplied to the source side. Therefore, if the source terminals are common, the source voltage rises or an excessive drain current flows.

However, if the source wiring is separated for each unit data line, the junction capacitance of the source wiring extending in parallel with the data line becomes large, and in order to charge the separated source wiring, on the non-selected word line. The charging current will flow through the memory cell having the low threshold voltage. When this charging current flows, hot electrons are generated in the memory cell and are injected into the floating gate, causing the threshold voltage to rise and inverting the data. Therefore, as shown in FIG. 2, in this example, not only the source line 14 is separated for each data line, but also a plurality of word lines are divided into n groups (n = 16 to 128) as a group to form a group 11 By connecting the source diffusion wiring layer 14 of each group to a common source line via the selection transistors 16 and 19 and the drain diffusion wiring layer 13 to each data line, the capacitance on the source wiring side is reduced. The amount of charging current flowing through the memory cell having a low threshold voltage is reduced to prevent data inversion.

In the above description, the case where the design range of the threshold voltage in the thermal equilibrium state of the memory cell is widened, but when the threshold voltage in the thermal equilibrium state is optimized, the voltage of the non-selected word line is Data can be held even when 0V is set to 0V, the source terminal need not be separated, and the selection transistor connected to SS1 can be omitted.

Read is block 1 containing W12
In order to activate the above, SD1 and SS1 for the selection transistors 15 and 16 are set to 3.3V or more. For the word lines in the selected block, 3.3V is applied to W12 and all other word lines are set to 0V. A constant read voltage is applied to the data line. At this time, when the threshold voltage of the target memory cell is low, the voltage of the data line is lowered, and when it is high, the voltage is held at a constant voltage. The memory cell data can be determined by reading out to 33.

The plane structure and sectional structure of the memory cell device will be described with reference to FIGS. As shown in FIG. 4, an element isolation region 42 is formed in the direction of the data line 41, and the metal wiring 41 forming the data line is connected to a selection transistor (for example, 1 in FIG. 2) via a contact hole 43.
It is connected to the drain diffusion layer 44 of 5). The drain diffusion layer 44 is connected to the drain diffusion layer in the memory cell block via the gate 45 of the selection transistor. The transistor region of the memory cell is a region where a region 46 (outer side surrounded by a frame) defining the first-layer floating gate and a region 47 defining a word line intersect. The floating gate of the memory cell has a two-layer structure, and the floating gate of the second layer is defined by the region 48. A diffusion layer wiring region is formed between the region 46 and the element isolation region 42, and a source side diffusion layer region is formed so as to face the drain side. The source side diffusion layer region is a select transistor (eg, 16 in FIG. 2).
Is connected to the common source region 50 via the gate 49 of the.

FIG. 5 is a sectional view taken along the line AA 'in the plan view of FIG. 4, and FIG. 6 is a sectional view taken along the line BB'. Each memory cell area has a LOCOS (Local Oxidation of Silicon)
n) It is isolated by the element isolation region 51 formed of an oxide film. The floating gate is formed by a two-layer structure, and its purpose is to increase the capacitive coupling value between the floating gate electrode and the word line and lower the write / erase voltage.
Therefore, when importance is attached to process simplification, the floating gate 56 is not necessarily formed. Although the memory cell of this embodiment is formed on a p-type silicon substrate,
It can also be formed on a p-type well region formed by a CMOS process on a p-type silicon substrate and on a p-type well region on an n-type silicon substrate. In the cross section (FIG. 6) parallel to the data lines, the word lines are formed with the minimum processing size and at equal intervals, and the first and second floating gates 54 and 56, the interlayer insulating film 57, and the control gate 58 that becomes the word line. Has a laminated structure. The word lines are separated by a p-type impurity region 76 introduced by ion implantation.

In the above example, AA 'parallel to the word line is used.
With a length about 3 times the minimum processing dimension on the surface, B-
On the B'side, a 1-bit memory cell is formed with a doubled length. That is, under the minimum processing accuracy of 0.35 micron, the memory cell area can be set to about 0.74 square micron.

The basic operations of erasing, writing, and reading of data in the block of the nonvolatile semiconductor memory device have been described above. A nonvolatile semiconductor memory device using these is further described with reference to FIGS. 20 to 27. Add.

FIG. 20 shows details of the block configuration of the chip 81 including the nonvolatile semiconductor memory device shown in FIG. 3, peripheral circuits connected thereto, means for controlling them, and the like.
The memory array unit 31, the sense latch circuit 39, and the decoder 34 are divided into eight, for example, here according to the parallel degree of the input / output circuit 76, and the chip 8 is provided via the input / output circuit 76.
1 It is electrically connected to the outside. Memory array unit 31
In, 512 bytes of memory cells are connected to one word line. As described above, current fixed storage devices mainly handle data in units of 512 bytes, so 512 word memory cells are connected to one word line, but the number of memory cells on the word line is Needless to say, it can be appropriately changed depending on the application of the nonvolatile semiconductor memory device chip. Reference numeral 11 is a cell group similar to the cell group shown in FIG. 2, and indicates one of the cell groups included in the cell block received by one decoder 35. Therefore, although not shown in FIG. 20, between the cell groups belonging to the adjacent cell blocks, the selection transistor 15 shown in FIG.
Selection transistors similar to 16, 19, and 20 are provided. In consideration of redundant memory cells, 512 bytes + redundant bit memory cells can be connected to each input / output circuit. The address signal A is stored in the address buffer / latch 77, is transmitted to at least the decoders 35 and 36, and one word line is selected.

In the random access operation, the input address signal A is transmitted to the decoders 34, 35 and 36, but in the serial access operation, the input address signal A is input to the decoder 3.
5 and 36, the serial clock SC
To the serial clock buffer 78 and the internal address signal generated by the address counter 79 is transferred to the decoder 3
It is transmitted to 4. In random access, the decoder 34 decodes the address signal supplied from the address buffer / latch 77 and selects the latch circuit or the data line of the bit corresponding to the data input / output unit in the input / output circuit 76. In serial access, the address signal output from the address counter 79 is sequentially decoded to sequentially select one sector of the latch circuit 33 or the data line for each data input / output unit in the input / output circuit 76. CTRL is an internal controller.

FIG. 21 shows a timing chart for basic input data when rewriting data. After the chip is selected and an external command such as reading or rewriting is accepted, each operation is started. An example of the rewriting operation executed under the control of the internal controller CTRL based on the external control signal C will be shown below, but it goes without saying that data erasing, writing, and the like can be similarly executed. Generally, various signals related to rewriting are input at the time of rewriting, but a portion not essential to the present invention is omitted.

First, a chip is selected and a rewrite command (C) is issued.
Is input, and further the address signal A is input (I). The erase word line is selected according to the input address signal A, and the erase is performed by the above-described method. That is, the high voltage generating circuit 37 outputs about 1 to the selected word line.
A high voltage of 2V is applied, and the 512-byte memory cells on the word line are collectively erased. In order to confirm that the memory cell on the word line is in the erased state, for example, 5 V is applied to the word line and about 1 V is applied to the data line, and the threshold voltage is judged and verified. Repeat (II) until all bits on the selected word line are erased. Then, data is serially input from the I / O terminal in a length of 512 bytes. The input data is sequentially stored in the latch circuit 33 in the sense latch circuit 39 in synchronization with the serial clock SC (III). Since the data input is transferred at intervals of 50 to 100 ns, the time t3 required for the data input (III) is 100 μs at most. When the data transfer is completed, the process moves to data writing (IV). Negative voltage generating circuit 38 applies -7V to one word line corresponding to the selected address, and the data line is selected according to the data stored in latch circuit 33 corresponding to each bit in sense latch circuit 39.
3V or 0V is applied. The writing (t41) and the writing verification (t42) are performed as described above, and the rewriting is completed.

As described above, unlike the conventional NOR type operation, there is no need for a weak write operation called prewrite before the erase operation.

As described above, since the erasing is performed by the tunnel injection through the gate oxide film, the high voltage generating circuit 3
7 makes it possible to set the threshold voltage of the memory cell after erasing sufficiently high by increasing the voltage applied for erasing. In this case, as shown in FIG.
Verification of the erased state of memory cells after erasing becomes unnecessary,
The verification process can be omitted. In addition, since the latch circuit 33 occupied for reading the memory cell data is released for the verification process after erasing, the rewriting data can be transferred after the address is input. That is, FIG.
As shown in 3, the address input (I) is followed by the data input (III), and 512 bytes can be serially input. As a result, since it is possible to continuously perform from the address input to the data input without waiting for the erasing time, the occupation time of the external I / O can be reduced.

On the other hand, in FIG. 22, data input (III)
Is performed between the I / O terminal and the latch circuit 33, and the erase (II) is performed on at least one word line in the memory array 32. Therefore, as shown in FIG. Data input under control (I
II) and erase (II) can proceed at the same time.

Since data can be erased and written for each word line in this manner, the erase unit and the write unit can be matched, and this can be treated as a sector.
In the conventional NOR flash memory, the erase unit is larger than the write unit. Therefore, in order to rewrite the data, it was necessary to temporarily save the data in the erase area to an external buffer area. Since the unit and the writing unit are the same, it is not necessary to save the erase area data. As a result, erasing / writing can be performed on one word line by one address input and serial data transfer, and the rewriting operation can be unified into one command.

Further, as shown in FIG. 25, the memory array section 31 shown in FIG.
By adding the address latch 83, the rewriting shown in FIG. 23 can be processed in parallel. This is achieved by dividing the memory array section 31 into array blocks 84 and 85, and the erase unit and the write unit are the same. However, in consideration of the continuity of a plurality of serial data, in the file allocation table that manages the file system using the memory chip 81, addresses of consecutive sectors are set to the parity bit or the parity bit so as to access different mats. Has memory array block select bits.

FIG. 26 shows an operation timing chart of the nonvolatile semiconductor memory device of FIG. The address signal A is input (I) and stored (R1) in the address buffer / latch 82. The address buffer / latch 82 is used for erasing, and for example, erasing is performed on one word line in the array block 84 according to the contents held in the address buffer / latch 82. (II). After erasing, the address in the address buffer / latch 82 is transferred to the address latch 83, and the data input (III) is executed. The next address signal A is input (I ′) during the data input (III), and the address buffer / latch 82
(R1). After the data input (III), the data stored in the data latch 33 is written to the address stored in the address latch 83, that is, one word line in the array block 84 erased as described above (I
V). Here, the erase operation (II ′) for one word line in the array block 85 is simultaneously performed according to the contents held in the address buffer / latch 82.

In the array block configuration of the conventional NOR flash memory, since the memory cells are directly connected to one data line, erasing and writing can be performed simultaneously by simply dividing the memory array section into array blocks. I couldn't do it. In this example, since the memory cell is indirectly connected to the data line via the selection transistors 15 and 16 (FIG. 2), for example, the array block 84
Data is written in the memory cell in the array block 85.
When simultaneously erasing the data in the memory cells in the memory cells, the select transistors on the data line side for the cell group 11 selected for writing in the array block 84 are turned on and the voltage of the data line is set to the sub data line (the select transistor). Through the data path to the drain of the memory cell) to enable writing, and the select transistor on the data line side for the cell group 11 selected for erase in the array block 85 is turned off to open the sub data and the source. The select transistor on the line side is turned on and the sub-source line is grounded to enable erasing. As described above, since the memory cells can be erased in word line units and the memory cells are separated by the selection transistors, when the memory array section 31 is divided into array blocks, erase and write are performed simultaneously in the chip. It will be possible. Further, as described above, since the data writing time and the data erasing time are equal to about 1 ms, there is no time overhead due to simultaneous execution. By performing the writing and the erasing in parallel, the rewriting time viewed from the outside of the chip can be shortened to about 50%. Incidentally, FIG.
6, one of the array blocks 84 and 85 is shown as an array block (1), and the other is shown as an array block (2).

Next, a memory cell as a second example will be described with reference to FIGS. FIG. 8 shows a plan view of the memory block. As shown in the operation of the first example, when the threshold voltage in the thermal equilibrium state is optimized, data can be retained even if the voltage of the non-selected word line is 0 V, and the separation of the source terminal is unnecessary. Therefore, the selection transistor connected to the source terminal side can be omitted. The plan view of FIG. 8 shows a plan pattern when the source terminals of the memory cells are shared. That is, the first
Area 46 that defines the floating gate of the second layer (outside of the frame)
The transistor region of the memory cell defined by the intersecting region of the region 47 defining the word line is in contact with the transistor region of the adjacent memory cell without the LOCOS region. FIG. 9 shows a sectional structure view taken along the plane AA ′ of FIG. The cross-sectional structural view taken along the line BB 'of FIG. 8 is shown in FIG.
Is the same as. The source region 63 is shared by two memory cells on the word line 58, and the drain diffusion layer 61 is formed independently of each memory cell. As a result, the length of the memory cell in the word line direction can be reduced, and the memory cell area can be further reduced. The operation of this memory cell is performed according to the voltage conditions shown in FIG.

FIG. 10 shows a memory cell structure as a third example. First floating gate 5 of the first example
4 is a deposited oxide film 7 on the side wall as an insulating film formed on the side surface
1 and a thermal oxide film 72 having a film thickness of 50 to 300 nm formed by the thermal oxidation process. As the deposited oxide film 71 on the side wall, a silicon oxide film or a silicon nitride film formed by the CVD method can be used. However, it is desirable to use a silicon oxide film from the viewpoint of improving the rewriting reliability of the memory cell. With this structure, the impurity diffusion layer 63 to be the diffusion layer wiring is formed.
The first floating gate 54 and the deposited oxide film 71 on the side wall.
It can be easily formed by an ion implantation method using as a mask. Further, as shown in FIG. 11, a thermal oxide film 72 and a silicon oxide film 73 are used as the insulating film 55 in FIG.
And the silicon nitride film 74 can be used.
In this case, the silicon nitride film 74 is formed under the silicon oxide film 73 and between the silicon oxide film 73 and the first floating gate 54, and the floating becomes a problem when the thermal oxide film 72 is formed by a thermal oxidation process. It prevents bird's beaks from entering directly under the gate.

In the third example, the deposited oxide film or the silicon nitride film is formed on the side surface of the floating gate 54, so that the thermal oxide film 72 between the floating gate 56 and the silicon substrate is formed.
To facilitate the formation of. Generally, when the thermal oxide film 72 is formed near the floating gate 54, the bird's beak region bites into the tunnel oxide film 53 due to the thermal oxidation process.
The tunnel oxide film becomes thick. In this embodiment, by using a deposited oxide film or a silicon nitride film,
It is possible to suppress the progress of oxidation on the side surface of the floating gate, prevent the tunnel oxide film from becoming thicker, and prevent the deterioration of the memory cell characteristics.

FIG. 12 shows a memory cell structure as a fourth example. In contrast to the third example, the shallow groove element isolation structure 75 is used in the element isolation region. For example, 0.3 that realizes a large capacity memory of 256 Mbits.
With the rule of 5 microns or less, it becomes difficult to form a narrow element isolation region with the silicon oxide film formed by the thermal oxidation process. In particular, in the nonvolatile memory cell of this method, it is necessary to overlap the first floating gate and the drain side diffusion layer in order to obtain a sufficient tunnel current. For example, the junction depth of the drain side n-type diffusion layer needs to be 0.1 micron or more, and the depth of the shallow groove region needs to be at least about 0.2 micron.

FIG. 13 shows a memory cell structure as a fifth example. In the fourth example, the floating gate has a two-layer structure, but in the present embodiment, only the first layer floating gate 54 is formed. Therefore, the interlayer insulating film 57 is also formed on the floating gate 54 and the deposited oxide film 71 formed on the side surface of the floating gate 54. In this example, since the capacitance between the floating gate 54 and the control gate 58 is small, it is necessary to set the control gate voltage required at the time of rewriting to a high value, or the rewriting time can be lengthened. You will need it. However, since the floating gate has a single-layer structure, the memory cell formation process is simplified, and an inexpensive nonvolatile semiconductor memory device is provided for use in an external memory memory device that does not require high speed. be able to.

FIG. 14 shows a memory cell structure as a sixth example. In the third example, as shown in FIG. 10, the deposited oxide film 71 is used as an oxidation resistant film and the thermal oxide film 72 is used.
However, in this example, since the thermal oxide film 72 is formed without forming the deposited oxide film 71, the deposited oxide film forming step can be omitted and the process steps can be reduced.

FIG. 15 shows a memory cell structure as a seventh example. In the sixth example, as shown in FIG. 14, the floating gate electrode has a two-layer structure of the first floating gate 54 and the second floating gate 56, but in this example,
The floating gate electrode of the second layer has a single-layer structure. This can be achieved by first forming the thermal oxide film 72 and then forming the floating gate electrode 56. Also in this embodiment, since the floating gate can be formed into a single layer, the process steps can be simplified.

FIG. 16 also shows a memory cell structure as an eighth example. In the first example, as shown in FIG. 5, the p-type diffusion layer region 64 for the channel stopper was formed on the source terminal side, but in this example, the source,
P-type diffusion layer regions are formed on both sides of the drain terminal by, for example, an angle ion implantation method. Thereby, the process steps can be simplified.

The memory cell structure described above, a sector structure having 512 bytes as a basic unit, a block structure in which the contact hole area is reduced by collecting 32 to 128 word lines, and a rewriting method are used. By making the change, it becomes possible to manufacture a high-speed large-capacity nonvolatile semiconductor memory device driven by a low-voltage single power supply. The nonvolatile semiconductor memory device can be used to form a card-type data memory device, which can be used as an external memory device for workstations and as a memory device for electronic still cameras. As shown in the first embodiment, since the word line is divided for each sector, it is possible to set the data erasing unit at an arbitrary scale, and a part of the above storage device is set in the program area of the system. It can be allocated and the rest can be secured as a data area.

FIG. 17 is a diagram showing the dependence of the current driving capability on the number of times of rewriting of the memory cell. When the conventional hot carrier is used for writing, when the positive voltage is applied to the word line for writing using the tunnel phenomenon, and when the negative voltage is applied to the word line described in each of the above examples, the tunnel is performed. Comparison is made with the case of writing using the phenomenon. As is clear from this, it can be seen that when the negative voltage is applied to the word line to perform the writing utilizing the tunnel phenomenon, the decrease in the current driving capability β is suppressed. Although details of the hot carriers are omitted, when writing using the tunnel phenomenon is performed by applying a positive voltage to the data line, that is, the write operation is performed by grounding the control gate and applying a positive voltage Vp to the drain diffusion layer. In this case, of the electron-hole pairs generated at the drain end, holes are injected into the gate oxide film according to the direction of the electric field. When the number of rewrites is small, the amount of injected holes is small, and the deterioration is only at the drain end, which does not decrease β of the memory cell, but when the number of rewrittens increases, the amount of injected holes also increases. And the deterioration spreads from the drain edge to the vicinity of the source. Therefore, β of the memory cell decreases. However, when a negative voltage is applied to the word line to perform writing using the tunnel phenomenon as in the above example, the drain voltage is generated at the drain end by setting the drain voltage to a positive voltage of, for example, about 3.3V. It is possible to suppress electron-hole pairs and prevent β of the memory cell from decreasing.

The nonvolatile semiconductor memory device described in detail above is
When performing an electrical write operation for removing charges held in the floating gate electrode to the outside, a first voltage having a reverse bias voltage with respect to the semiconductor substrate is applied to the drain region of the memory cell targeted for the write operation. Then, a second voltage having a polarity different from that of the first voltage is applied to the control gate of the memory cell with respect to the semiconductor substrate to turn off the second MOSFET on the source impurity layer side of the memory cell to turn off the memory cell. When electrically erasing the source terminal of the cell and electrically injecting charges into the floating gate electrode from the outside, the semiconductor substrate is used as a control gate of a plurality of memory cells to be erased. On the other hand, a third voltage having the same polarity as the first voltage is applied, and all the other electrodes have the same voltage as the semiconductor substrate. For example, when an electric write operation of a memory cell is performed, a tunnel phenomenon between the drain region of the memory cell and the floating gate is used to extract electrons from the floating gate, and when an erase operation is performed, a tunnel phenomenon between the semiconductor substrate and the floating gate is performed. Electrical rewriting is performed by injecting electrons into the floating gate using. As described above, in the electrically rewritable nonvolatile semiconductor memory device, since both writing and erasing operations are performed by using the tunnel phenomenon between the floating gate electrode and each diffusion layer of the drain / source / substrate, the writing and erasing operations are performed. In both operations, the current consumption per bit is about 10 nA, and the power consumption can be suppressed. As a result, a booster circuit with a small current drive capability is sufficient, and the booster and step-down circuit required to generate the high voltage required for writing and erasing can be formed in the chip, and high-speed nonvolatile While using a semiconductor memory device,
Writing, erasing, and reading can be performed with a single 3.3 V power supply.

Further, at the time of erasing, a high voltage (12 V) is applied to only one word line and the other word lines are grounded, thereby erasing all the memory cells connected to one word line. You can Therefore, if a plurality of memory cells are connected in parallel to one word line, one word line can be defined as one sector and a plurality of memory cells can be erased simultaneously (sector erase method). it can.
Further, by selecting a plurality of word lines, the memory cells on the plurality of word lines can be erased at once.

At the time of writing, when the threshold voltage of the memory cell reaches a predetermined low threshold voltage state as a writing state, the voltage of the latch circuit 33 becomes 0 V, so that in the subsequent writing, the drain diffusion layer is formed. The voltage of 7 is 0
V, and the electron tunneling phenomenon does not occur. Therefore, even when writing is performed in multiple bits at the same time, variations in low threshold voltage are suppressed.

In the write operation, as described above, since data can be simultaneously written in a plurality of memory cells on one word line by using the latch circuit, one word line can be written in the same manner as erasing. It is possible to write in sector units by defining one sector. That is, since the erase unit and the write unit can be the same, it is not necessary to save data when rewriting data.

At the time of reading, the selected word line is set to Vc.
Since the non-selected word line is set to c and the unselected word line is set to the grounded state, the memory cell in the written state is turned on and the current flows, but the memory cell in which the writing is not performed is in the off state and the current does not flow. Therefore, the on / off state of the memory cell can be obtained by observing the current or voltage flowing through the data line using the sense amplifier connected to the data line.

As described above, since the write and erase operations can be achieved by the tunnel phenomenon between the diffusion layer in the channel region of the memory cell and the floating gate, the tunnel region area can be reduced,
It has become possible to miniaturize the memory cell area. That is, a cell area equal to or smaller than that of the conventional NOR flash memory cell can be achieved.

Further, since a negative voltage is used for the word line at the time of data writing and the drain voltage at the time of data writing can be lowered to a power supply voltage (for example, 3.3V), peripheral circuits such as a decoder system in the data area can be used. Higher breakdown voltage is unnecessary, and the peripheral circuit area can be reduced, and
It is possible to suppress generation of electron-hole pairs at the drain end at the time of rewriting data and prevent deterioration of the gate oxide film in the channel portion, and it is possible to prevent a decrease in current driving capability even after rewriting 10 6 times. Further, since the disturb prevention voltage applied to the non-selected word line at the time of writing can be set to 3.3 V which is the power supply voltage at most, it is not necessary to use the boosted power supply.
Writing time can be shortened.

Further, as shown in FIG. 2, since one contact hole region is formed for a group of a plurality of memory cells (for example, 16 to 128) as one unit, the contact hole region is formed. The area occupied by the memory array is reduced, the memory cells can be miniaturized, and a large-capacity nonvolatile memory device such as 64M or 256M can be realized.

<< File Memory System >> Next, FIG.
0, a file memory system using the nonvolatile semiconductor memory device as described in FIG. 25 will be described below as an embodiment of the memory system of the present invention.

FIG. 27 shows a nonvolatile semiconductor device FM of the present invention.
An example of an effective memory system configuration using C (including flash memory chips CH1 to CHk) will be shown. Each of the flash memory chips CH1 to CHk is shown in FIG.
Alternatively, it can have the same configuration as the chip 81 shown in FIG. Therefore, each of the memory chips CH1 to CHk is provided with a plurality of sectors having one word line and a plurality of memory cells connected thereto, and a sector buffer (see FIGS. Corresponding to the sense latch circuit 39 including the latch circuit 33 shown). The memory chips CH1 to CHk are connected in parallel to form a nonvolatile semiconductor device FMC. The number of memory chips CH1 to CHk may be, for example, 8 to 20. Input data is transferred via a data bus transceiver 101 to a PCMCIA (Personal Computer Memory Card Inte
rnational Association) standard, IDE (Intelligent D
evice Electronics) standard, CPU I / O bus, and other external system buses. Further, the memory system includes an address decoder 103 for selecting the memory chips CH1 to CHk and an address bus driver 102 for inputting an address for selecting a sector (that is, a word line) in the chip, and the address A control bus controller 104 for decoding, controlling data, and controlling chips is provided. The data bus transceiver 101 and the address bus driver 10
2, the address decoder 103, and the control bus controller 104, the host interface 10
0 is formed. The circuit blocks indicated by 102 and 103 in FIG. 27 have a structure for latching an internal address, and the output signal thereof can be latched. This is because the external bus is designed to be released after the necessary signals have been sent.

In the conventional memory system, since the unit of chip erasing is larger than the unit of writing, the information of the memory chip corresponding to the erasing is temporarily stored (stored) in the buffer memory provided outside the chip before erasing. It was necessary to input write information, rewrite the buffer memory contents, and then successively write back the erased range information in a certain write unit to the chip.

In the memory system shown in FIG. 27, the PCM
It goes without saying that a memory card system compatible with a data bus such as CIA can be constructed, but by using the nonvolatile semiconductor device FMC of this embodiment, the sector buffer (39) provided in the chip can be Since the size is at least the same as the size of erase / write, the temporary storage work of the data, which was required when rewriting the data in the conventional memory system described above, becomes unnecessary, and the buffer memory required in the conventional memory card system is eliminated. Can be omitted. Erasing and writing can be performed continuously because temporary storage work is not required. Specifically, in the conventional memory system, for example, when the unit memory area capacity for erasing is 4 Kbytes and the amount of data to be rewritten is 512 bytes, the time required for rewriting data is 1 ms erasing + 1 ms writing / writing. It is 512 bytes x 8 times, and it takes 9 ms in total. In the memory system using the non-volatile semiconductor device FMC of the present embodiment, erase 1 ms + write 1 ms,
The total time is reduced to 2 ms. Further, in the case of rewriting 4 Kbytes of data, it takes 9 ms in the conventional configuration as in the above calculation, and in the memory system of this embodiment, a plurality of word lines (a plurality of sectors) are selected and erased at the same time. The writing is 1 ms / 512 bytes × 8 times, and the total is 9 ms, which is the same as the conventional case.

FIG. 28 shows another memory system configuration. The host interface 100 in FIG.
Is replaced with a microprocessor 200. Even in this configuration, since the size of the sector buffer provided in the chip is at least the same as the size of erase / write, it is sufficient to transfer the data of the system bus to the sector buffer in the chip, and the 1-chip microcomputer facilitates this. It is controllable. With this configuration, it is possible to reduce the number of parts on the card when the system is deployed on the card.

FIG. 29 shows a construction example of a memory system provided with an external buffer memory when the above memory chip is used. A buffer memory 110 of at least 512 bytes is provided on the data bus of FIG. 27 so that control from the control bus controller 104 is possible. As described above, the conventional configuration requires a buffer memory of 4 Kbytes or more for rewriting data by saving the data in the memory area of the erase unit including the data rewriting area. It was occupied by rewrite data. In this configuration, for example, the 4 Kbyte buffer memory 110 is not provided for storing (saving) the write data, but is prepared for prefetching the data. That is, while rewriting data to a certain chip, the next rewriting data is transferred into the memory system from the external system bus. Therefore, the contents of the buffer memory 110 need only be 512 bytes, which is the minimum required for sector rewriting, and a large-scale memory chip is not necessary. That is, 512 × integer bytes may be used. Alternatively, an area for prefetching data may be provided in the area of the conventional buffer memory described above, and the buffer memory may be used for both operation modes of data reading and data writing.

Since the addresses 102 and 103 in FIG. 29 pre-store the address of the data for continuous rewriting, the next address signal is latched, and rewriting is started based on the address after the chip currently being written is rewritten. R.
Also, the larger the address read-ahead (storage) capacity, the larger the number of continuous rewrites and the longer the bus open time. The above operation is performed by the control bus controller 104 according to the control signal from the external bus 101, 102, 10
3 and memory chips CH1 to CHk.

As described above, the buffer memory 11
0 enables prefetching (successive rewriting) of data, and has the effect of sending addresses and data for a plurality of chips one after another for latch storage and opening the external bus during that time to enable another work. is there. In addition, for each chip, there is a restriction that the operation cannot be shifted to the next operation until the rewriting based on the 512B internal sector buffer is completed, but in a system using a plurality of chips, even if one writing is in progress, Since writing to the other chip can be performed in parallel, there is an advantage that the rewriting speed can be increased.

The configuration of the system using the nonvolatile semiconductor device (flash memory chip) of the present invention has been described above.
Generally, for file use, rewriting is performed with 512 bytes as one sector, so that the rewriting time when the system configuration according to the present embodiment is used can be made faster than the conventional configuration. Further, it is possible to store the write data for one sector required for data rewriting (erasing / writing) in the memory chip described in FIG. 29, and it is possible to rewrite without adding a buffer memory for this to the system. Therefore, there is an advantage of reducing the occupied area and cost. In the conventional configuration, it is needless to say that the buffer memory 4 KB cannot be pre-read because the buffer memory 4 KB uses all the buffer memories for temporary storage of the erase size 4 KB type memory.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

In the above description, the case where the invention made by the present inventor is mainly applied to the file memory system which is the field of application which is the background of the invention has been described, but the present invention is not limited to this and is applicable to various memory systems. It can be widely applied.

[0105]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Since data can be simultaneously written to a plurality of memory cells on one word line by using a latch circuit, one word line is defined as one sector like sector erase and sector unit is used. Can be written. That is, since the latch circuit provided in the chip is provided so as to be comparable to the erase / write data size, in other words, the write and erase units are matched,
The temporary storage work of the data, which was required when rewriting the data, is unnecessary. Therefore, the buffer memory for that purpose can be omitted, and further erasing and writing can be continuously performed. Further, it becomes possible to convert the rewriting operation into one command.

Since the size of the sector buffer composed of the latch circuit is at least the same as the size of erase / write, it is sufficient to transfer the data of the system bus to the sector buffer in the chip, and an easy interface by a one-chip microcomputer. Control can be realized. By utilizing such a microprocessor as the interface means, the number of parts on the card can be reduced when the present memory system is developed on the card.

A data cache function can be realized by adopting a buffer memory capable of prefetching data (successive rewriting), and addresses and data for a plurality of chips are sent one after another in a latched manner, and externally stored during that time. You can open the bus to allow the host side to do other work. Further, rewriting can be performed in parallel for chips different from each other, which contributes to an increase in rewriting speed.

It is possible to realize a large-capacity file system and a file card used in a small portable device, and to construct a data storage file system for an electronic still camera that processes a large amount of image data. It enables the production of card-type portable recording / playback equipment.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a simplified sectional structure of a memory cell of a nonvolatile semiconductor device used in a memory system of the present invention.

FIG. 2 is a circuit diagram of an example of a memory array of a non-volatile semiconductor device used in the memory system of the present invention.

FIG. 3 is a schematic block diagram showing an example of a non-volatile semiconductor device used in the memory system of the present invention.

FIG. 4 is a plan view of a memory cell as a first example used in the memory system of the present invention.

5 is a cross-sectional view showing the shape of a memory cell taken along the plane AA ′ of the plan view of FIG.

FIG. 6 is a cross-sectional view showing a memory cell shape on a BB ′ plane of the plan view of FIG. 4.

FIG. 7 is a cross-sectional structural diagram of a conventional NOR flash memory cell.

FIG. 8 is a plan view of a memory cell structure as a second example.

9 is a cross-sectional view showing the shape of the memory cell on the plane AA ′ of the plan view of FIG.

FIG. 10 is a sectional structural view showing a memory cell shape as a third example.

FIG. 11 is a sectional structural view showing a memory cell shape obtained by expanding a memory cell structure as a third example.

FIG. 12 is a sectional structural view showing a memory cell shape as a fourth example.

FIG. 13 is a sectional structural view showing a memory cell shape as a fifth example.

FIG. 14 is a sectional structural view showing a memory cell shape as a sixth example.

FIG. 15 is a sectional structural view showing a memory cell shape as a seventh example.

FIG. 16 is a sectional structural view showing a memory cell shape as an eighth example.

FIG. 17 is a characteristic diagram showing the dependence of the current drive capability on the number of rewrites.

FIG. 18 is an explanatory diagram showing a voltage relationship of a signal line in each operation of data erasing, writing, and reading in a nonvolatile semiconductor memory device including a memory cell as a first example.

FIG. 19 is an explanatory diagram similar to FIG. 18 in a nonvolatile semiconductor memory device including a memory cell as a second example.

FIG. 20 is a block diagram of an example of a nonvolatile semiconductor memory device used in the memory system of the present invention.

FIG. 21 is an explanatory diagram showing various operations of the apparatus shown in FIG. 20.

22 is an explanatory diagram showing various operations of the apparatus shown in FIG. 20. FIG.

FIG. 23 is an explanatory diagram showing various operations of the apparatus shown in FIG. 20.

FIG. 24 is an explanatory diagram showing various operations of the apparatus shown in FIG. 20.

FIG. 25 is another block diagram of a nonvolatile semiconductor memory device used in the memory system of the present invention.

FIG. 26 is an explanatory diagram showing various operations of the apparatus shown in FIG. 25.

FIG. 27 is a block diagram of an embodiment according to the memory system of the present invention.

FIG. 28 is a block diagram of another embodiment according to the memory system of the present invention.

FIG. 29 is a block diagram of another embodiment of the memory system of the present invention.

[Explanation of symbols]

 1 p-type semiconductor substrate 2 gate insulating film 3 floating gate electrode 4 interlayer insulating film 5 control gate 6,62 source region 7,61 drain region 8,64 p-type impurity region 9 full tunnel injection system 10 edge tunnel emission system 11 parallel memory Cell group 12,43 Contact hole 13 Drain diffusion layer wiring 14,63 Source diffusion layer wiring 15,16,19,20 Select transistor 17 Common source line 18,41 Metal data line 21 Hot carrier injection method on the drain side 22 Source side n type diffusion layer region 23 drain side n type diffusion layer region 24 drain side p type diffusion layer region 25 edge tunnel erasing method 31 memory array section (memory cell array) BLK1, BLK2 memory block CTRL internal controller 32, 60 data line 33 latch Circuits 34, 35, 36 Decoder 37 High voltage generation circuit (boosting circuit) 38 Negative voltage generation circuit 39 Sense latch circuit 42 Element isolation region 44 Drain diffusion layer 45, 49 Select transistor gate region 46 First layer floating gate region 47 word line formation region 48 second layer floating gate region 50 common source region 51 element isolation region 52 p-type silicon substrate 53 tunnel oxide film 54 first floating gate 55, 59 insulating film 56 second floating gate 57 interlayer Insulating film 58 Control gate 65,76 P-type impurity region 71,73 Silicon oxide film 72 Thermal oxide film 74 Silicon nitride film 75 Shallow trench element isolation structure CH1 to CHk Semiconductor memory chip 101 Data bus tranceiver 103 Address decoder 110 Data buffer memory

Front page continued (72) Inventor Toshihiro Tanaka 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Hitoshi Kume 1-280 Higashi Koikeku Ku, Tokyo Kokubunji City Inside Central Research Laboratory, Hitachi Ltd. (72) Inventor Katsutaka Kimura 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi, Ltd.

Claims (7)

[Claims] 1. An electrically erasable and writable non-volatile semiconductor memory system having a plurality of semiconductor memory chips and control means connected to the chips for controlling the operation of the chips. Provided is a memory cell array divided into a plurality of memory blocks each having a plurality of semiconductor memory cells arranged in rows and columns, and each memory cell therein has a source and drain region formed on a semiconductor substrate, Insulated gate field effect including a gate insulating film formed on the semiconductor substrate between drain regions, a floating gate formed on the gate insulating film, and a control gate formed on the floating insulating film via an interlayer insulating film Including one transistor structure, the drain region of the transistor structure of a plurality of memory cells on one column is one. Is connected to the data line,
The control gates of the transistor structures of the plurality of memory cells on one row are connected to one word line, and the source regions of the transistor structures of the plurality of memory cells on one column are connected to each other, Source and drain regions formed in the semiconductor substrate, the source and drain regions being provided in the memory block, having a plurality of common source lines extending in the row direction and formed on the substrate;
And a plurality of first selection insulating field effect transistor rows in which a plurality of selection transistors each having a gate electrode formed on the semiconductor substrate via an insulating film between the source / drain regions are arranged in parallel in the row direction. However, one row of the first insulating field effect transistor for selection is provided for each of the memory blocks, and one selection transistor is provided for each column of one memory block. Source and drain regions formed in the semiconductor substrate, connected between the commonly connected source regions of the transistor structure of the memory cell and the corresponding one common source line;
And a plurality of second selection insulating field effect transistor rows in which a plurality of selection transistors each having a gate electrode formed on the semiconductor substrate via an insulating film between the source / drain regions are arranged in parallel in the row direction. However, one row of the second selection insulating field effect transistor is provided for each of the memory blocks, and one selection transistor is provided for each column of one memory block. The connection between the drain region of the transistor structure of a plurality of memory cells in one column and the corresponding one data line is performed, and further, the plurality of memory cells connected to one word line to be collectively erased are connected. In order to write data to one memory cell at a time, write / write one bit on each data line.
A memory system comprising a plurality of latch circuits each of which is connected to each data line and stores read data under the control of the control means. 2. The interface means having a data bus transceiver for transferring write / read data to and from the semiconductor memory chip and an address decoder for selecting one of the memory chips. The memory system according to claim 1, further comprising: 3. The memory system according to claim 1, wherein said control means further comprises a microprocessor having interface means. 4. A write data buffer memory is further provided for storing write data to be supplied to the plurality of memory cells connected to one selected word line via the latch circuit. The write data buffer memory has a storage capacity substantially equal to n times (n is a positive integer) the storage capacity of a plurality of memory cells connected to one word line. The memory system according to claim 1, wherein the memory system is a memory system. 5. A read / write data buffer memory for storing read / write data, the read / write data buffer memory comprising a plurality of memory cells connected to a selected word line. Is substantially n times (n is a positive integer) the storage capacity of a plurality of memory cells connected to one word line for storing write data to be supplied via the latch circuit. 2. The memory system according to claim 1, wherein the memory system comprises storage areas having the same storage capacity. 6. The write data buffer memory, when the current write data is transferred to the latch circuit, irrespective of whether the current write data has already been written or not, under the control of the control means, 5. The memory system according to claim 4, wherein the memory system is arranged so as to store write data. 7. Each of the semiconductor memory chips further comprises an internal controller responsive to the output of the control means,
A memory cell unit area of the memory cell array for the batch write operation is equal to a memory cell unit area of the memory cell array for the batch erase operation, and the batch write operation and the batch erase operation are performed under the control of the internal controller. The memory system according to claim 1, wherein