JPH02177097A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To ensure the transmission of a bit line level to a selection memory cell and to reduce power consumption by utilizing electron discharge from a floating gate in the data erasure mode and electron injection to the floating gate in the data write mode. CONSTITUTION:An external program pulse VPPA is given to a bit line at data erasure, electrons of the floating gate are discharged from memory cells M1 - M8 closer to the bit line in the order to bring all memory cells to the state of data 1. At first, in the erasure of the memory cell M1, an H level is applied to a control line SD1 of a selected TR S1 at the bit line side, the voltage VPPA is applied to the bit line to apply an L level voltage to a control line SS1 and word lines WL2 - WL8. Thus, the M1 is brought into the erased state. The voltage VPPA is sent sequentially via the memory cell M2 and the memory cells M2 - M8 are erased. In the write mode, a program pulse VPPB from a boost circuit 14 is applied to the control gate of the selected cell to inject electrons to the floating gate to apply write while using a data as 0.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention provides an electrically rewritable nonvolatile semiconductor constructed using a memory cell having a MOS transistor structure having a floating gate and a control gate. Memory device (E2 FROM
) regarding.

(Prior Art) In the field of E2 FROM, memory cells having a MOS transistor structure having a floating gate and a control gate are widely known. The E2 FROM memory array is constructed by arranging memory cells at each intersection of row lines and column lines that intersect with each other. In the actual pattern, the drains of the two memory cells are made common and the column lines are connected thereto to minimize the cell occupation area.

However, even in this case, a contact portion with the column line is required for each common drain of two memory cells, and this contact portion occupies a large portion of the cell occupation area.

As a promising solution to this problem, the applicant has previously proposed NA
We have proposed an E2 FROM with an ND cell configuration (Japanese Patent Application No. 62-233944). This NAND cell is a system in which multiple memory cells each having a floating gate and a control gate are directly connected so that the source and drain are shared. configured. N
The AND cells are arranged in a matrix, with the drain at one end connected to a bit line, and the control gate of each memory cell connected to a word line. Data erase and write operations in this NAND cell utilize electron tunneling between the floating gate and the drain layer or substrate. The erase/write operation will be specifically explained.

To erase data, a "H" level potential of about 20V is applied to the word lines of all memory cells, and an "L" level potential, ie, OV, is applied to the bit lines. As a result, all memory cells become conductive, and electrons are injected from the substrate into the floating gate by tunneling, resulting in an erased state in which the threshold voltage moves in the positive direction (eg, threshold voltage 2V). This is -batch elimination. Data writing is performed in order from the memory cell farthest from the bit line among the NAND cells. At this time, the bit line is given a "H" level potential of, for example, 23V, the word line connected to the selected memory cell is given 0, and the unselected word line is given a "H" level potential of 2~3V. It will be done.

The word line connected to the memory cell to which writing has already been performed is Ov. As a result, the "H" level potential of the bit line is transmitted to the drain of the selected memory cell, and in this memory cell, the electrons of the floating gate are released to the drain, and the threshold value moves in the negative direction, resulting in a state of "1". (for example, threshold value -2V) data writing is performed. At this time, no electric field is applied between the control gate and the substrate in the memory cells on the bit/node line side of the selected memory cell, so that the erased state is maintained. In the case of writing "0", an intermediate potential of, for example, 11.5V is applied to the bit line. At this time, the memory cells on the Bi/Node line side of the selected memory cell enter a weak erase mode,
No data has been written to these areas yet, and the electric field is weak, so over-erasing will not occur. For data reading, 0V is applied to the selected word line, and 5V is applied to other word lines, for example.
This is done by giving a current and detecting the absence of a current. “】
If it is "0", current will flow; if it is 0, no current will flow.

E2FROM with NAND cell configuration proposed earlier
had the following problems. One is that the erase state is a state in which electrons are injected into the floating gate to raise the threshold in the positive direction, so when writing data, the memory cell's potential is high before the bit line potential is transmitted to the selected memory cell. This causes a potential drop due to the threshold voltage. In particular, N
When a large number of memory cells constitute an AND cell, and when writing is performed to a memory cell distant from a bit line, the potential applied to the bit line drops significantly, resulting in poor writing efficiency.

Furthermore, when "1" writing/erasing is repeated, the threshold value after erasing becomes higher in unselected memory cells located on the bit line side from the selected memory cell. This is due to the fact that only the erase mode is repeated in unselected memory cells. As a result, when the threshold value of the unselected memory cell becomes higher than the read potential, erroneous reading occurs. Further, the transmission of the bit line potential during writing becomes even worse, and eventually writing becomes impossible. Further, when a program pulse is applied to the drain to cause the floating boot to emit electrons, a relatively large current flows. For this reason, it is difficult to generate this program pulse using an internal booster circuit, as this increases the power consumption and size of the chip, and it must be supplied from outside the chip.

(Problem to be solved by the invention) As described above, the E2F of the NAND cell configuration proposed earlier
In ROM, since the erase state is a state in which electrons are injected into the floating gate and the threshold value is raised, the transmission efficiency of the program pulse potential applied to the bit line during writing to the selected memory cell is poor, and the writing/erasing is difficult. By repeating this, the threshold value of unselected memory cells in the erased state on the bit line side becomes higher and higher, causing malfunction.Furthermore, the program pulse applied to the bit line when writing data must be formed by an internal booster circuit. The problem was that it was difficult.

An object of the present invention is to provide an E2 FROM composed of NAND cells fM that solves such problems.

[Structure of the Invention (Means for Solving the Problems)] The present invention provides a structure in which a plurality of NAND cells each having a stacked structure of a floating gate and a control gate are connected in series, and a plurality of NAND cells are arranged in a matrix. An E2 FROM is configured such that the drain at one end is connected to a bit line, and the control gate of each memory cell is connected to a word line. a data erase mode in which electrons are emitted into the substrate or drain, and a data write mode in which electrons are injected from the drain layer or substrate into the floating gate by applying a program pulse to the control gate of the selected memory cell; Program at
The pulse is generated by an internal booster circuit, and the program pulse in the data erase mode is supplied from outside the chip.

(Operation) In the present invention, "data erasing" and "data writing"
The concept of this is the opposite of what was previously proposed by the applicant. In other words, the state in which electrons are emitted from the floating gate and the threshold value is low is defined as the erase state, the operation to do so is defined as the data erase operation, and the state in which electrons are injected into the floating gate and the threshold value is increased is defined as the write state. , such an operation is referred to as a data write operation. As a result, when writing data, it is no longer difficult to write data into a selected memory cell located away from the bit line due to a potential drop due to the threshold voltage of an unselected memory cell.

Also, when erasing, if a method of erasing is adopted sequentially from the bit line side, the transmission of the "H2 level potential from the bit line to the selected memory cell is performed without a potential drop due to the threshold value. Also, the current consumption is small. The program pulse for writing data is generated by an internal booster circuit, and the program pulse for erasing data, which consumes a relatively large amount of current, is supplied externally, resulting in a highly reliable EEL FROM with low power consumption as a whole. can get.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main structure of an E2 FROM according to an embodiment of the present invention. 11 is a memory array, 12 is a row decoder for selecting word lines, and 13 is a column decoder for selecting bit lines. Internal boost circuit 1 inside the chip
4 is formed, and this booster circuit 14 receives the high voltage program pulse ■ applied to the word line during data writing.
, 8 are generated. The high voltage program pulse VPPA applied to the bit line during data erasing is supplied from outside the chip.

FIG. 4 is a plan view showing one NAND cell of the memory array 11, and FIGS.
It is a BB sectional view. The configuration of one NAND cell will be explained by focusing on it.

In this embodiment, eight memory cells M1 to M8 and two selection transistors S, .

In each memory cell, a floating gate 4 (41 to 48) made of a first layer polycrystalline silicon film is formed on a substrate 1 via a first gate insulating film 3 made of a thermal oxide film, and a second gate insulating film is formed on the floating gate 4 (41 to 48). Control gates 6 (6z to 68) made of a second layer polycrystalline silicon film are formed through the film 5.

The control gate 6 of each memory cell is connected to the word line W L
(W L 1 to WL 8). Eight memory cells are connected in series in such a manner that the n+ type layer 9 serving as the source and drain of the memory cell is shared by adjacent cells. In this embodiment, a selection transistor 5183 is connected to the drain side and the source side to form one N A N
It constitutes the D cell. selection transistors s,,s3
Gate electrodes 49+69 and 410.610 of the first layer constitute the floating gate and control gate of the memory cell.

Obtained by simultaneously buttering the second layer polycrystalline silicon film, between the 71f poles 49 and 69 and between the electrodes 410 and 61
0 are in contact at predetermined intervals in the word line direction. The whole is covered with a CVD insulating film 7, and a wiring line 8 is provided as a bit line BL which contacts the n-type terminal which is the drain of the selection transistor S1 with respect to the memory cell. This contact portion is doped with n-type impurities in an overlapping manner as shown by the broken line in FIG. 5(a).

Coupling capacitance ff between floating gate 4 and substrate 1 in each memory cell
i C1 is the coupling capacitance Q between the floating gate 4 and the control gate 6
It is set smaller than C2. To explain the specific dimensions, both the floating gate 4 and the control gate 6 have a pattern width of 1 μm1, so the channel length of the memory cell is 1 μm, and the floating gate 4 is located above the field region as shown in FIG. 5(b). It extends 1 μm on each side.

The first gate insulating film 3 is a thermal oxide film of 110 people, and the second
The gate insulating film 5 is a 350-layer thermal oxide film.

Selection transistor s1. For s3, the drain side (
That is, the channel length of the selection transistor S1 on the bit line side is set longer than that of the selection transistor S3 on the source side. This is to prevent bunch-through of the selection transistor S1.

Further, a source diffusion layer to which a ground potential is applied is formed commonly in the word line direction.

Such NAND cells are repeatedly arranged while being folded in the bit line direction while sharing a bit line contact source diffusion layer to form a memory array.

The operation of E:+pRohx configured in this way will now be explained with reference to FIGS. 2 and 3. In this embodiment, to erase data, an external programming pulse VPPA is applied to the bit line, and electrons from the floating gate are ejected from the memory cell closer to the bit line. As a result, all the memory cells are brought into the low threshold data "1" state. In the data write mode, a program generated by the internal booster circuit is applied to the control gate for one selected memory cell.
By applying a pulse vPP B and injecting electrons into the floating gate, the data is set to "O".

These operations will be explained in more detail with reference to FIG. 3, focusing on one NAND cell.

First, memory cell N1. ~N18 data deletion is performed. This data erasing is to release electrons from the floating gate of the memory cell to the substrate or drain to move the threshold value in the negative direction, in other words, to set the data in all memory cells to 1''.

In this embodiment, this erasing operation is performed sequentially starting from the memory cell M closest to the bit line BL. First, memory cell M
To erase 1, apply "H# level (for example, 20V) to the control line SDI of the selection l transistor S1 on the bit line side,
External program pulse vpp^ to bit line BL
(for example, 20V) to the control line SS of the selection transistor on the source side and the word lines WL2 to WL8.
"L" L-bell potential (-0V) is applied.At this time, the "Hl-level potential applied to the bit line BL is transmitted to the drain of memory cell M1 through selection transistor S1, and in memory cell M, A high electric field is applied between the ffi control gate and the substrate. As a result, the electrons in the floating gate are emitted to the substrate and drain, and the threshold value moves in the negative direction, resulting in an erased state with a threshold voltage of -2y, for example. Next, to erase data from the memory cell M1, as shown in FIG. 3(a), an "H" level potential is applied to the word line WL1 connected to the gate of the memory cell. At this time, the programming pulse vPPA applied to the bit line BL is transmitted to the drain of the memory cell M2, and in this memory cell M2, electrons are similarly emitted from the floating gate and its threshold value moves in the negative direction. . Thereafter, in the same way, the bit lines BL “
By transmitting an H'' level potential to the drain of the memory cell.

Erase M3 to M8.

Data writing is performed by injecting electrons into the free gates of memory cells whose threshold values have become smaller in order from those farthest from the bit line BL to move the threshold values in the positive direction. First, to write to the memory cell M8, an intermediate potential (-9V) is applied to the word lines WL1 to WL7, and an internal voltage boost is applied to the word line WL8 connected to the control line of the selection transistor S1 on the bit line side and the control gate of the selected memory cell M8. Program pulse vPP B (-18
The control line SS of the selection transistor S3 on the source side is set to an "L" level potential (-0V). At this time, when an "L" level potential (-0V) is applied to the bit line BL, a high electric field is applied between the substrate and drain of the memory cell M8 and the floating gate, and electrons are injected into the floating gate by a tunnel current. As a result, the threshold value of the memory cell M8 moves in the positive direction, and enters a "0" write state with a threshold value of 2v, for example. At this time, in the other memory cells M1 to M7, only a weak electric field due to an intermediate potential is applied between the control gate and the substrate, and the erased state is maintained. Writing "1" data is performed by applying an intermediate potential to the bit line BL to prevent electron injection into the floating gate, that is, by maintaining the erased state.

Next, writing to the memory cell M7 is performed using a program pulse PP from the internal booster circuit, as shown in FIG. 3(b).
B is applied to the word line WL7 connected to the control gate of the selected memory cell M7, and the word line WL connected to the memory cells on the bit line side.

~W L 6 is an intermediate potential, and written memory cells 8,
The word line WL8 connected to the control gate No. 18 is set to an L" level potential (-0V) or an intermediate potential. As a result, when an "L" level potential is applied to the bit line BL, the memory cell M7 similarly has a t$ floating gate. electron injection is carried out in
“O” writing is performed. Similarly, the memory cells M6 and . Write to M6, . . .

Note that during data writing to memory cells M, ~~8 connected to bit lines BL, the same word lines WL,~WL8
Similarly, writing can be performed on memory cells of other bit lines controlled by the bit line by applying a bit line potential corresponding to the data.

FIG. 3(c) shows the potential relationship during the read operation. This example is a case where data is read from memory cell M7. Word line WL3 connected to selected memory cell M7
A "L" level potential (-0V) is applied to the select transistors s, , s3 and all remaining word lines, and a read voltage (-5V) is applied to the bit line BL. As a result, memory cell M3 has a high threshold voltage.
No current flows in the 0" state, and current flows in the "1" state where the threshold is low.

As described above, in this embodiment, the threshold values of all memory cells are negative, ie, in the D type state, when data is erased. During erasing, since the erase operation is performed sequentially starting from the memory cells on the bit line side, all the memory cells on the bit line side from the selected memory cell are in the D type state, and the "H level" program pulse applied to the bit line is applied to the memory cells on the bit line side. The potential of VPPA is transmitted to the drain of the selected memory cell without a potential drop due to the threshold voltage.Therefore, there is no need to make the potential of the program pulse VPPA used for erasing operation so high.Even when writing data, " In the case of 1'' writing, the intermediate potential of the bit line is transmitted to the selected memory cell without receiving a potential drop equal to the threshold voltage in unselected memory cells located on the bit line side from the selected memory cell.

So, for example, the program pulse ■PPB at the time of writing
If Vcc is lowered to about 15V, the power supply potential Vcc=5V can be used as the intermediate potential, and it is also possible to reduce the volatiles in the boosted potential. This leads to the simplification of peripheral circuits. The output of the internal booster circuit is used only for the high-voltage program pulse applied to the word line in erase mode, and the high-voltage program pulse applied to the bit line in write mode is supplied from outside the chip. Therefore, an E2 FROM can be obtained in which the power consumption of the chip is effectively reduced and the chip is miniaturized, and normal write and read operations can be performed using only external voltages W and Vcc.

In the embodiment shown in FIG. 1, when erasing data, an external program pulse VPPA is supplied to the bit line of the memory array via the column decoder 13, and at the same time, the program pulse VPPA is supplied to the bit line of the memory array via the row decoder 12 to erase the already erased memory cell. An "H" level signal that keeps the memory cell in a conductive state is also applied to the word line. “H” applied to this word line
``Since the level signal is applied to the control gate of the memory cell, it does not consume a large amount of current, so the output of the internal booster circuit can be used.The configuration of the embodiment in this case is shown in Figure 1. This is shown in FIG. 6, and its operation timing diagram is shown in FIG.

This embodiment also provides the same effects as the previous embodiment.

[Effects of the Invention] As described above, according to the present invention, by using electron emission from the floating gate as the data erasing mode and using electron injection into the floating gate as the data writing mode, bit line potential selection memory can be used. It is possible to realize an E2 FROM with a NAND cell structure that can ensure reliable transmission to the cell and also generates part of the high voltage program pulse inside the chip, effectively reducing power consumption. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of an E2 PROM according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, and FIGS. 3(a) to (C) are diagrams showing each operation mode. NA at
A diagram showing the potential relationship within the ND cell, Figure 4 is one NAN
A plan view showing the configuration of the D cell part, FIGS. 5(a) and 5(b) are sectional views taken along A-A- and B-B in FIG. 4, and FIG. FIG. 7 is a timing chart for explaining its operation. 11...Memory array, 12...Row decoder,
13... Column decoder, 14... Internal booster circuit,
1...p-type silicon substrate, 2...element isolation insulating film,
3゜5... Gate insulating film, 4 (41-48)... Floating gate, 6 (61-68)... Control gate, 7...
・CVD insulation film, 8...Ag wiring (bit line), BL
...Bit line, WL...Word line, 81-S4...
・Selection transistor. VPPA = 20V v v Applicant's agent Patent attorney Takehiko Suzue Figure 3 n4'' He A. Figure (a) (b) Figure

Claims (2)

[Claims] (1) A floating gate and a control gate are stacked on a semiconductor substrate via a gate insulating film, and there are multiple memory cells that can be electrically rewritten by transferring charge between the floating gate and the substrate or drain layer. A plurality of NAND cells connected in series are arranged in a matrix, and the NA
In a nonvolatile semiconductor memory device in which the drain at one end of an ND cell is connected to a bit line and the control gate of each memory cell is connected to a word line, an "L" level potential is applied to the control gate of a selected memory cell. In the data erase mode, a program pulse is applied to the drain to release electrons in the floating gate to the drain layer or substrate, and a "L" level potential is applied to the drain of the selected memory cell, and a program pulse is applied to the control gate. and a data write mode in which electrons are injected into the floating gate, the program pulse for the data erase mode is supplied from an external circuit, and the program pulse for the data write mode is generated by an internal booster circuit. A nonvolatile semiconductor memory device characterized by: (2) In the data erase mode, programming and pulses are applied to the bit lines, and the bit lines are sequentially “L” from the word line on the bit line side.
"H" level potential is applied to the remaining word lines on the bit line side of the word line to which the "L" level potential has been applied, and "L" level potential is applied to the remaining word lines on the source side. By doing so, electrons from the floating gate are released into the substrate in order from the memory cell on the bit line side. In the data write mode, an "L" level potential is applied to the bit line and a program pulse is applied to the selected word line. death,
2. The nonvolatile semiconductor memory device according to claim 1, wherein an intermediate potential is applied to the word line on the bit line side, and electrons are injected into the floating gate in order from the memory cell farthest from the bit line.