JPH0866536A - Distributed processing type hall computer device - Google Patents

Abstract

PURPOSE: To miniaturize a host computer and to call data when a fault occurs, etc., by connecting an island computer to a board computer with a twist pair line and the host computer to the island computer with a bus type LAN, respectively. CONSTITUTION: In a game field, the island computer 2 is connected to plural board computers 1 with the twist pair line 4 which performs bus system communication. Also, the bus type LAN 5 is installed in the game field, and a transceiver 6 as a branch take-out port is arranged at a prescribed part. Moreover, a transceiver cable 7 is connected to the transceiver 6. The host computer 3 and the island computer 2 are connected to the bus type LAN 5 with transceiver cables 7 installed at separate parts, and also, the host computer 3 is connected to the island computer 2 with the bus type LAN 5. While, terminating devices 8 are arranged on both termination of the bus type LAN 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hall computer system for collectively managing a plurality of computers contained in respective devices arranged at a plurality of places in a game arcade.

[0002]

2. Description of the Related Art In a game arcade, a game machine is arranged for each island, and a sand lending machine for lending pachinko balls, medals, etc., depending on the game machine, is carried from a sand lending machine. Each device such as a safe for temporarily storing money and a counting machine for counting the number of acquisition of value media such as pachinko balls and medals is arranged, and a host computer for collecting and collectively managing the data of these devices Is installed.

Conventionally, in order to input data to each of these devices, signal lines have been wired from each signal output terminal of each device to the input section of the host computer main body, so a large number of signal lines are wired in the island and in the game arcade. However, there is a problem in that the host computer becomes large in size, the installation space for the host computer becomes difficult to secure, the wiring work takes a long period of time, and the construction cost becomes high.

Further, conventionally, since the data of all the devices arranged in the game arcade are stored only by the host computer, when the host computer fails, the data is input and stored from each device. There are drawbacks that it is impossible to call the stored data, and all stored data are invalid.

Further, since the host computer and each device are connected by serial communication, the number of devices connectable to the host computer is limited by the number of interface ports provided in the host computer. There was a drawback that there is.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to make a host computer compact and to enable data input from each device and recall of stored data even when the host computer fails. It is an object of the present invention to provide a distributed processing type hall computer device capable of restoring stored data and having no limit on the number of devices connectable to a host computer.

[0007]

In order to solve the above-mentioned problems, the distributed processing type hall computer device of the present invention is installed for each gaming machine, and is used for gaming machines, sand lending machines, safes, and counting machines. A computer that collects data individually, an island computer that is installed on each island and that collects data collected by each computer on the island, a display unit for displaying the data, and a printing unit for printing And a host computer for collecting data collected by the island computer and having a key input operation unit for inputting instructions to the island computer and the platform computer, and between the island computer and each platform computer. A bus type LA is connected between the host computer and each island computer, which are connected by a twisted pair line for performing bus type communication. Wherein the in is connected.

Further, each computer is a gaming machine,
A second data storage area that has a first data storage area for storing and holding data input from a sand lending machine, a safe, and a counting machine for a certain period of time, and each island computer stores and retains data collected from each of the individual computers for a certain period of time. It has a storage area.

Further, the host computer, in order to perform communication on the bus type LAN, has the bus type LAN.
Via a memory device for setting an address required for each device connected to the host computer via the device, and each device requests the host computer to set its own address. In addition to the address setting request switch described above, there is provided an address storage unit for storing the self address sent to itself after the address setting request switch is activated, and an address storage area for storing the self address.

Furthermore, the host computer is
The island computer is provided with a download unit including a storage device that replaces a data collection program for collecting each data stored in the island computer or the stand computer with a new data collection program, and the island computer is associated with the new data collection program. And a data conversion saving means for matching the storage formats and storage addresses of all data stored in the first data storage area of the computer and the second data storage area of the computer.

[0011]

The platform computer collects and stores the data of the connected gaming machines, sand lending machines, safes, and counters individually. The island computer arranged on each island collects and stores the data collected by each computer on the island by performing bus-type data communication with the computer under the umbrella via a twisted pair line. The host computer performs data communication with each island computer connected via the bus LAN according to the command input from the key input operation unit, and collects the collected data of each individual computer collected by each island computer. The display unit displays the collected data on the screen, and the printing unit prints the collected data.

By connecting a host computer and a device for collecting and storing data by a bus LAN, it is possible to add a new island computer or to connect devices other than the island computer to the host computer indefinitely. To do.

Each computer stores the data input from the gaming machine, the sand lending machine, the safe and the counter in the first data storage area, and holds the stored data for a certain period.

Each island computer stores the data collected from each computer in the second data storage area and holds it for a certain period.

The host computer collects and stores the data collected by each island computer, displays the collected data on the display unit and prints the data by the printing unit, and the contents input by the operation input from the key input operation unit. To the island computer and the platform computer.

The host computer activates the address setting means composed of a storage device, and turns on the address setting request switch provided in each device connected to the host computer via the bus type LAN to turn on its own address. When the setting is requested to the host computer, in response to this, the address setting means determines the address required for each device connected to the host computer via the bus type LAN and transmits the address to the bus type LAN. The island computer stores the self address sent from the host computer by the address storage means in the address storage area in which the self address is stored.

When the data collection program for each data collection stored in the island computer is replaced with the new data collection program, the island computer is stored in the first data storage area together with the address of the host computer. The host computer, which has transmitted the data to the bus type LAN and has received the data, matches the storage format and the storage address of all the received data of the island computer in correspondence with the new data collection program to be downloaded by the data conversion storage means. Data and the new data collection program together with the address of the island computer are transmitted to the bus type LAN by the download means, and the island computer which receives them transmits the consistent data. And new data collection program respectively To 憶.

When replacing the data collection program stored in the base computer for each data collection with a new data collection program, the base computer replaces all the data stored in the second data storage area with the base computer. When it receives these, the island computer sends all the data received from the host computer together with the address of the host computer to the bus type LAN, and the host computer receiving this sends the data conversion storage means. In accordance with the new data collection program to be downloaded, the storage formats and storage addresses of all the received data of the base computer are matched, and by the download means, the matched data and the new data collection program are linked to the base computer. With the address of The island computer, which has transmitted these data to the LAN and has received them, transmits the consistent data received from the host computer to the computer and the new data collection program, and the computer which has received these data, The consistent data and the new data collection program are stored respectively.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts of a distributed hall computer device according to the present invention. In the game arcade, a computer 1 is installed for each game machine installed on each island,
An island computer 2 is installed for each island, and a host computer 3 for collectively managing each device installed in the game arcade is installed.

The island computer 2 and a plurality of individual computers 1 in the island on which the island computer 2 is installed are connected by a twisted pair wire 4 for bus communication.

A bus-type LAN 5 is laid in the game arcade, transceivers 6 are provided as branch outlets at predetermined locations on the bus-type LAN 5, and a transceiver cable 7 is connected to each transceiver 6. With respect to the bus LAN 5, the host computer 3 and each island computer 2 installed on each island are connected to transceiver cables 7 at different predetermined locations.
The host computer 3 and each island computer 2 are connected by a bus type LAN 5. Reference numeral 8 is a bus type LA
It is a terminating device provided at both ends of N5.

If the required number of transceivers 6 are provided in advance when the bus LAN 5 is laid, the island computer 2 can be additionally connected to the bus LAN 5 as the island expands. As shown in FIG. 1, a prize POS 9 other than the island computer 2 or another device 10 such as a crime prevention terminal can be connected.

As shown in FIG. 2, the host computer 3 stores and stores a host CPU 11 which is a processing executing means, an address setting means, a program downloading means, a data conversion saving means which is executed at the time of executing the downloading means, and the like. A rewritable memory and a memory 12 composed of a RAM as a working area used when executing these means, a collected data memory 1 for storing and holding collected data for a specific period of time.
3 and a communication interface 14 for transmitting and receiving via the bus type LAN 5, and the host CPU 11 has a display unit 1 including a CRT device for displaying data and the like.
5. A printing unit 16 for printing and a key input operation unit 17 for inputting the contents to be instructed to the island computer and the platform computer are respectively connected.

The island computer 2 is, as shown in FIG.
The island CPU 18 which is a process executing means, a rewritable memory in which an execution program of the island CPU 18 is stored and stored, a memory 19 configured by a RAM as a working area used when executing these means, and each computer 1 A collection data memory 20 is provided as a second data storage area for exclusively storing and holding collection data from the computer for a certain period of time, and a communication interface 21 for transmitting and receiving via the bus type LAN 5 and a base computer 1 An address setting request switch S for requesting the host computer 3 to set its own address is provided with communication interfaces 22 and 23 for transmission and reception.
W1 is the island CPU1 via the input / output unit 24 of the island CPU18.
8 is connected.

The address storage means for storing the self-address sent to itself after the operation of the address setting request switch SW1 is an island C stored in the memory 19.
An address storage area, which is a part of the execution program of the PU 18 and stores its own address, is a part of a working area provided in the memory 19.

The base computer 1 is, as shown in FIG.
A base CPU 25 which is a process executing means, a rewritable memory in which an execution program of the base CPU 25 is stored and stored, a memory 26 constituted by a RAM as a working area used when executing these means, and a base C
The CPU 25 has a collection data memory 27 as a first data storage area for exclusively storing and holding the data collected by the PU 25 for a certain period of time, a communication interface 28 for communicating with the island computer 2, and a process of the base CPU 25. An input / output unit 29 for inputting / outputting various signals necessary for operation is provided, and an address setting request for requesting the host computer 3 to set its own address to the host CPU 25 via the input / output unit 29. The switch SW2, the game machine 30, the sand lending machine 31, the safe 32, and the counter 33 are connected.

The address storage means for storing the self-address sent to itself after the operation of the address setting request switch SW2 is the base C stored in the memory 26.
An address storage area, which is a part of the execution program of the PU 25 and stores its own address, is a part of a working area provided in the memory 26.

Further, the collected data memory 27 has a table CP.
Amusement machines 30 and sand rental machines 3 collected by U25
1, various data of the safe 32 and the counter 33 are stored and held respectively.

The operation of this embodiment will be described below with reference to the processing flowchart of the host CPU 11 shown in FIGS. 6 to 16, the processing flowchart of the island CPU 18 shown in FIGS. 17 to 30, and the processing flowchart of the base CPU 25 shown in FIGS. 31 to 39. Will be described with reference to.

First, the host CPU 11 is the bus type LAN 5
An address setting process will be described in which the host CPU 11 allocates the physical addresses of the island CPU 18 and the individual CPUs 25 provided for each island, which are required for communication via the.

Physical addresses of each island computer 2, prize POS 9 and other equipment 10 connected to the host computer 3 shown in FIG. 1 via the bus type LAN 5 and each island computer 2 via a twisted pair line 4. The physical address of each computer 1 connected by the above is not set.

First, as an address setting procedure, the addresses of the island computer 2, the prize POS 9, and the other device 10 that are directly connected to the host computer 3 shown in FIG. 1 by the bus LAN 5 are determined, and then the steps shown in FIG. Table computers 1 (1) to 1 (4) under the umbrella of the island computer 2 (1) arranged in the stripe and table computers 1 (5) belonging to the island computer 2 (2) arranged in the stripe 2 ) -1 (8) addresses are determined.

Specifically, the host computer 3 is turned on by sequentially turning on the address request setting switch SW1 provided in each island computer 2 and the address request setting switch SW2 provided in each computer 1. In response to the address request, the host computer 3 transfers the predetermined address data when receiving these address request signals, and each computer receives and stores the address data.

When the address is set, the address setting processing mode is set in the host CPU 11 by the key operation of the key input operation unit 17 of the host computer 3 in FIG.

As shown in FIG. 6, first, the host CPU 1
Since it is determined whether or not 1 is the address setting processing mode (step a1), it is determined to be true and step a
9 address setting processing is performed. As shown in FIG. 7, the start island number and the end island number are keyed by key operation of the key input operation unit 17 of the host computer 3.
The host CPU 11 stores the key-entered start island number in the island number storage register SN1 (step a2).
0), end island number, end island number storage register SN2
To the address setting register A (step a21).
The initial address value is set in D (step a22), and
The address request signal by the ON operation of the address setting request switch SW1 from the island computer 2 (1) arranged in one stripe shown in FIG.

Island computer 2 arranged in one stripe
When the address setting request switch SW1 of (1) is turned on, the island CPU 18 first determines whether the address setting request switch SW1 is on (step b1), as shown in FIG. Then, the island CPU address request command is transmitted to the bus type LAN 5 (step b12).

The host CPU 11 side determines in step a23 of FIG. 7 whether or not there is a request signal from the island CPU 18, and when an island CPU address request command is received from the bus type LAN 5 (step a23). The address value stored in the island number storage register SN1 and the address setting register AD is stored in the island CPU 18 as a bus type L.
It is transmitted to AN5 (step a24), and the address stored in the address setting register AD is stored in a predetermined storage area of the memory 12 in association with the island number stored in the island number storage register SN1 (step a2).
5).

Thereafter, the host CPU 11 increments the value of the island number storage register SN1 by 1 (step a2).
6) One value is updated in the address setting register AD (step a27), and it is determined whether the value in the island number storage register SN1 exceeds the value set in the end island number storage register SN2 (step a27). a28), it is determined whether or not the address setting of the all-island computer 2 directly connected to the bus type LAN 5 by the host CPU 11 is completed.

When it is determined by the determination processing in step a28 that the value of the island number storage register SN1 does not exceed the value set in the end island number storage register SN2, the bus type LAN 5 is directly connected. It means that the address setting of the all-island computer 2 is not completed. In this case, the host CPU 11 executes the step a2.
Returning to the determination processing of 3, waiting for the input of the address request signal by the address setting request switch SW1 of the next island CPU 18, each time the input of the address request signal is detected, the address value is sequentially updated by the processing of steps a24 to a27. Then, the address value is data-transferred and set to all island computers 2 connected to the bus type LAN 5, and the current value stored in the address setting register AD in association with the island number is set by itself. It is stored in a predetermined storage area of the memory 12.

As described above, if the required number of transceivers 6 is provided in advance when the bus LAN 5 is laid, the island computer 2 is newly added to the bus LAN when the island is expanded.
When an extension connection is made with respect to 5, a new address can be set corresponding to the input and set island number on the software by turning on the address setting request switch SW1.

In step a24 of FIG. 7, the host CP
The value of the address set in the island number storage register SN1 and the address setting register AD transmitted from U11 on the bus LAN 5 is received by the island CPU 18 by the process of step b13 of FIG. 18, and the island CPU 18 receives it. The address received corresponding to the island number is stored in the memory 19
(Step b14).

If the island number is entered by mistake,
By setting and inputting the correct island number for the start island number and the end island number using the key input operation unit 17, the host CP
Although the updated address is set as the address in U11, the updated address can be corrected and stored in correspondence with the correct island number.

When it is determined by the determination processing of step a28 shown in FIG. 7 that the address setting of the all-island computer 2 directly connected to the bus LAN 5 by the host CPU 11 is completed, the host CPU 11 and the host CP are
This means that the U11 has established data communication with the all-island computer 2 directly connected to the bus LAN 5.

Although not shown in the flow chart of FIG. 7, the prize POS 9 and the other device 10 shown in FIG.
An address setting request switch for requesting the host computer 3 to set its own address is provided, and an address storage means and a self address for storing the self address sent to itself after the address setting request switch is operated are stored. In the example shown in FIG. 1, the start device number input from the host computer 3 is 1, the end device number is 2, and each address setting request switch is operated in sequence to give a prize POS9. Is assigned as the device number 1, and the address value is assigned as the other device 10 as the device number 2.

After this processing, the host CPU 11 sends the address corresponding data of all the devices stored in the predetermined storage area of the memory 12 connected to the bus type LAN 5 to all the devices connected to the bus type LAN 5. The data is sequentially transmitted to the devices (step a29). That is, the command for island address storage is sent along with the address of the device to be transmitted to the bus type L.
The bus type L is transmitted to the AN5 and then stored in the memory 12 shown in FIG. 2 together with the device address of the transmission target.
The address corresponding data of all devices connected to AN5 is transmitted. At this time, the address data of the host CPU 11 is also transmitted. Although not shown, the address of the host CPU 11 is, for example, address 1
It is assumed to be preset such as 00.

After the determination of step b1 and step b2, the island CPU 18 determines true by the determination processing of whether or not the command is the island address storage command of step b15 of FIG. 19, and the bus type LAN 5 including the address of the host CPU 11 The address corresponding data of all the devices connected to the device are received (step b22), the received address corresponding data of all the devices are stored in the memory 19 (step b23),
The address 11 and the storage end reply are transmitted to the bus type LAN 5 (step b24).

When the host CPU 11 receives the end response from the island CPU 18, it sends the address corresponding data of all the devices connected to the bus LAN 5 to the device connected to the next bus LAN 5 (step). a2
9).

By this processing, for example, the address of the host computer 3 is added to the island computer 2 (1) shown in FIG.
Address of island computer 2 (2), prize P shown in FIG.
Since the addresses of the OS 9 and the other device 10 are stored in the memory 19 shown in FIG. 3, even if the host computer 3 loses its function, the island computer 2 (1)
Thus, it becomes possible to perform data communication with all devices connected to the bus type LAN 5.

When the processing in step a29 is completed, the host CPU 11 waits for the input of the start console number and the end console number, as shown in FIG. When the start console number and the end console number are keyed in by the key operation of the key input operation unit 17 of the host computer 3, the host CPU
11 stores the start console number keyed in in the console number storage register DN1 (step a30), stores the end console number in the end console number storage register DN2 (step a31), and allocates it to one stripe shown in FIG. An address request signal by turning on the address setting request switch SW2 from the table CPU1 (1) under the umbrella of the installed island computer 2 (1) is awaited for reception (step a32).

Base computer 1 arranged in one stripe
When the address setting request switch SW2 of (1) is turned on, as shown in FIG. 31, the base CPU 25 first determines whether the address setting request switch SW2 is on (step c1). Then, the base CPU address request command is transmitted to the island CPU 18 (step c12).

When the island CPU 18 receives the base CPU address request command, the island CPU 18 determines in step b3 shown in FIG. 17 whether or not there is a communication command from the base CPU 25 as true, and in step b70 for the base CPU. The determination process of whether or not it is an address request command is determined to be true, and the address of the host CPU 11 and its own address
The PU address request command is transmitted to the bus type LAN 5 (step b71).

The host CPU 11 receives the base CPU address request command from the island CPU 18 from the bus type LAN 5 (step a32), and sets the received address of the island CPU 18 as the head portion, and then the current value of the address setting register AD. An address for the base CPU is additionally created, and the base CPU address and the base number stored in the base number storage register DN1 for the base CPU25 are transmitted to the bus type LAN 5 (step a33), and the island of the transmission partner is transmitted. The address of the CPU 18 is set to the address setting register AD
The address-corresponding data of the base computer 1 added to the head of the address value stored in (1) is stored in a predetermined storage area of the memory 12 in association with the base number stored in the base number storage register DN1 ( Step a3
4).

The island CPU 18 proceeds to step b72 in FIG.
The unit number and the unit CPU address transmitted from the host CPU 11 are received from the bus-type LAN 5 in the processing of 1. and the unit number and the unit CPU address are transmitted to the unit computer 1 (1) that requested the address (step b73). ).

The base CPU 25 proceeds to step c13 of FIG.
Unit number and unit CP transmitted from island CPU 18 in the processing of
The U address is received, the received base CPU address corresponding to the received base number is stored in a predetermined storage area of the memory 26 (step c14), and a storage completion reply is transmitted to the island CPU 18 ( Step c15).

The island CPU 18 receives the transmitted reply of completion of storage from the platform CPU 25 of the platform computer 1 (1) (step b74).

The host CPU 11 executes step a3 in FIG.
After the processing of 2, the value of the unit number storage register DN1 is incremented by 1 (step a35), the value of the address setting register AD is updated by 1 (step a36), and the value of the unit number storage register DN1 is stored as the end unit number. Whether the address setting of the island computer 2 (1) and all computers 1 under the island computer 2 (2) has been completed by determining whether the value set in the register DN2 is exceeded (step a37). Determine whether or not.

If the value of the machine number storage register DN1 does not exceed the value set in the end machine number storage register DN2 by the discrimination processing of step a37, the address setting of all the machine computers 1 is not completed. In this case, the host CPU 11 returns to the determination processing in step a32 and returns to the next computer 1.
Waiting for the input of the address request signal by the address setting request switch SW2 in (2), each time the input of the address request signal is detected, the address is sequentially updated by the processing of steps a33 to a37, and the island of one stripe shown in FIG. Computer 1 under the computer 2 (1)
Addresses are set for (2), 1 (3), and 1 (4), and the address for the machine CPU is stored in a predetermined storage area of the memory 12 in association with the machine number.

Then, the island computer 2 of 1 Shima (1)
When the setting of the addresses for the base computers 1 (1) to 1 (4) under the control of 2 is completed, the base computers 1 (5) to 1 under the control of the 2-strip island computer 2 (2)
Similarly, by sequentially turning on the address setting request switch SW2 of (8), the computer 1 (5)-
The address setting for 1 (8) is completed.

If the result of the determination process of step a37 shown in FIG. 8 is true and it is determined that the address setting of all the base computers 1 is completed, the host CPU 11
Data communication has been established with all the base computers 1 (1) to 1 (8), and the host CPU 11 causes all the devices connected to the bus type LAN 5 to all the base computers 1 (1) to 1 (1). The address corresponding data of (8) is sequentially transmitted to each device. That is, a command for storing the machine address is transmitted together with the address to be transmitted to the bus type LAN 5, and then all the machine computers 1 (1) to 1 (8) stored in the memory 12 shown in FIG. The address corresponding data is transmitted (step a38).

The island CPU 18 executes the step b after the judgment of the step b1, the step b2 and the step b15 of FIG.
It is determined to be true by the determination process of whether or not the command is for storing 16 platform addresses, the address corresponding data of all platform computers 1 are received (step b25), and the received address corresponding data of all platform computers 1 are stored in the memory. It is stored in 19 (step b26), and the address of the host CPU 11 and the storage end reply are transmitted to the bus type LAN 5 (step b27).

When the host CPU 11 receives the end response from the island CPU 18, it sends the address corresponding data of all the base computers 1 to the equipment connected to the next bus type LAN 5, and the bus type LAN 5 The address corresponding data of all the stand-by computers 1 are transmitted to the devices connected to, and the address corresponding data of all the stand-by computers 1 are stored in each device connected to the bus LAN 5 (step a38).

By this processing, for example, the island computer 2 (2) shown in FIG.
Since the addresses of the base computers 1 (1) to 1 (4) under the control of the computer are stored in the memory 19, the 1-base computer 1
Data communication with (1) to 1 (4) can be performed.

Next, a data collection process performed by the table CPU 25 of the table computer 1 will be described. 31 and 3
2 is a flowchart showing a main routine of a process performed by the base CPU 25. The platform CPU 25 first performs a process of determining whether or not an address request signal is input by turning on the address setting request switch SW2 (step c1). If no address request signal is input, then the island CPU 18 From the island CPU 18 is performed (step c2). If there is no communication command from the island CPU 18, the closing processing end flag F1 is executed.
Is performed to determine whether the closing process is completed (step c3). If the value of the closing process end flag F1 is not the value 1 that defines the end, a predetermined process is performed. By repeatedly executing the processes of steps c4 to c11 in a cycle, as shown in FIG. 4, various data from the gaming machine 30, the sand lending machine 31, the safe 32 and the counter 33 connected to the base computer 1 Are periodically collected and updated and stored in the collected data memory 27.

The process shown in steps c4 to c7 is a process for collecting various data from the gaming machine 30, and the base CPU 25 indicates, for example, if the gaming machine 30 is a pachinko gaming machine, an out indicating the number of out balls. Data input process (step c4), safe data input process showing the number of safe balls (step c5), special prize signal input process showing big hit occurrence (step c6), starting signal input showing that the symbol is changing due to winning of the starting mouth The processing (step c7) is sequentially performed and is temporarily stored in the memory 26 as gaming machine data.

Next, the stand CPU 25 performs the sand renting machine signal input processing, temporarily stores the sand renting machine data input from the sand renting machine 31 in the memory 26 (step c8), and performs the safe signal input processing to perform safe deposit. The safe data input from 32 is temporarily stored in the memory 26 (step c9), the counter signal input processing is performed, and the counter data input from the counter 33 is temporarily stored in the memory 26 (step c10). Each of the temporarily stored gaming machine data, sand renting machine data, safe data, and counter data is stored in the collected data memory 27 (step c11).

Next, the respective data of the gaming machine 30, the sand lending machine 31, the safe 32, and the counter 33 which are stored and held by the respective CPUs 1 under the island CPU 18 performed by the island CPU 18 of the island computer 2 are collected. The data collection process will be described.

FIG. 17 is a flow chart showing the main routine of the processing performed by the island CPU 18. Island CPU18
First, it determines whether or not the address request signal is input by turning on the address setting request switch SW1 (step b1). If the address request signal is not input, then on the bus LAN 5 Is performed to determine whether or not there is a communication command from (step b
2).

The determination processing in step b2 is the bus type LAN.
5 is the address sent together with the communication command as to whether the communication command sent to the island computer 18 is for the island computer 18 or for one of the plurality of computers under the island computer 2 Is a process for determining the value of the value, the island CPU 18 is a bus LAN
If it is determined that the communication command transmitted on the 5 is related to the own island, it is determined to be true and step b
On the other hand, when it is determined that the communication command is not related to the own island, the process proceeds to step b3 and subsequent steps while the process proceeds to step 15 and subsequent steps.

In the determination processing of step b2, the island CPU1
8 compares the value of the address transmitted on the bus LAN 5 with its own address stored in a predetermined storage area of the memory 19, and if they match, determines that it is a communication command for itself.

When the communication command for the base computer 1 is transmitted on the bus type LAN 5, when the host CPU 11 transmits the communication command, the address of the island computer 2 is set to the head part of the address of the base computer 1. Since it is transmitted to the bus type LAN 5 by adding to the address, the island CPU 18 compares the beginning part of the value of the address transmitted to the bus type LAN 5 with its own address, and if they match, It is determined that the command is a communication command for the base CPU 25 belonging to the island.

In step b3, the island CPU 18 determines whether or not there is a communication command from the platform CPU 25. If it is determined in this determination process that there is a communication command from the base CPU 25, the island CPU 18
Shifts to the processing of step b70 and thereafter, while the unit CP
If it is determined that there is no communication command from U25,
Control goes to step b4.

The island CPU 18 performs a data collection process for collecting data from each of the CPUs 25 under the umbrella by the processing loop formed by steps b4 to b10.

The island CPU 18 is under the control of each computer 1 connected via the twisted pair wire 4, for example, as shown in FIG. Each computer 1
(1) to 1 (4) are the gaming machine 30 and the sand lending machine 3 stored in the respective collected data memory 27 shown in FIG.
It is determined whether or not the process of collecting the data of 1, the safe 32 and the counter 33 from each computer 1 (1) to 1 (4) has started (step b4). In the case of 1 stripe in 5, the first 1 of the plurality of unit computers 1 (1) to 1 (4) under the umbrella
The platform, that is, the platform computer 1 (1) is selected by setting the value of the platform index register i to 1 (step b5), and the data collection process shown in steps b6 to b10 is started.

When the island CPU 18 proceeds to step b6, it sends a data request command to the platform CPU 25 of the platform computer 1 (1) (step b7).

Computer 1 designated as a transmission partner
Upon receiving the data request command, the stand CPU 25 of (1) receives the data request command, and after the determination in step c2 of FIG.
37, a data request command is detected and the process proceeds to step c28 in FIG. 37, and the collected data memory 2 shown in FIG.
Each of the game machine data, the sand renting machine data, the safe data, and the counter data currently stored is read from 7 and transmitted to the island CPU 18.

The island CPU 18 receives each data from the table CPU 25 of the table computer 1 (1) of the transmission partner (step b7), and stores the game machine data and the sand in a predetermined storage area of the collected data memory 20 shown in FIG. Update and store each of the rental machine data, safe data, and counter data (step b
8).

Next, the island CPU 18 increments and updates the value of the table index register i (step b9), and compares the updated value of the table index register i with the number of connected plural computers 1 of the tables. By doing so, it is determined whether or not the data collection processing from all the computers 1 under the umbrella has been completed (step b1).
0).

If the value of the base index register i does not exceed the number of connected base computers 1, data collection processing from the base computer 1 is in progress, so the island CPU 18
Returns to step b4, determines true, performs the processing of step b6 and subsequent steps, and based on the updated value of the table index register i, the table C of the next table computer 1 (2).
A data request command is transmitted to PU25.

Thereafter, the value of the platform index register i is updated by the processing loop formed by steps b4 and b6 to b10, and data request commands are sequentially transmitted to the platform CPU 25 of each of the computers 1 (i) under its control. Then, the data is received from each computer 1 (i) and updated and stored in a predetermined storage area of the data collection memory 20 for each of the gaming machine data, the sand renting machine data, the safe data, and the counter data.

When the value of the base index register i exceeds the number of connected base computers 1, the CPUs of all the base computers 1 (1) to 1 (4) under its control
It is determined that the data collection process from 25 is completed (step b10), and the island CPU 18 determines that the platform index register i
Is initialized and the process returns (step b11).

Next, the opening process, the in-business process, the closing process, and the program download process performed by the host computer 3 will be described.

FIG. 6 is a flow chart showing the main routine of the processing executed by the host CPU 11, and the host CP
The U11 first determines each processing mode set by the key input from the key input operation unit 17 through a series of determination processing from step a1 to step a6, and when determined to be each processing mode, it is determined. After performing the process corresponding to the process mode, the process proceeds to the display process of step a7. Further, when all the determination results of the series of steps a1 to a6 are negative, the process proceeds to the display process of step a7. The host CPU 11 performs step a
After the display process of 7, the printing process of step a8 is performed and the process returns.

The display process is a process for outputting the data written in the screen area set in the memory 12 of FIG. 2 to the display unit, and the print process is the print area set in the memory 12. This is a process of outputting the data written in the print section to the printing unit.

First, the host CPU 11 performs the above-mentioned determination processing as to whether it is in the address setting processing mode (step a1). If it is not in the address setting processing mode, then it determines whether it is in the setting input processing mode. Is performed (step a2), and if it is not the setting input processing mode, it is determined whether or not it is the opening processing mode (step a2).
3) If it is not the opening processing mode, it is determined whether it is the processing mode during business (step a4). If it is not the processing mode during business, it is determined whether it is the closing processing mode. (Step a5) If it is not the closing processing mode, it is determined whether or not it is the download processing mode (step a6). If it is not the download processing mode, the display processing of step a7 is performed.

In the setting input processing mode, the host CPU 11 determines that the determination processing in step a2 is true and performs the setting input processing in step a10. The setting performed in the setting input process is, as an initial setting, the gaming machine 3
0, number setting of sand lending machine 31, safe 32 and counter 33, unit price and exchange rate of balls and coins, affiliation of gaming machine 30 (setting of island to which each gaming machine belongs, model, game type), Settings related to the input signal of the sand renting machine 31, settings of wiring connection in the island computer 2 of renting machines and counters other than the sand renting machine 31, setting of correspondence relationship between the sand renting machine 31 and the gaming machine 30, hall name and model name Enter the name such as, and set the business settings such as stop setting, advance warning setting, caution board, abnormal board and end table setting, automatic clear setting, data on / off time setting, replenishment format setting, broadcast setting Then, the function keys in the key input operation unit 17 are set.

Next, the opening process will be described. When the store opening processing mode is set by the key input of the key input operation unit 17 of the host computer 3, the determination result of step a3 is determined to be true, and the store opening processing shown in FIG. 9 is started.

The host CPU 11 has a key input operation unit 17
It is determined whether or not there is a store opening operation input from (step a40). When there is a store opening operation input, the key input start island number is stored in the island number storage register SN1 (step a41), and the end island is stored. The number is stored in the end island number storage register SN2 (step a42), and an opening command is transmitted to the bus LAN 5 together with the address of the island CPU18 of the island corresponding to the start island number stored in the island number storage register SN1. (Step a43).

When the island CPU 18 designated as the transmission partner receives the opening command from the bus type LAN 5, the island CPU 18 detects the opening command by the judgment processing of step b17 after the judgment of steps b2, b15 and b16, and FIG.
The process proceeds to step b28 shown in FIG. 9 to initialize various flags and the like necessary for the processing set in the work area on the memory 19 (step b28), and then, for example, in the case of 1 stripe in FIG. Nodai computer 1
The first one of (1) to 1 (4), that is, the base computer 1 (1) is selected by setting the value of the base index register i to 1 (step b29), and the base computer 1 (1) is selected. An opening command is transmitted to the stand CPU 25 (step b30).

Computer 1 designated as the transmission partner
When the stand CPU 25 of (1) receives the opening command,
After the determination in step c2 of FIG. 31, the opening command is detected in the determination processing of step c17, and step c21 of FIG.
And the contents of the memory 26 are initialized (step c2
1), the closing process end flag F1 is cleared to 0 to be unprocessed (step c22), the end reply is transmitted to the island CPU 18 (step c23), and the process returns.

When the island CPU 18 receives the end reply from the table CPU 25 of the table computer 1 (1) of the transmission partner (step b31), it updates the value of the table index register i (step b32) and the updated table index. By comparing the value of the register i with the number of connected plural computers 1 under its control, it is judged whether or not the transmission processing of the opening command to all the computer 1 under its control is completed (step b33). Stand index register i
If the value of does not exceed the number of connected base computers 1, it means that the opening command is being transmitted to the base computer 1. Therefore, the island CPU 18 returns to step b30 and updates the value of the base index register i. Based on this, an opening command is transmitted to the base CPU 25 of the next base computer 1 (2). Hereinafter, steps b30 to b
By the processing loop formed by 33, the value of the table index register i is updated and a store opening command is sequentially transmitted to the table CPU 25 of each computer 1 (i) under its control.

When the value of the base index register i exceeds the number of connected base computers 1, the CPUs of all the base computers 1 (1) to 1 (4) under the control of each base CPU.
It is determined that the transmission processing of the opening command to 25 is completed (step b33), and the island CPU 18 transmits the completion reply together with the address of the host CPU 11 to the bus LAN 5 (step b34).

When the host CPU 11 receives the completion reply from the island CPU 18 designated as the transmission partner from the bus LAN 5 (step a44), the island number storage register SN.
The value of 1 is incremented by 1 (step a45), and it is determined whether or not the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2 (step a46). CPU11
All island CPUs directly connected to the bus LAN 5
It is determined whether or not the opening processing of all the computers 1 under the control of 18 is completed.

If the value of the island number storage register SN1 does not exceed the value set in the end island number storage register SN2 by the determination processing of step a46, it means that the opening process is not completed. In this case, , The host CPU 11 returns to step a43 and returns to island C of the next island.
An opening command is transmitted to PU18. Host CPU 11
Executes the processing loop formed by steps a43 to a46 to update the value of the island number storage register SN1 to sequentially specify the island computer and transmit the opening command.

When the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2, the host CPU 11 determines that the store opening processing has ended by the determination processing of step a46, and the processing mode is set to open. The mode is switched to the middle processing mode (step a47), and the store opening processing is ended.

Next, the in-business process of step a12 of FIG. 6 will be described. When the store opening process ends and the processing mode is switched to the business process mode, the determination result of step a4 is determined to be true, and the business process shown in FIG. 10 is started.

The host CPU 11 first determines whether or not the in-business process mode is canceled (step a5).
0). It should be noted that the cancellation of the processing mode during business is automatically canceled at the time when the closing processing mode is set and input by the key input of the key input operation unit 17, because the processing mode is switched from the processing mode during business to the closing processing mode. . When the host CPU 11 determines in the determination processing of step a50 that the in-business-time processing mode has been canceled, the host CPU 11 returns without performing the processing and ends the in-business processing.

When the host CPU 11 determines in the determination processing of step a50 that the in-business process mode has not been released, the host CPU 11 proceeds to step a51, and the key input operation unit 17
It is determined whether or not there is an input from (step a51),
If there is no input, the determination processing of step a51 and step a50 is repeated, and the input to the key input operation unit 17 is awaited.

When the machine number and the command are input by the key input of the key input operation unit 17, it is determined to be true and the process proceeds to step a52. The command entered in this case is
Control command for the base computer 1 and data collection memory 2 of the island computer 2 for the island computer 2
Data request command for calling the collected data relating to the base computer 1 stored in 0.

First, the case where a control command is input will be described. For example, when a control command such as stop or release is input, the host CPU 11 determines that the determination processing in step a51 is true, and inputs it together with the address for the platform CPU of the platform computer 1 corresponding to the entered platform number. The control command thus generated is transmitted to the bus type LAN 5 (step a53).

The base CPU address and the control command transmitted on the bus LAN 5 are received by the island computer 2, and the island CPU 18 of the island computer 2 executes the step b1.
In the determination processing of step b2 after the determination of
By determining whether or not the head portion of the U address matches the self address, it is determined whether the received control command is transmitted to the base computer 1 under its control, and the island computer 2 If it is transmitted to the base computer 1 under its control, the island CPU 18 determines that it is true, and detects the command received in the determination processing after step b15.

In this case, since the received control command is a command for the base CPU 25, the island CPU 18
Determines that all the determination processes of steps b15 to b19 are false, determines that the determination process of step b20 is true, and proceeds to step b52 of FIG.

Island CPU 18 moved to step b52
Transmits the received control command to the base CPU 25 of the base computer 1 corresponding to the latter half address of the received base CPU address (step b52).

Sending partner's table Computer 1's table CPU 2
In step 5, after the determination of steps c1 and c2, the process proceeds to step c16, and after the determination process of steps c16 to c18 is determined to be false, the communication command received by the determination process of step c19 is a control command. Is detected, the process proceeds to step c29 in FIG. 38, and control processing corresponding to the content of the control command is performed (step c29). For example, if the control command is to stop, the shooting stop command or the like is output to the gaming machine 30 to stop the gaming machine 30, and if the control command is open, to the gaming machine 30. A stop release command is output and the game machine 3
0 can be played.

After the processing of step c29, the base CPU 25
Transmits a response indicating that the processing is completed to the island CPU 18 (step c30).

When the island CPU 18 receives the processing end response from the base CPU 25 of the destination computer 1 (step b53), it transmits the end response together with the address of the host CPU 11 to the bus LAN 5 (step b54). ).

The host CPU 11 receives an end response to the control command from the island CPU 18 from the bus type LAN 5 (step a53), and ends the present business process. In addition, the island CPU for the transmitted control command
The end response to the control command from 18 is displayed on the display unit 15 by the display processing performed after step a12, as shown in FIG.

Since the in-business process mode is set unless it is canceled by the setting input of the closing process mode from the key input operation unit 17, in the next main routine of the host CPU 11, the in-business process of step a12 is executed. Then, the host CPU 11 executes the step a.
The process returns to step 50 and waits for release of the processing mode during business and for waiting for input to the key input operation unit 17.

Next, a case where a data request command is input at the time of inputting step a51 will be described. When the data request command is input, the host CPU 11 determines that the determination processing in step a51 is true, and the input control command is bus type along with the base CPU address of the base computer 1 corresponding to the input base number. It is transmitted on the LAN 5 (step a53).

The base CPU address and the data request command transmitted on the bus LAN 5 are received by the island computer 2, and the island CPU 18 of the island computer 2 receives them in the discrimination processing of step b2 after the discrimination of step b1. It is determined whether or not the received control command is transmitted to the platform computer 1 under its control by determining whether or not the leading portion of the address for the platform CPU matches the self address, and the island If it is transmitted to the base computer 1 that is under the control of the computer 2, the island CPU 18 determines that it is true and detects the command received in the determination processing after step b15. The processing up to this point is the same as when the control command is input.

In this case, since the received command is the data request command, the island CPU 18 proceeds to step b.
15, step b16, step b17 and step b
It is determined that all the determination processes up to 18 are false, and step b19
27 is determined to be true, and the process proceeds to step b51 in FIG.

Island CPU 18 moved to step b51
Reads the collected data about the platform computer 1 corresponding to the received platform CPU address from a predetermined storage area of its own data collection memory 20,
The collected data concerning the base computer 1 read out together with the address 1 is transmitted to the bus type LAN 5 (step b51).

The host CPU 11 receives the response to the data request command from the island CPU 18, that is, the collected data on the platform computer 1 corresponding to the platform number keyed in, from the bus type LAN 5 (step a53). The process ends. The received collected data regarding the base computer 1 is displayed on the display unit 15 by the display processing of step a7 performed after step a12, and further, step a13 as shown in FIG.
It is printed by the printing process of. In this case as well, since the in-business process mode is set unless it is canceled by the setting input of the closing process mode from the key input operation unit 17, in the next main routine of the host CPU 11, the in-business process of step a12 is executed. The Rukoto.

Next, the store closing process in step a13 of FIG. 6 will be described. When the store closing mode is set by the key input of the key input operation unit 17 of the host computer 3,
After the in-business process is completed, the determination result of step a5 is determined to be true, and the closing process shown in FIG. 11 is started.

The host CPU 11 has a key input operation unit 17
It is determined whether or not there is a store closing operation input from (step a60), and when there is a store closing operation input, the key input start island number is temporarily stored and stored in the island number storage register SN1 (step a61). ), The end island number is temporarily stored and is also stored in the end island number storage register SN2 (step a62), and the island number storage register SN1 is stored.
Island CP corresponding to the start island number stored in
Bus type LAN with closing command together with U18 address
5 (step a63).

When the island CPU 18 designated as the transmission partner receives the closing command from the bus type LAN 5, the step b1, the step b2, the step b15, and the step b1.
6, after the determination in step b17, a closing command is detected in the determination processing in step b18, and step b35 shown in FIG.
Then, the process of transmitting a closing command to each of the computers 1 under the umbrella is started.

Processing of Step b35 and Step b36
Through the processing loop formed by step b39,
The processing of step b29 and step b30 of transmitting the store opening command to each computer 1 in FIG.
Since the algorithm is the same as the algorithm of the processing loop formed by step b33 and only the closing command is transmitted instead of the opening command, detailed description will be omitted.

The computer 1 designated as the transmission partner by the closing command transmission processing in step b36 of FIG.
The processing of the base CPU 25 will be described below.
5, after the determination of step c1 and step c2 of FIG. 31, the process proceeds to the determination process of step c16 and subsequent steps, further determines that the communication command received in the determination process of step c17 is a closing command, the step of FIG. Move to c24.

The stand CPU 25 prohibits signal input from the address setting request switch SW2, the gaming machine 30, the sand lending machine 31, the safe 32 and the counter 33 (step c2).
4), the current game data, sand renting machine data, safe data, and counter data stored in the collected data memory 27 are stored and held as the final data as they are (step c25), and the closing process completion flag F1 indicates that processing has been completed. The prescribed value 1 is set (step c26), and the end reply is transmitted to the island CPU 18 (step c27).

Note that the platform CPU 25 returns after the process of transmitting the end response in step c27, and therefore, if the determination results of steps c1 and c2 are both false, the process proceeds to the determination process of step c3. In this case, since the value of the closing process end flag F1 is 1, the CPU 2
5, since the determination process of step c3 is determined to be true and the process returns, the input process of steps c4 to c10 and the storage process of step c11 are not performed, and the game data stored in the collected data memory 27, the sand The final data of each of the lending machine data, the safe data and the counter data is stored and held as it is.

When the island CPU 18 receives the replies indicating the closing of the store from all the subsidiary computers 1 under its control, the value of the platform index register i exceeds the number of connected platform computers 1, and the determination processing in step b39 is determined to be true. Then, the process proceeds to step b40, and an end reply is transmitted to the bus type LAN 5 together with the address of the host CPU 11 (step b40), and the value of the platform index register i is initialized (step b41).

When the host CPU 11 receives the end reply transmitted from the island CPU 18 designated as the transmission partner from the bus LAN 5 (step a64), it increments the value of the island number storage register SN1 by 1 (step a6).
5) By judging whether the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2 (step a66), the host C
It is determined whether or not the closing processing of all the computers 1 under the umbrella of all the island CPUs 18 directly connected to the bus LAN 5 to the PU 11 has been completed.

In the discrimination processing of step a66, the value of the island number storage register SN1 is changed to the end island number storage register SN2.
If the value set in is not exceeded, it means that the closing process is not completed. In this case, the host CPU
11 returns to step a63, and the island CPU1 of the next island
8 sends a closing command. The host CPU 11 executes the processing loop formed by steps a63 to a66, and thereby the island number storage register S
The value of N1 is updated, the island computer is sequentially specified, and the closing mand is transmitted.

When the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2, the host CPU 11 determines in step a66 that the store closing process has ended and proceeds to step a67. Then, for example, the end of the closing process is displayed on the display unit 15.

Next, the host CPU 11 sets the start island number that was temporarily stored in the island number storage register SN1 for the final data collection from each island computer 2 (step a67), and the end that was temporarily stored. The island number is set in the end island number storage register SN2 (step a68), and a data request command is issued on the bus LAN 5 together with the address of the island CPU18 of the island corresponding to the start island number stored in the island number storage register SN1. (Step a68).

The host CPU 11 allows the bus LAN 5
The process of the island CPU 18 of the island computer 2 designated as the transmission partner in response to the data request command transmitted above is step b42 after the process of step b41 of FIG.
By the processing of step b4, the data request command from the host CPU 11 is received from the bus type LAN 5 (step b4).
2) Select the first one of the plurality of table computers 1 (1) to 1 (4) under its control by the table index register i (step b43), and select the table computer 1 (1).
A data request command is transmitted to the stand CPU 25 (step b44).

When the base CPU 25 receives the data request command from the island CPU 18, it executes the process of step c28 of FIG. 37 as described above and the game data and the sand renting machine data stored and retained in the collected data memory 27 as they are. , Final data of safe data and counter data are transmitted to the island CPU 18 (step c28).

The island CPU 18 receives each final data from the table CPU 25 of the table computer 1 (1) of the transmission partner (step b45), and the collected data memory 20 shown in FIG.
The gaming machine data, the sand renting machine data, the safe data, and the counting machine data are stored in the predetermined storage area set in (step b46).

Then, the island CPU 18 increments and updates the value of the platform index register i (step b47), and compares the updated value of the platform index register i with the number of connected plurality of platform computers 1. By doing so, it is determined whether or not the data collection processing from all the subsidiary computers 1 has been completed (step b4).
8).

If the value of the platform index register i does not exceed the number of connected platform computers 1, data collection processing from the platform computer 1 is in progress, so the island CPU 18
Returns to step b44 and the next computer 1 based on the updated value of the platform index register i.
A data request command is transmitted to the stand CPU 25 of (2). Hereinafter, by the processing loop formed by steps b44 to b48, the value of the table index register i is updated, and the data request command is sequentially transmitted to the table CPU 25 of each computer 1 (i) under its control, and each computer 1 The final data is received from (i) and stored in the collected data memory 20 for each of the gaming machine data, the sand renting machine data, the safe data, and the counting machine data.

When the value of the table index register i exceeds the connected number of the table computers 1, the CPUs of all the table computers 1 (1) to 1 (4) under its control
It is determined that the data collection process from 25 is completed (step b48), the island CPU 18 initializes the value of the platform index register i (step b49), and the collected data memory 2
Game machine data stored in 0, sand rental machine data,
Host C sends each final data of safe data and counter data
It is transmitted to the bus type LAN 5 together with the address of the PU 11 (step b50), and the process returns to step b4.

From this point onward, the processing of steps b6 to b10 is executed, but since the value of the closing processing flag F1 is 1 which has been processed on the side of the base CPU1, the final data is repeated. It will be sent.

The host CPU 11 sends the final data transmitted from the island CPU 18 designated as the transmission partner to the bus type LAN.
When it is received from above 5 (step a69), it is stored in the collected data memory 13 for each of the gaming machine data, the sand renting machine data, the safe data and the counter data (step a7).
0). Next, the host CPU 11 increments the value of the island number storage register SN1 by 1 (step a7).
1) By determining whether or not the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2 (step a72), the host C
It is determined whether or not the final data collection processing of all the island CPUs 18 directly connected to the bus LAN 5 in the PU 11 has been completed.

If it is determined by the determination processing in step a72 that the final data collection processing is not completed, the host CPU 11 returns to step a68 and sends a data request command to the island CPU 18 of the next island. .
The host CPU 11 executes steps a68 to a7.
By executing the processing loop formed by 2, the value of the island number storage register SN1 is updated to sequentially specify the island computer and transmit the final data request command,
The final data is received and stored in the collected data memory 13.

Then, when the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2, the host CPU 11 determines that the final data collection process is completed by the determination process of step a72. The closing process ends.

As described above, at the time when the store closing process is completed, the game machine data, the sand renting machine data, the safe data, and the count that have been updated and stored from the time when the store opening process is performed are stored in each platform computer 1 of each island. The final computer data is stored and held, and each island computer is assigned to each island 2
The final data of each computer 1 under the control of each island computer 2 is game machine data, sand rental data,
The safe data and the counter data are separately stored and held, and the host computer 3 further stores the final data stored and held by each island computer 2 as the gaming machine data, the sand lending data, the safe data and the counter data. Retained.

Therefore, even if the host computer 3 does not function due to a failure or the like, the final data is stored and held in each island computer 2 and each computer 1, so that each island computer is stored. 2 and data can be input from the respective computers 1 and the stored data can be called, and the disadvantage that all the stored data becomes invalid can be avoided.

If the final data is collected when the host computer 3 recovers from the failure, the final data stored from each island computer 2 and each computer 1 can be input and stored. Therefore, the necessary final data can be restored.

Next, the program download process of step a14 will be described. Host computer 3
When the download processing mode is set by the key input of the key input operation unit 17, the determination result of step a6 is determined to be true, and the download processing of the program shown in FIGS. 13 to 16 is started.

The host CPU 11 has a key input operation unit 17
It is determined whether or not there is an operation input for selecting whether to download the island computer 2 from the computer or to download the town computer 1 from the island computer 2.
If there is an input by the selection operation of download, the determination processing of step a80 is determined to be true, the process proceeds to step a81, and the input island number and the end island number are awaited.

Further, if there is an input from the key input operation unit 17 by a selection operation of the town road of the platform computer 1,
If the determination process of step a80 is determined to be false, step a9
The number shifts to 0, and the input stand-by number and end-stage number are awaited.

First, the processing when the download of the island computer 2 is selected will be described. In this case, the start island number and the end island number are input from the key input operation unit 17, and when the start island number and the end island number are input, the host CPU 11 sends the start island number input by the key input. It is stored in the number storage register SN1 (step a81), the end island number is stored in the end island number storage register SN2 (step a82), and the island island CPU18 corresponding to the start island number stored in the island number storage register SN1. The data request command for island computer download is transmitted to the bus type LAN 5 together with the address (step a83).

When the island CPU 18 designated as the transmission partner receives the island computer download data request command from the bus type LAN 5, after the determination of step b1, step b2, step b15 to step b20, the determination processing of step b21 is performed. It is determined that the received communication command is a download data request command,
In step b55 of FIG. 29, it is determined whether or not this download data request command is for an island computer (step b55). In this case, it is determined to be true and the process proceeds to step b56, where the address of the host CPU 11 All the current data stored and held in the collected data memory 20 are transmitted together to the bus type LAN 5 (step b5).
6).

The host CPU 11 receives the data transmitted by the island CPU 18 designated as the transmission partner from the bus LAN 5 (step a84), temporarily stores the data in the work area set in the memory 12, and then stores the data. , A conversion data area in which the conversion data subjected to the consistency processing by performing the data conversion with the consistency of the data storage format and the relative data storage address corresponding to the new program to be downloaded is set on the memory 12 (Step a85).

After the processing of step a84, the host CPU1
1 is the island C stored in the island number storage register SN1
The compatibility-processed conversion data stored in the conversion data area of the memory 12 and the new program together with the address of the PU 18 are transmitted to the bus type LAN 5 (step a86).

The island CPU 18 designated as the transmission partner receives the converted data and the new program which have been subjected to the consistency processing transmitted from the host CPU 11 by the processing of step b57 in FIG. 29 (step b57),
The received conversion data is stored in the collected data memory 20 (step b58), the received new program is stored in a predetermined area of the memory 19 (step b59), and an answer of storage end together with the address of the host CPU 11 is sent to the bus type LAN5. It is transmitted to the above (step b60).

The host CPU 11 executes step a in FIG.
By the processing 87, the end reply transmitted by the island CPU 18 designated as the transmission partner is received from the bus LAN 5 (step a87), and then the value of the island number storage register SN1 is incremented by 1 (step a88) to obtain the island number. The value of the storage register SN1 is the end island number storage register SN2.
It is determined whether or not the download processing of all the island CPUs 18 directly connected to the bus LAN 5 by the host CPU 11 has been completed by determining whether or not the value set in the above is exceeded (step a89). .

If it is determined by the determination processing in step a89 that the value of the island number storage register SN1 does not exceed the value set in the end island number storage register SN2, that is, if the download processing is not completed. If it is determined, the host CPU 11 executes step a83.
Returning to, an island computer download data request command is transmitted to the island CPU 18 of the next island.

The host CPU 11 updates the value of the island number storage register SN1 by executing the processing loop formed by steps a83 to a89 to sequentially specify the island computers and send the island computer download data request command. Then, the data is received from the island computer 2 designated as the transmission partner, the converted data is created in conformity with the new program, the new program is downloaded to the island computer 2 designated as the transmission partner, and the converted data is transmitted. I will send it.

When the value of the island number storage register SN1 exceeds the value set in the end island number storage register SN2, the host CPU 11 completes the program download process for the island computer 2 by the determination process of step a89. And returns.

Next, the processing when the download of the base computer 1 is selected will be described. In this case, the start console number and the end console number are input from the key input operation unit 17, and when the start console number and the end console number are input, the host CPU 11
As shown in FIG. 5, the key input start platform number is stored in the platform number storage register DN1 (step a90), the end platform number is stored in the end platform number storage register DN2 (step a91), and the platform number storage register DN1 is stored. Computer 1 corresponding to the start platform number stored in
Bus computer LA with a data request command for computer download along with the address for the CPU of the CPU 25
It is transmitted to N5 (step a92).

As described above, the island CPU 18 of the island computer 2 having the base computer 1 designated as the transmission partner under its control sends a communication command to the base computer 1 under the control of its own island by the head portion of the base CPU address. If it is determined that there is a computer computer download data request command from the bus type LAN 5, step b1, step b2, step b15 to step b
After the determination of 20, it is determined that the communication command received by the determination processing of step b21 is the download data request command, the process proceeds to step b55 of FIG. 29, and whether this download data request command is for the island computer or not. It is determined whether or not (step b55). In this case, it is determined to be false, and the process proceeds to step b61 in FIG.

The island CPU 18 transmits a download data request command to the base CPU 25 of the base computer 1 corresponding to the received base CPU address of the base computer (step b61).

After the determination of step c1, step c2, step c16 to step c19, the table CPU 25 of the table computer 1 designated as the transmission partner proceeds to step c20.
It is determined that the received communication command is the download data request command by the determination processing in step S31, the process proceeds to step c31 in FIG. 39, and all the current data stored and held in the collected data memory 27 is transmitted to the island CPU 18 ( Step c31).

The island CPU 18 receives all the data transmitted by the platform CPU 25 (step b62), and the host CPU 1
All the data of the base computer 1 received together with the address of 1 are transmitted to the bus type LAN 5 (step b6).
3).

The host CPU 11 executes step a in FIG.
By the process of 93, all the data transmitted from the base computer 1 designated as the transmission partner is received from the bus LAN 5 (step a93), and the data is temporarily stored in the work area set in the memory 12, Then, the converted data that has been subjected to the consistency processing by performing the data conversion for ensuring the consistency of the storage format of the data, the relative storage address of the data, and the like corresponding to the new program to be downloaded is set in the memory 12. It is temporarily stored in the area (step a94).

After the processing of step a94, the host CPU1
1 is the consistency-processed conversion data stored in the conversion data area on the memory 12 together with the address for the machine CPU of the machine computer 1 corresponding to the machine number stored in the machine number storage register DN1 and new. And the program are transmitted to the bus type LAN 5 (step a95).

The island CPU 18 of the island computer 2 having the base computer 1 designated as the transmission partner under its control is shown in FIG.
The conversion data and the new program, which have been subjected to the consistency processing, transmitted by the host CPU 11 by the processing of step b64 in step b64 are received from the bus type LAN 5 (step b64), and the host computer 1 corresponding to the received address for the table CPU The received conversion data subjected to the consistency processing and the new program are transmitted to the stand CPU 25 (step b65).

The platform CPU 25 of the platform computer 1 designated as the transmission partner receives the converted data and the new program which have undergone the consistency processing from the island CPU 18 (step c3).
2) The received converted data is stored in the collected data memory 27 (step c33), the received new program is stored in a predetermined area of the memory 26 (step c34), and a storage end response is transmitted to the island CPU 18 (step). c3
5).

The island CPU 18 receives the end reply from the base CPU 25 (step b66), and sends the end reply together with the address of the host CPU 11 to the bus type LAN 5 (step b67).

When the host CPU 11 receives from the bus type LAN 5 the end reply of the base computer 1 designated as the transmission partner (step a96), it is stored in the base number storage register DN1 to designate the next base computer 1. Increment the value of the existing machine number by 1 (step a9
7) By determining whether or not the value of the machine number storage register DN1 exceeds the value set in the end machine number storage register DN2 (step a98), the download processing of all the machine computers 1 is completed. Or not.

If the value of the machine number storage register DN1 does not exceed the value set in the end machine number storage register DN2 by the judgment processing of step a98, it is judged that the download processing of the machine computer 1 is not completed. In this case, the host CPU 11 executes step a
Returning to 92, the base CPU address of the next base computer 1 (i) corresponding to the base number stored in the base number storage register DN1 on the bus type LAN 5 and the base computer download data request command are transmitted.

The host CPU 11 updates the value of the machine number storage register DN1 by executing the processing loop formed by steps a92 to a98 and sequentially specifies the machine computers and transmits the machine computer download data request command. Then, the data transmitted from the computer of the transmission partner is received from the bus-type LAN 5 and corresponding to the new program, the converted data is created with consistency, and the new program is downloaded to the computer 2 of the transmission partner. At the same time, the converted data is transmitted.

When the value of the machine number storage register DN1 exceeds the value set in the end machine number storage register DN2, the host CPU 11 completes the download processing of the program relating to the machine computer 1 by the determination processing of step a98. And returns.

As described above, when changing the operation programs for collecting data stored in the island computer 2 and the base computer 1 to new operation programs, the host computer 3 operates the island computer 2 And the base computer 1 can be downloaded and changed into a new operation program, and the collected data stored in each of the island computer 2 and the base computer 1 can be updated before the new program is downloaded. The island computer 2 and the base computer 1 are again made compatible with the program.
Since the collected data is stored in each of the above, the stored collection data is not lost due to the change of the program, and can be successively inherited corresponding to the new program.

[0165]

According to the distributed processing type hall computer device of the present invention, since the host computer and the island computer are connected via the bus type LAN, the island computer is newly added to the bus type LA.
It is possible to add and connect to N without restriction, and to connect other devices other than the island computer to the bus type LA.
It is also possible to connect to the host computer via N.

[0166] Bus computer communication between an island computer arranged for each island and a base computer installed for each gaming machine and individually collecting data for gaming machines, sand lending machines, safes, and counters It is connected with a twisted pair wire for performing, and since the island computer collects the data collected by each computer in the island, it is not necessary for the host computer to directly collect the data collected by each computer in each island. Therefore, the host computer can be miniaturized.

When a device is newly connected to the host computer via the bus LAN, the address required for each device connected to the host computer via the bus LAN on the host computer side is set. The address setting means including a storage device for setting is activated, and the address setting means on the device side operates the address setting request switch to store the self-address in the address storage area. As a result, the address required for communication on the bus LAN can be set. Therefore, it is necessary to prepare a different address value for each device to which a dedicated circuit for setting the address is connected. There is no need to operate the address setting request switch. That.

A game machine is installed in each game machine,
A stand computer that individually collects the data of the sand lending machine, the safe, and the counting machine includes a first data storage area that stores and holds the data input from the gaming machine, the sand lending machine, the safe, and the counting machine for a certain period of time. The host computer, which is installed in each island and collects the data collected by each computer in the island, has a second data storage area that stores and holds the data collected from each computer for a certain period. Even if is not functioning due to a failure, etc., the final data is stored and held in each island computer and each computer, so the data input and stored data from each island computer and each computer Can be called and all the data stored in the host computer becomes invalid. It can be.

If the host computer is made to collect the final data when the host computer recovers from the failure, the final data stored from each island computer and each computer can be input and stored. , It is possible to recover the required final data.

When changing the operation programs stored in the island computer and the base computer for data collection and the like into new operation programs, download them from the host computer to the island computer and the base computer, respectively. It can be changed to a new operation program, and the collected data stored in each of the island computer and the base computer can be made compatible with the new program before the island program and the collected data stored in the island computer again. Since it is stored in each of the computer and the base computer, the collected data stored in the island computer and the base computer will not be lost due to the change of the program, and these collected data will be continuously corresponded to the new program. Inheriting It can be.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a distributed processing type hall computer device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an essential part of a host computer in the distributed processing type hall computer device of the embodiment.

FIG. 3 is a block diagram of a main part of an island computer in a distributed processing type hall computer device according to an embodiment.

FIG. 4 is a block diagram of a main part of a base computer in the distributed processing type hall computer device of the embodiment.

5 is a block diagram showing a part of the distributed processing type hall computer device of FIG. 1;

FIG. 6 is a flowchart schematically showing main routine processing of a host CPU arranged in a host computer in the embodiment.

FIG. 7 is a flowchart schematically showing a part of the address setting process of the host CPU in the embodiment.

FIG. 8 is a continuation of the flowchart of FIG.

FIG. 9 is a flowchart schematically showing a store opening process of the host CPU in the embodiment.

FIG. 10 is a flow chart schematically showing the processing during business hours of the host CPU in the embodiment.

FIG. 11 is a flowchart schematically showing a part of the closing process of the host CPU in the embodiment.

FIG. 12 is a continuation of the flowchart of FIG. 11.

FIG. 13 is a flowchart schematically showing a part of the program download processing of the host CPU in the embodiment.

FIG. 14 is a continuation of the flowchart of FIG.

FIG. 15 is a continuation of the flowchart of FIG.

FIG. 16 is a continuation of the flowchart of FIG.

FIG. 17 is a flowchart schematically showing main routine processing of an island CPU arranged in the island computer in the embodiment.

FIG. 18 is a flowchart schematically showing address storage processing of the island CPU in the embodiment.

FIG. 19 is a flowchart showing a part of the processing of the island CPU in the embodiment.

FIG. 20 is a continuation of the flowchart of FIG.

FIG. 21 is a flowchart showing a part of the processing of the island CPU in the embodiment.

FIG. 22 is a continuation of the flowchart of FIG.

FIG. 23 is a continuation of the flowchart of FIG.

FIG. 24 is a continuation of the flowchart of FIG.

FIG. 25 is a continuation of the flowchart of FIG. 20.

FIG. 26 is a continuation of the flowchart of FIG. 25.

FIG. 27 is a continuation of the flowchart of FIG. 20.

FIG. 28 is a continuation of the flowchart of FIG. 20.

FIG. 29 is a continuation of the flowchart of FIG. 20.

FIG. 30 is a continuation of the flowchart of FIG. 29.

FIG. 31 is a flowchart schematically showing a part of main routine processing of a base CPU arranged in the base computer in the embodiment.

FIG. 32 is a continuation of the flowchart of FIG. 31.

FIG. 33 is a flowchart schematically showing the address storage processing of the base CPU in the embodiment.

FIG. 34 is a flowchart showing a part of the processing of the base CPU in the embodiment.

FIG. 35 is a continuation of the flowchart of FIG. 34.

FIG. 36 is a continuation of the flowchart of FIG. 34.

FIG. 37 is a continuation of the flowchart of FIG. 34.

38 is a continuation of the flowchart of FIG. 34.

FIG. 39 is a continuation of the flowchart of FIG. 34.

[Explanation of symbols]

 1 computer 2 Island computer 3 Host computer 4 Twisted pair wire 5 Bus type LAN 6 Transceiver 7 Transceiver cable 8 Terminator 9 Prize POS 10 Other device 11 Host CPU 12 Memory 13 Collected data memory 14 Communication interface 15 Display section 16 Printing section 17 Key input operation unit 18 Island CPU 19 Memory 20 Collected data memory 21 Communication interface 22 Communication interface 23 Communication interface 24 Input / output unit 25 CPU 26 Memory 27 Collected data memory 28 Communication interface 29 Input / output unit 30 Gaming machine 31 Sand rental machine 32 Safe 33 Counter SW1 address setting request switch SW2 address setting request switch

Claims (4)

[Claims] 1. A stand computer installed in each gaming machine and individually collecting data of a gaming machine, a sand lending machine, a safe, and a counter, and a computer installed in each island and each computer in the island And an island computer for collecting the data collected by the computer, a display unit for displaying the data, a printing unit for printing, and a key input operation unit for inputting contents to instruct the island computer and the platform computer. A host computer that collects data collected by the island computer, and the island computer and each computer are connected by a twisted pair line for performing bus-type communication, and the host computer and each island computer A distributed processing type hall computer device, characterized in that it is connected to a bus type LAN by a bus type LAN. 2. Each computer includes a first data storage area for storing and holding data input from a gaming machine, a sand lending machine, a safe, and a counter for a certain period, and each island computer has each computer. 2. The distributed processing type hall computer device according to claim 1, further comprising a second data storage area for storing and holding the data collected from the storage device for a certain period. 3. The memory for setting an address required for each device connected to the host computer via the bus type LAN, in order for the host computer to communicate on the bus type LAN. Each device is provided with an address setting means, and each device is provided with an address setting request switch for requesting the host computer to set its own address, and is sent to itself after the operation of the address setting request switch. 3. The distributed processing type hall computer device according to claim 1, further comprising address storage means for storing the self address and an address storage area for storing the self address. 4. The host computer includes a download unit including a storage device that replaces a data collection program for collecting data stored in the island computer or the platform computer with a new data collection program, and the new data. Data conversion storage means for matching the storage formats and storage addresses of all the data stored in the first data storage area of the island computer and the second data storage area of the platform computer in correspondence with the collection program. 4. The distributed processing type hall computer device according to claim 1, 2 or 3, further comprising: