JPH086546A - Display control method for on-screen display and control device therefor - Google Patents

Abstract

PURPOSE:To provide the display control and its display control device of an on-screen display capable of performing a stable character display having no jitter. etc., as to the technology for generating the clock for an on-screen display in the display control method and the display control device of the on-screen display. CONSTITUTION:In this control of the on-screen display, a pulse signal corresponding to a horizontal synchrinizing signal generated by an on-screen display device is generated by a voltage controlled oscillator (a VCO) 31, etc., during a period a video is displayed on screens such as CRT and so forth and the oscillated pulses are counted and the count value is compared with a reference value and when both value are made to coincide by increasing or decreasing the input control voltage of the VCO 31 so that the count value coincides with the reference value, an oscillation pulse at this time is made to be the clock pulse for the on-screen display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control method and a display control device for an on-screen display, and more particularly to a technique for generating a clock signal for the on-screen display.

[0002]

CR used in personal computers and the like
Recently, so-called on-screen display (hereinafter referred to as "OSD") functions have been installed in T monitors and TV receivers. This function is a function of displaying, for example, characters, symbols, figures, etc. for displaying the channel number, volume, etc. on the screen in a superimposed manner with the image.

The character display is generally performed by using a display-dedicated clock generated separately from the system clock of the microcomputer as the OSD dot clock. Conventionally used in the TV field,
There is a type in which a character is displayed on a CRT screen by synchronizing an oscillation pulse generated by an LC oscillator or an RC oscillator with a horizontal synchronizing signal pulse. In this case, since the LC oscillator and the RC oscillator are configured by external parts of the IC, there is a disadvantage that adjustment is required. Further, since a horizontal synchronizing signal of a predetermined frequency is used in TV images, OSD display will not be hindered even if the clock frequency generated based on the oscillation pulse of the oscillator is fixed, but in the field of CRT monitors such as the multi-scan system. , It could not be used because it requires a variable frequency character display. That is, in the monitor display of a personal computer, the frequency of the horizontal synchronizing signal is set according to a software program for instructing the display content, and it is necessary to create a display clock corresponding to such set frequency. In view of this, in the field of CRT monitors, conventionally, a PLL clock synthesizer configuration as shown in FIG. 4 has used a variable frequency display clock system capable of changing in accordance with the frequency of the horizontal synchronizing signal. That is, a PLL circuit configuration including a phase detector 301, a voltage controlled oscillator (VCO) 302, and a 1 / N divider 303 is used to detect the phase of a horizontal synchronizing signal, multiply its clock by 1 / N, and multiply the clock by OSD. The dot clock is used to enable generation of the display clock according to the frequency change of the horizontal synchronizing signal.

[0004]

However, the above-mentioned P
In the LL synthesizer system, there is a problem that a jitter appears in the character display because the phase shift of the OSD dot clock is likely to occur due to variations in phase detection performance of the phase detector 31 that phase-detects the horizontal synchronization signal, noise, and the like. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display control of an on-screen display and a display control device therefor, which solves the above-described problems in generating a conventional display clock and can perform stable character display without jitter or the like. To do.

[0006]

In order to achieve the above object, a method of controlling display of an on-screen display according to the invention of claim 1 is generated in an on-screen display device during a video display period on a screen. The number of pulses corresponding to the horizontal synchronizing signal is counted, the count value is compared with a predetermined reference value, the pulse frequency of the horizontal synchronizing signal is converted so that the number of pulses matches the reference value, and the conversion is performed. A pulse is used as the clock for the on-screen display.

According to a second aspect of the present invention, there is provided a display control device, wherein a voltage control oscillator for inputting the horizontal synchronizing signal and outputting an oscillation pulse corresponding thereto, and a voltage control oscillator for the voltage control oscillator during the video display period. A counter that counts oscillation pulses, compares the count value of the counter and the predetermined reference value, and according to the difference, the input control voltage of the voltage controlled oscillator so that the count value matches the reference value. And an input voltage control unit for increasing or decreasing the voltage, and when the count value matches the reference value, the oscillation pulse of the voltage controlled oscillator at that time is used as the on-screen display clock.

[0008]

In the display control method according to the first aspect of the present invention, the number of pulses corresponding to the horizontal synchronizing signal is counted during the image display period on the screen, and the count value is made equal to the reference value. Convert to the desired on-screen display clock frequency.

In the display controller according to the second aspect of the present invention, the horizontal synchronizing signal is introduced through the voltage controlled oscillator, the oscillation pulses of the voltage controlled oscillator are counted, and the difference is compared with the reference value. Accordingly, the input control voltage of the voltage controlled oscillator is controlled to convert the oscillation frequency of the voltage controlled oscillator into the frequency of the on-screen display clock so that the count value matches the reference value.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an on-screen display device for implementing a display control method according to the present invention.

The signal processing section 1 includes a video signal, an OSD signal,
The processing circuits 11, 12, 13, and 14 process the vertical synchronizing signal and the horizontal synchronizing signal, respectively. The display unit 2 uses the video signal, the OSD signal, the vertical synchronizing signal, and the horizontal synchronizing signal from the signal processing unit 1 and the clock generated by the display clock generating unit 3 to display a normal image or an OSD on a CRT (not shown) screen. I do. Signal control between the signal processing unit 1 and the display unit 2 is performed according to an instruction from the main controller 4 including a microcomputer.

The display clock generator 3 introduces a horizontal synchronizing signal and converts it into an oscillation pulse signal, a voltage control oscillator (VCO) 31, an oscillation pulse counter 32 for counting the oscillation pulses, and an oscillation pulse counter 32 for counting. And a comparator 33 for comparing the value with a reference count value preset in the reference count value setting unit 34. The reference count value setter 34 sets a reference count value corresponding to a predetermined OSD dot clock frequency. The comparison result of the comparator 33 is input to the up / down counter 36 through the filter 35 and counted up or down. When the count value of the oscillation pulse counter 32 and the reference count value match, the comparator 33 turns off the operation.
The signal CS is given to the up / down counter 36, and the count value of the up / down counter 36 at that time is D / A.
The converter 37 converts the analog value and the converted value is V
It is input to the control input terminal of CO31. The VCO 31 outputs an oscillation pulse signal having a frequency corresponding to the analog conversion value input to the control input terminal. A filter 35 that outputs a count instruction signal to the up / down counter 36 when the comparison result of the comparator 33 is the same for a predetermined number of times so that an unnecessary counter operation does not occur with respect to a temporarily irregular horizontal synchronization signal due to noise or the like. Is provided. Comparator 3
The functions of the reference count value setting unit 34 and the filter 35 may be performed by software under the control of a microcomputer.

The circuit configuration of the VCO 31 is shown in FIG. This is a VCO using a so-called ring oscillator. The inverters 51 to 54 and the NAND gate 55 are connected in an odd number (5) stage ring shape, and the NAND gate 5
A horizontal synchronizing signal is introduced to 5, and the gate output becomes an OSD dot clock through the inverting output amplifier 56 and is fed back to the first stage inverter 51. Each inverter is composed of C-MOS. The control input is given to the gate electrode of the transistor Q1 through the D / A converter 37, and the transistor Q1 is connected in series to the transistor Q2. The power supply transistors Q3 to Q6 are mirror-connected to the transistor Q1 and are connected to the power supply lines of the inverters 51 to 54, respectively.

VC comprising such a ring oscillator
In O31, the oscillation frequency is 1/2 NCR (C: capacitance of one inverter, R: resistance of one inverter,
N: a total of 5 inverters 51 to 54 and NAND gates
In this case, when a control voltage is applied from the D / A converter 37 to the gate electrode of the transistor Q1,
By changing the ON resistance of the transistor according to the applied voltage, the current flowing through each of the transistors Q3 to Q6 via the transistor Q2 is determined. As a result, the rising time (falling time) of each output of the inverters 51 to 54 becomes variable by the current flowing in each of the transistors Q3 to Q6, in other words, the oscillation cycle of the ring oscillator becomes variable according to the input control voltage.

The operation of generating the OSD dot clock in the above configuration will be described. FIG. 2 shows the synchronization relationship between the video signal and the horizontal synchronization signal. As shown in FIGS. 2A and 2B, the horizontal synchronizing signal is output from the horizontal synchronizing signal processing circuit 14 as a pulse signal having a predetermined frequency during the video display period. This video display period is a period that contributes to the image display of the video display signal, and the output of the horizontal synchronization signal is constant during the period when it does not contribute to the image display, that is, the horizontal blanking period. Switches to a pulse signal. The VCO 31 does not oscillate during the horizontal blanking period, but oscillates during the video display period. The frequency of the horizontal synchronizing signal is, for example, 20 kHz to 80
It is assumed that the bandwidth is used up to kHz, and that the OSD dot clock uses 640 pulses / line, for example, and the corresponding count value is set in the reference count value setter 34.

During the image display period, the count value of the oscillation pulse counter 32 and the reference count value are compared. If there is a difference between the two, the up / down counter 36 counts according to the increase / decrease of the comparison result of the comparator 33. To do. D / A according to the count value of the up / down counter 36
The analog conversion value of the converter 37 is given as the input control voltage of the VCO 31 (see FIG. 3). In this way, the VCO
The frequency of the transmission pulse of 31 is the reference count value setter 34
When the frequency differs from the frequency determined by the set count value of, the count value of the up / down counter 36 increases / decreases, and the control input voltage of the VCO 31 increases / decreases accordingly, so that the frequency of the oscillation pulse of the VCO 31 is changed to a predetermined set frequency. To be done. The output of the VCO 31 is supplied to the display unit 2 as an OSD dot clock, and the main controller 4
The OSD signal output from the OSD signal processing circuit 12 is displayed on the CRT screen during the video display period in accordance with the OSD display instruction from.

As described above, the O of the predetermined frequency is set in accordance with the frequency of the horizontal synchronizing signal arbitrarily designated by the above frequency width.
The SD dot clock can always be stably generated. The OSD clock generation technique of the present invention is not only effective in the field of CRT monitors, such as personal computers, which require variable frequency, but may be applied to the field of TV.

Further, the VCO in the present application is not limited to the ring oscillator configuration of FIG. 3 described above, and may be any one that can change the frequency according to the input control voltage.

[0020]

According to the present invention, the number of pulse signals corresponding to the horizontal synchronizing signal is counted, and the synchronizing signal is frequency-converted so as to coincide with the OSD dot clock of a desired frequency. It is possible to stably generate an OSD dot clock that does not cause jitter and the like according to the frequency change of the horizontal synchronization signal without performing the phase detection of the horizontal synchronization signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an on-screen display display device according to an embodiment of the present invention.

FIG. 2 is a schematic waveform diagram showing a synchronization relationship between a video signal and a horizontal synchronization signal of the above embodiment.

FIG. 3 is a circuit diagram showing a VCO 31 of the above embodiment.

FIG. 4 is a block diagram showing a conventional character display clock generation configuration unit.

[Explanation of symbols]

 1 Control Section 2 Display Section 3 OSD Clock Generation Section 31 VCO (Voltage Controlled Oscillator) 32 Oscillation Pulse Counter 33 Comparator 34 Reference Count Value Setter

Claims (2)

[Claims] 1. A method of generating a clock for an on-screen display in an on-screen display device for displaying character information on a screen in an overlapping manner with a video, wherein a horizontal signal generated by the on-screen display device during a video display period on the screen. The number of pulses corresponding to the synchronization signal is counted, the count value is compared with a predetermined reference value, the pulse frequency of the horizontal synchronization signal is converted so that the number of pulses matches the reference value, and the converted pulse Is used as the clock for the on-screen display. 2. The display control device in the display control method according to claim 1, wherein the voltage control oscillator receives the horizontal synchronization signal and outputs an oscillation pulse corresponding to the horizontal synchronization signal, and the voltage control is performed during the video display period. A counter that counts oscillation pulses of an oscillator, compares the count value of the counter with the predetermined reference value, and inputs the voltage-controlled oscillator so that the count value matches the reference value in accordance with the difference. And an input voltage control means for increasing or decreasing a control voltage, and when the count value matches the reference value, the oscillation pulse of the voltage controlled oscillator at that time is the clock for the on-screen display, of the on-screen display Display controller.