JPH0863971A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a reliable operation of memory function using an internal control signal with a minute error by supplying a control signal generated by using the control signal generation circuit to peripheral circuits of the semiconductor device provided with a memory cell array through a signal line equivalent to a word ling in capacity. CONSTITUTION: The internal control signals generated by the use of the circuit signal generation circuit 2 are fed to the input/output circuit 1, a column decoder 4, a sense amplifier 6, a row decoder 3, a precharge circuit 7 and an equalizer circuit 8 which compose the peripheral circuits of the memory cell array 5 through the word line capacity equivalent signal line 9. Through this system, the internal control signal with a minimum error taking account of the actual word line operation is easily generated to enable a reliable operation of memory function, providing a fast, energy-saving semiconductor memory device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory cell array.

[0002]

2. Description of the Related Art Conventionally, when controlling a memory cell array of a semiconductor device, a control signal generating circuit generates a control signal based on address information input from an input / output circuit, and the generated control signal is applied to the memory cell array. By supplying the data to the peripheral circuit of, the writing or reading operation to the memory cell array is performed. The peripheral circuits include, for example, an input / output circuit, a row decoder, a column decoder, a sense amplifier, a precharge circuit, an equalize circuit and the like.

A conventional semiconductor device will be described below with reference to the drawings. FIG. 5 is a block diagram of a conventional semiconductor device, in which 1 is an input / output circuit, 2 is a control signal generation circuit for generating a control signal based on information input from the input / output circuit 1, and 3 is a control signal generation circuit. 2 is a row decoder that selects a row address from a selection signal generated from 2; 4 is a column decoder that selects a column address from a selection signal generated from the control signal generation circuit 2; and 5 is selected by the row decoder 3 and the column decoder 4. A memory cell array for storing the data, 6 is a sense amplifier for amplifying the memory information selected by the row decoder 3 and the column decoder 6 from the memory cell array 5 by the sense amplifier drive signal generated by the control signal generating circuit 2, and 7 is a control circuit. A precharge circuit drive signal generated from the signal generation circuit 2 is used to precharge the memory cell array 5. Charge circuit, 8 is a equalizing circuit for performing the equalization of the memory cell array 5 by equalization circuit drive signal generated from the control signal generation circuit 2.

The operation of the semiconductor device configured as described above will be described below. First, the address a input by the input / output circuit 1 and the read signal r from the memory
Are selected by the control signal generation circuit 2. At this time, the control signal generation circuit 2 sends a row decoder selection signal to the row decoder 3. At the same time, the control signal generation circuit 2 sends a column decoder selection signal to the column decoder 4. Then, the memory cell at the address a input by the input / output circuit 1 is selected from the memory cell array 5. The read information from the selected memory cell is amplified by the sense amplifier 6 by the sense amplifier drive signal generated from the control signal generation circuit 2. The amplified information is output from the input / output circuit 1 by the output drive signal generated from the control signal generation circuit 2.

When the read signal r is not input from the input / output circuit 1, the precharge drive signal generated by the control signal generation circuit 2 drives the precharge circuit 7,
The memory cell array 5 is precharged. At the same time, the equalizing circuit 8 is driven by the equalizing drive signal generated from the control signal generating circuit 2 to equalize the memory cell array 5.

[0006]

When designing the semiconductor device having the above-mentioned structure, in addition to connection information between the control signal generating circuit and each peripheral circuit, delay information of each wiring or element, for example, in the memory cell array. It must be designed in consideration of the capacitance value of the word line. However, there is some error between the actual capacitance value of the word line and the capacitance value that can be grasped only by simulation at the design stage. This error is not a problem when the capacity of the entire memory cell array is small, but the simulation error becomes large when the capacity of the entire memory cell is large.

Therefore, there is a problem that the timings of signals for controlling the peripheral circuits are deviated, and for example, the sense amplifier is driven before the word line is selected to cause a malfunction, and this malfunction is taken into consideration. If a design is made with an extra margin, the read operation becomes too slow. In addition, such a timing shift may cause a problem that information is output from the input / output circuit before the word line of the selected memory is opened, and the pre-charge occurs even when the word line of the read memory is opened. In addition, there is a problem that a write error occurs in the memory due to the equalization. Further, there is a problem that extra power consumption is required because the row address and the column address are selected even when the word line is not required to be selected.

The present invention solves the above-mentioned conventional problems, and reduces the deviation of the timing between the signal for controlling each peripheral circuit and the word line operation, and makes it possible to develop a high speed and low power consumption semiconductor. The purpose is to provide a device.

[0009]

To achieve this object, a semiconductor device according to a first aspect of the present invention includes a memory cell array, a peripheral circuit that operates to write or read information to and from the memory cell array, and a peripheral circuit. A control signal generation circuit for generating a control signal and a word line equivalent capacitance signal line having a capacitance equivalent to that of a word line in the memory cell array are provided. It is to be supplied to the peripheral circuit through.

According to the second aspect of the invention,
The peripheral circuit described includes a sense amplifier circuit driven by a sense amplifier drive signal from the control signal generation circuit.

According to a third aspect of the invention, the peripheral circuit includes a precharge circuit driven by the precharge drive signal from the control signal generation circuit.

Further, the structure according to claim 4 is characterized in that the peripheral circuit includes an equalizing circuit driven by the equalizing drive signal from the control signal generating circuit.

According to a fifth aspect of the present invention, the peripheral circuit includes a row decoder that performs a selection operation with a row decoder selection signal from the control signal generation circuit.

According to a sixth aspect of the present invention, the peripheral circuit includes a column decoder which performs a selection operation by a column decoder selection signal from the control signal generation circuit.

According to a seventh aspect of the present invention, the peripheral circuit includes an input / output circuit that performs a selection operation by the input / output circuit selection signal from the control signal generation circuit.

According to another aspect of the semiconductor device of the present invention, a memory cell array, a sense amplifier that operates to read information from the memory cell array, a control signal generation circuit that generates a signal for controlling the sense amplifier, and a memory cell array internal. A word line equivalent capacitance signal line having a capacitance equivalent to that of the word line, and the control signal generating circuit supplies the generated control signal to the sense amplifier via the word line equivalent capacitance signal line, The line equivalent capacitance signal line is arranged at a position opposite to the control signal generating circuit with the memory cell array interposed therebetween.

[0017]

Since the control signal drives each peripheral circuit after performing the same operation as the actual word line operation, for example,
Since the malfunction of the sense amplifier can be prevented in advance, and since the sense amplifier can be configured without including the simulation error margin at the time of designing, the high speed operation can be performed accordingly. Further, since the precharge and the equalization can be surely performed when the word line is not open, it is possible to prevent a writing error in the memory and reduce the power consumption. Further, since the memory cell can be selected by the row decoder and the column decoder only during the period when the word line needs to be opened, the power consumed by the bit line can be reduced. In addition, since the input / output circuit is selected after the word line is opened, it is possible to prevent the output of information before the word line is opened by mistake, and it is possible to reduce the power consumption.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 9 is a word line equivalent capacitance signal line having substantially the same capacitance as a word line in the memory cell array, 2 is a signal from the word line equivalent capacitance signal line and an input signal from the input / output circuit 1 are selectively combined. , The input / output circuit 1, the row decoder 3, the column decoder 4, the sense amplifier 6, the precharge circuit 7, the equalize circuit 8, and the word line equivalent capacitance signal line 9 for generating a control signal.

Reference numeral 1 is an input / output circuit, 3 is a row decoder, 4 is a column decoder, 5 is a memory cell array, 6 is a sense amplifier, 7 is a precharge circuit, and 8 is an equalize circuit. Are the same.

The operation of the semiconductor device configured as described above will be described below. First, the read signal r from the memory input by the input / output circuit 1 of FIG. 1 is selected by the control signal generation circuit 2. At this time, the control signal generation circuit 2 outputs a signal to the word line equivalent capacitance signal line 9. The word line equivalent capacitance signal line 9 receives this signal, performs the same operation as the word line operation when the memory cell is actually selected, and sends the signal to the control signal generation circuit 2 again. The signal sent from the word line equivalent capacitance signal line 9 and the control signal generation circuit 2 by the input / output circuit 1
By the combination of the address a and the read signal r input to the control signal generating circuit 2, the control signal generating circuit 2 can generate a read signal toward each peripheral circuit at the timing of the actual word line operation. Specifically, the control signal generation circuit 2 sends the row decoder selection signal to the row decoder 3, and also sends the column decoder selection signal to the column decoder 4.
Send to Then, the memory cell of the address input by the input / output circuit 1 is selected from the memory cell array 5. The read information from the selected memory cell is amplified by the sense amplifier 6 by the sense amplifier drive signal generated by the control signal generation circuit 2, and output from the input / output circuit 1 by the output drive signal generated by the control signal generation circuit 2. .

Even when the read signal r is not input from the input / output circuit 1, the control signal generating circuit 2 outputs a signal to the word line equivalent capacitance signal line 9. The word line equivalent capacitance signal line 9 receives this signal, performs the same operation as the word line operation in which no memory cell is actually selected, and then sends the signal to the control signal generation circuit 2. The control signal generation circuit 2 generates a control signal to each peripheral circuit based on the signal sent from the word line equivalent capacitance signal line 9. Specifically, the precharge circuit 7 is driven by the precharge drive signal generated by the control signal generation circuit 2,
The memory cell array 5 is precharged. At the same time, the equalizing circuit 8 is driven by the equalizing drive signal generated from the control signal generating circuit 2 to equalize the memory cell array 5.

Next, taking the case where the above semiconductor device is an SRAM as an example, a more specific structure of the word line equivalent capacitance signal line will be described with reference to FIGS.

FIG. 2 is a circuit diagram of the decoding section of the row decoder 3, where 10 is a 3-input NAND circuit and 11 is a 2-input N circuit.
It is an OR circuit. Address input a1, a2, a3, a4
Is H level and the control signal c from the control signal generating circuit 2 is H level, the decode output w1 outputs H level. Otherwise, the decode output w1 outputs the L level.

FIG. 3 is a circuit diagram of the memory cell array, in which 13 and 14 are N-type MOS transistors, 15 is an inverter, and 12 is a memory cell. The memory cell array 5 in FIG. 1 is one in which the memory cells 12 are arranged in the number of columns and the number of rows. A memory cell is selected by the word line w2, and the contents of the memory cell can be output by the bit lines b1 and b2.

FIG. 4 shows an embodiment of the word line equivalent capacitance signal line. This is because the address inputs a1, a2, a3, a4 of the decoding section of the row decoder 3 shown in FIG. 2 are fixed by the power supply 17, and the N-type MOS transistors 13 and 14 of the memory cell 12 shown in FIG. The memory cell word line equivalent capacitance 16 in which the same transistor is grounded to the power supply 17 and the ground is connected to the memory cell array 5
It consists of the same number of columns as the above.

With this configuration, when the control signal c from the control signal generating circuit 2 is at H level, the decode output w1 of the word line equivalent capacitance signal line also becomes H level, and word line operation similar to actual delay is performed. Can be reflected on the output w3 of the memory cell word line equivalent capacitance 16 to output the H level. Specifically, when the read signal r is input from the input / output circuit 1 to the control signal generation circuit 2, the control signal c becomes H level, and the H level signal is transmitted from the control signal generation circuit 2 to the word line equivalent capacitance signal line. Is output.

In particular, when the word line equivalent capacitance signal line 9 and the control signal generating circuit 2 are arranged in the most distant state,
Since the capacitance corresponding to the wiring length is further increased, the H level is output from the output w3 of the word line equivalent capacitance signal line 9 reflecting the state in which the actual delay is maximum. With such an arrangement, the delay amount of the control signal can be increased and adjusted. For example, when adjusting the drive timing of the sense amplifier, if the capacitance of the word line equivalent capacitance signal line is not sufficient, such an arrangement ensures that the sense amplifier drive timing is more reliable than the word line selection timing. Can be late. This is suitable when it is desired to ensure the reliability of the sense amplifier operation. As the arrangement position in the farthest state, for example, as shown in FIG. 1, the word line equivalent capacitance signal line 9 may be provided at a position opposite to the control signal generating circuit 2 with the memory cell array 5 interposed therebetween. .

When the read signal r is not input from the input / output circuit 1 to the control signal generation circuit 2, the control signal generation circuit 2 outputs an L level signal as the control signal c. Also at this time, if the word line equivalent capacitance signal line 9 is arranged farthest from the control signal generation circuit 2 and the memory cell array 5, the actual maximum delay state from the output w3 of the word line equivalent capacitance signal line 9 is obtained. It is possible to output an L-level signal by reflecting it. The control signal generation circuit 2 selectively determines the output w3 of the word line equivalent capacitance signal line 9 and the information from the input / output circuit 1, and the control signal generation circuit 2 outputs the drive signal of the precharge circuit and the drive signal of the equalize circuit. Can occur. It is also possible to generate a sense amplifier drive signal, a row decoder selection signal, a column decoder selection signal, and an input / output circuit selection signal as needed, and each peripheral circuit can be driven according to the word line operation. it can.

As described above, according to the present embodiment, by newly providing the word line equivalent capacitance signal line 9, the timing of the word line operation and the control operation of each peripheral circuit can be matched, and malfunction can be prevented. can do.
Further, by arranging the control signal generating circuit 2 and the word line equivalent capacitance signal line 9 in the most distant state, the operation timing can be further adjusted, and the reliability of the sense amplifier operation can be ensured in particular. .

Although the word line equivalent capacitance signal line 9 is arranged farthest from the control signal generation circuit 2 in the above embodiment, the word line equivalent capacitance signal line 9 may be arranged in the control signal generation circuit 2 in some cases. It may be arranged in the closest state and used for generating the memory internal control signal when the word line operation is the fastest.

[0031]

According to the present invention, by providing the word line equivalent capacitance signal line, it is possible to easily generate a memory internal control signal with a small error in consideration of the actual word line operation, and to perform a reliable memory function operation. It will be possible. Therefore, it is possible to develop a high-speed memory with low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a row decoder according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a memory cell array according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a word line equivalent capacitance signal line according to an embodiment of the present invention.

FIG. 5 is a block diagram of a conventional semiconductor device.

[Explanation of symbols]

 1 Input / Output Circuit 2 Control Signal Generation Circuit 3 Row Decoder 4 Column Decoder 5 Memory Cell Array 6 Sense Amplifier 7 Precharge Circuit 8 Equalize Circuit 9 Word Line Equivalent Capacitance Signal Line 10 3 Input NAND Circuit 11 2 Input NOR Circuit 12 Memory Cell 13 N Type MOS transistor 14 N type MOS transistor 15 Inverter 16 Memory cell Word line equivalent capacity 17 Power supply

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8242 7735-4M H01L 27/10 681 A

Claims (8)

[Claims] 1. A memory cell array, a peripheral circuit that operates to write or read information to and from the memory cell array, a control signal generation circuit that generates a signal that controls the peripheral circuit, and a word line inside the memory cell array. A semiconductor device comprising a word line equivalent capacitance signal line having an equivalent capacitance, wherein the control signal generation circuit supplies the generated control signal to the peripheral circuit via the word line equivalent capacitance signal line. 2. The semiconductor device according to claim 1, wherein the peripheral circuit includes a sense amplifier circuit driven by a sense amplifier drive signal from the control signal generation circuit. 3. The semiconductor device according to claim 1, wherein the peripheral circuit includes a precharge circuit driven by a precharge drive signal from the control signal generation circuit. 4. The semiconductor device according to claim 1, wherein the peripheral circuit includes an equalizing circuit driven by an equalizing drive signal from the control signal generating circuit. 5. The semiconductor device according to claim 1, wherein the peripheral circuit includes a row decoder that performs a selection operation with a row decoder selection signal from the control signal generation circuit. 6. The semiconductor device according to claim 1, wherein the peripheral circuit includes a column decoder which performs a selection operation by a column decoder selection signal from the control signal generation circuit. 7. The semiconductor device according to claim 1, wherein the peripheral circuit includes an input / output circuit which performs a selection operation by an input / output circuit selection signal from the control signal generation circuit. 8. A memory cell array, and a sense amplifier which operates to read information from the memory cell array.
A control signal generation circuit for generating a signal for controlling the sense amplifier and a word line equivalent capacitance signal line having a capacitance equivalent to a word line in the memory cell array are provided, and the control signal generation circuit outputs the generated control signal to the control circuit. The configuration is such that the word line equivalent capacitance signal line is supplied to the sense amplifier through the word line equivalent capacitance signal line, and the word line equivalent capacitance signal line is arranged at a position opposite to the control signal generation circuit with the memory cell array interposed therebetween. A semiconductor device characterized by the above.