JPH0863514A - Bit slice layout cell - Google Patents

Abstract

PURPOSE: To easily change driving 'performance only by means of arranging (or eliminating) the same cells by including plural specified terminal pairs in the layout cells of a function block. CONSTITUTION: The terminal STI1B, the terminal STI2B, the terminal STCB, the terminal STOB, the terminal STM1B and the terminal STM2B of the layout cells 1 arranged on the upper-side of a drawing are respectively connected to the corresponding terminals of layout cells 2 arranged on the lower side of the drawing, namely, a terminal STI1T, a terminal STI2T, a terminal STCT, a terminal STOT, a terminal STM1T and a terminal STM2T. Thus, the input signals and the output signals of respective logical gates in the layout cells 1 and 2 are mutually connected. Thus, the corresponding logical gates of the layout cell 1 and the layout cell 2 are connected in parallel, and the driving capacity of the output signals from the respective gates becomes two-fold.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout cell of a functional block composed of a plurality of logic gates in a CMOS integrated circuit, and more particularly, to changing the driving capability of an output signal by arranging the layout cells successively. Layout cells that enable

[0002]

2. Description of the Related Art Conventionally, this type of layout cell is shown in FIG.
The configuration is as shown in FIGS. 6, 7, and 8.

First, a 2-input multiplexer will be described as an example with reference to the drawings.

FIG. 5 is a diagram for explaining a conventional two-input multiplexer, and more specifically, it is a concrete example of a two-input multiplexer circuit in the case where the driving capability of an output signal is relatively small.

Referring to FIG. 5, a conventional two-input multiplexer circuit has an inverter SI1 which generates an inverted logic of a control signal C, and a control signal C and an output signal of the inverter SI1 which receive the input data I1 as input. , A clocked inverter SC1 connected to a control terminal, a control signal C and an output signal of the inverter SI1 are connected to control terminals, and an output of the clocked inverter SC1 and a clock Output terminal ST with the connection point with the output of the drive inverter SC2 as input
The inverter SI2 outputs the output data O to O.

In the 2-input multiplexer circuit of FIG. 5, when the control signal C is at a high level, the clocked inverter SC1 is in the active state, the output of the clocked inverter SC2 is in the high impedance state, and the input data I1. Is output to the output data O, and conversely, when the control signal C is at a low level, the input data I2 is output to the output data O.

In FIG. 5, for the inverter SI1, for example, the gate width (referred to as "PW") of the p-channel MOS transistor (referred to as "pMOS transistor") forming the CMOS inverter is 20 .mu.m and the pM is specified.
The gate length (referred to as "PL") of the OS transistor is 2.
5 μm, the gate width (referred to as “NW”) of an n-channel MOS transistor (referred to as “nMOS transistor”) is 1
0 μm, gate length of the nMOS transistor (“NL”)
Is 2 μm.

The pMOS transistor of the inverter SI2 has a gate width PW of 40 μm and a gate length PL of 2.5 μ.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

In both the clocked inverter SCI and the clocked inverter SC2, the gate width PW of the pMOS transistor is 40 μm and the gate length PL is 2.5 μ.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

The terminal is a terminal STI1 for input data I1.
The input data I2 terminal STI2, the control signal C input terminal STC, and the output data O output terminal STO are each formed of one terminal.

FIG. 6 is a diagram showing a specific example of the two-input multiplexer circuit in the case where the driving capability of the output signal is relatively large.

To increase the driving capability of the output signal, 2
It is necessary to increase the gate width of the transistor gate that forms the input multiplexer circuit.

Referring to FIG. 6, the 2-input multiplexer circuit includes an inverter LI1 which generates an inverted logic of a control signal.
And a clocked inverter LC1 to which the control signal C and the output signal of the inverter LI1 are connected to the control terminal with the input data I1 as the input, and the control signal C and the output signal of the inverter LI1 to the input with the input data I2. Clocked inverter LC2 connected to the terminals, the output of clocked inverter LC1 and clocked inverter L
And an inverter LI2 which receives the common connection point with the output of C2 as an input and outputs the output data O from the output terminal LTO.

In FIG. 6, for the inverter LI1, for example, the gate width PW of the pMOS transistor is 2
0 μm, gate length PL is 2.5 μm, gate width NW of nMOS transistor is 10 μm, gate length NL is 2 μm
m.

The pMOS transistor of the inverter LI2 has a gate width PW of 40 μm and a gate length PL of 2.5 μ.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

In both the clocked inverter LCI and the clocked inverter LC2, the pMOS transistor has a gate width PW of 40 μm and a gate length PL of 2.5 μ.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

The terminal is a terminal STI1 for input data I1.
The input data I2 terminal STI2, the control signal C input terminal, and the output data O output terminal STO are each formed of one terminal.

As described above, in the 2-input multiplexer circuit of FIG. 6, the gate width of each transistor constituting the 2-input multiplexer circuit is doubled as compared with the 2-input multiplexer circuit of FIG. Has been improved.

Next, a three-valued state buffer circuit will be described as an example with reference to the drawings.

FIG. 7 is an explanatory diagram of a conventional example of a three-valued state buffer circuit, and more specifically, it is a specific example of the three-valued state buffer circuit when the driving capability of the output signal is relatively small.

Referring to FIG. 7, the ternary state buffer circuit includes an inverter SI3 for generating an inverted logic of control signal E.
A NOR gate SO1 having the input data I1 and the output signal of the inverter SI3 as inputs; a NAND gate SA1 having the input data I1 and the control signal E as inputs;
An nMOS transistor SN1 having a gate electrode connected to the output end of the R gate SO1 and a source electrode connected to GND (ground), and a gate electrode connected to the output end of the NAND gate SA1 and a source electrode connected to a power supply pMO
The drain electrode of the nMOS transistor SN1 and the drain electrode of the pMOS transistor SP1 are commonly connected, and the connection point is connected to the output terminal STO and the output data O from the output terminal STO.
Is output.

In the ternary state buffer circuit of FIG. 7, when the control signal E is at a high level, the output data O becomes the input data I1.
When the control signal E is low level, the output data O is electrically cut off.

For the inverter SI3, for example, p
The gate width PW of the MOS transistor is 10 μm, the gate length PL is 2.5 μm, the gate width NW of the nMOS transistor is 7.5 μm, and the gate length NL is 2.0 μm.

The pMOS transistor of the NOR gate SO1 has a gate width PW of 40 μm and a gate length PL of 2.5 μm.
m, nMOS transistor gate width NW is 10 μm,
The gate length NL is 2 μm.

The pMOS transistor of the NAND gate SA1 has a gate width PW of 20 μm and a gate length PL of 2.5.
μm, gate width NW of nMOS transistor is 20μ
m, and the gate length NL is 2 μm.

The gate width N of the nMOS transistor SN1
The W is 20 μm and the gate length NL is 2 μm.

The gate width P of the pMOS transistor SP1
The W is 40 μm and the gate length PL is 2.5 μm.

The terminal is an input data I1 terminal STI1.
The control signal E input terminal STE and the output data O output terminal STO are each configured by one terminal.

FIG. 8 is a diagram showing a specific example of the ternary state buffer circuit when the drive capability of the output signal is relatively large.

In order to increase the driving capability of the output signal, 3
It is necessary to increase the gate width of the transistor gate that constitutes the value state buffer circuit.

Referring to FIG. 8, the ternary state buffer circuit includes an inverter LI3 which generates an inverted logic of control signal E.
A NOR gate LO1 that receives the input data I1 and the output signal of the inverter LI3; a NAND gate LA1 that receives the input data I1 and the control signal E;
An nMOS transistor LN1 having a gate electrode connected to the output end of the R gate LO1 and a source electrode connected to GND (ground), and a gate electrode connected to the output end of the NAND gate LA1 and a source electrode connected to a power supply pMO
The drain electrode of the nMOS transistor LN1 and the drain electrode of the pMOS transistor LP1 are commonly connected, the connection point and the output terminal LTO are connected, and the output data O is output from the output terminal LTO.

In FIG. 8, pMO of the inverter LI3
The gate width PW of the S transistor is 20 μm and the gate length P is
L is 2.5 μm, nMOS transistor gate width NW
Is 15 μm and the gate length NL is 2.0 μm.

The gate width PW of the pMOS transistor of the NOR gate LO1 is 80 μm and the gate length PL is 2.5 μm.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

The pMOS transistor of the NAND gate LA1 has a gate width PW of 40 μm and a gate length PL of 2.5.
μm, the gate width NW of the nMOS transistor is 40 μm
m, and the gate length NL is 2 μm.

Gate width N of the nMOS transistor LN1
The W is 40 μm and the gate length NL is 2 μm.

The gate width P of the pMOS transistor LP1
The W is 80 μm and the gate length PL is 2.5 μm.

The terminal is a terminal STI1 for input data I1.
The control signal E input terminal STE and the output data O output terminal STO are each configured by one terminal.

The ternary state buffer circuit of FIG.
Compared with the value state buffer circuit, the gate width of the MOS transistor forming the ternary state buffer circuit is doubled, and the drive capability of the output signal is improved.

[0039]

As can be seen from FIGS. 5 and 6, when it is desired to change the driving capability of the 2-input multiplexer circuit, the pMOS of each gate forming the 2-input multiplexer circuit and the gate width PW of the nMOS transistor,
It is necessary to change the NW according to the driving ability, and a layout cell is required for each driving ability.

Further, referring to FIGS. 7 and 8, when it is desired to change the drive capability of the output signal of the circuit composed of a plurality of logic gates, the pMOS and nMO of each gate forming the circuit are changed.
It is necessary to change the gate widths PW and NW of the S transistor in accordance with the driving ability, and a layout cell is required for each driving ability.

That is, in the layout cell of the functional block composed of a plurality of conventional logic gates described above, in order to change the driving capability of the output signal, the layout cell having the transistor size corresponding to the driving capability is used. It is required for each driving capability, increasing the cell manufacturing process.

Incidentally, for example, in Japanese Patent Laid-Open No. 1-238037,
Just prepare one type of output stage element and its drive circuit,
For the purpose of providing a semiconductor device that does not require a new design according to the application and can be applied to applications with different current capacities, an M (composed of an output stage element and a drive circuit for driving the output stage element). M ≧ 2) unit cells, and a current path between a pair of main terminals of a desired N (2 ≦ N ≦ M) unit cells among M unit cells is connected in parallel according to a load, There has been proposed a semiconductor device provided with a connecting means for commonly connecting the input terminals of these N unit cells.

However, in the semiconductor device disclosed in Japanese Patent Laid-Open No. 1-238037, a plurality of unit cells (M) each including an output stage element and a drive circuit for driving the output stage element are previously arranged (M
The number of these units is N, and N of them are wired in parallel by a wiring means. When the desired number N is smaller than the number M of unit cells, a circuit including an extremely redundant and useless configuration. Becomes On the other hand, the number N of unit cells required for the desired driving capability is equal to the number M of unit cells provided in advance.
If it exceeds, the semiconductor integrated circuit further including the unit cell must be redesigned. In the semiconductor device disclosed in the above publication, the collector / emitter current paths of N transistors are connected in parallel by wiring means, and the input terminals of N unit cells are commonly connected to the output of the signal circuit. That process is required.

Therefore, the present invention solves the above-mentioned problems, and in a bit slice type circuit, when the drive capacity is changed after layout, it is easy to change the drive capacity by arranging (or deleting) the same cells. The purpose is to provide a layout cell that realizes It is another object of the present invention to provide a layout cell that does not require a layout cell corresponding to the driving capability and reduces the layout cell creation process.

[0045]

In order to achieve the above object, the present invention provides a layout cell of a functional block including a plurality of logic gates in a semiconductor integrated circuit, wherein the layout cell of the functional block is connected to an input signal. A pair of terminals arranged on the boundary lines at both ends of the layout cell,
A pair of terminals connected to an output signal and arranged on the boundary lines at both ends of the layout cell, and a pair of terminals connected to a signal between logic gates included in the functional block and arranged on the boundary lines at both ends of the layout cell. There is provided a layout cell including:

According to the present invention, a layout cell of a functional block including a plurality of logic gates in a semiconductor integrated circuit is
A pair of terminals connected to an input signal and arranged on the boundary lines at both ends of the layout cell, a pair of terminals connected to an output signal and arranged on the boundary lines at both ends of the layout cell, and a logic gate included in the functional block. A pair of terminals connected to a signal between the layout cells and arranged on the boundary lines at both ends of the layout cell, respectively, and a boundary line at one end of one layout cell of the functional block and another functional block identical to the functional block. Of the layout cell is brought into contact with the boundary line at the other end of the layout cell, and the terminal at the one end of the one layout cell and the corresponding terminal at the other end of the other layout cell are connected to each other. A layout cell is provided that is configured to increase the drive capability of a block.

Further, in the present invention, in addition to the layout cell of the functional block, there are n layout cells of the same functional block as the functional block (n is a predetermined integer).
Provided individually, the border line of one side edge of one layout cell and the border line of the other side edge of another layout cell are alternately abutted,
The output signal has a driving capability (n + 1) times that of the original functional block.

In the present invention, preferably,
The functional block is a bit slice type circuit.

[0049]

According to the present invention, when it is desired to change the output signal drive capability, the output signal drive capability can be easily changed by simply arranging the layout cells in series vertically. The driving capability of the output signal can be changed according to the number of stacked products.

[0050]

Embodiments of the present invention will be described below with reference to the drawings.

[0051]

Embodiment 1 FIGS. 1 and 2 are views for explaining a layout cell according to a first embodiment of the present invention, and more specifically, FIG.
A specific configuration example when the present invention is applied to an input multiplexer circuit is shown.

In this embodiment, by arranging the layout cells of the 2-input multiplexer circuit continuously in a vertical stack, the drive capability of the output signal can be changed according to the number of vertical stacks of the layout cells.

The two-input multiplexer circuit of FIG. 1 is an example of a case where the driving capacity is comparatively small, and is composed of the same logic gate as the two-input multiplexer circuit when the driving capacity of the conventional example is comparatively small. The connection between them is similarly configured.

Referring to FIG. 1, the 2-input multiplexer circuit includes an inverter SI1 which generates an inverted logic of a control signal.
And input data 1 as input, control signal C and inverter S
A clocked signal whose output signal from I1 is connected to the control terminal
An inverter SC1, a clocked inverter SC2 in which the control signal C and the output signal of the inverter SI1 are connected to the control terminal by inputting the input data 2, the output signal of the clocked inverter SC1 and the clocked inverter S1.
The input terminal is connected to the connection point with the output signal of C2, and the inverter SI2 outputs data to the output data O.

In FIG. 1, pMO of the inverter SI1
The gate width PW of the S transistor is 20 μm and the gate length P is
L is 2.5 μm, nMOS transistor gate width NW
Is 10 μm and the gate length NL is 2 μm.

The gate width PW and the gate length PL of the pMOS transistor of the inverter SI2 are 40 μm and 2.5 μ, respectively.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

The gate width PW of the pMOS transistors of the clocked inverter SC1 and the clocked inverter SC2 is 40 μm, the gate length PL is 2.5 μm, and the nMO is nMO.
The gate width NW of the S transistor is 20 μm, and the gate length N
L is 2 μm.

As shown in FIG. 1, the input terminals of the input data 1 are located at the terminals S on the upper and lower boundaries indicated by the broken lines in the figure.
Two terminals, TI1T and terminal STI1B, are provided.

When two layout cells are vertically stacked, the terminal STI1T and the terminal STI1B are located on the upper side and the lower side of the layout cell at the position where the terminal STI1T and the terminal STI1B are connected, and are electrically connected inside the layout cell. ing.

Similarly, referring to FIG. 1, the input terminal of input data 2 has two terminals STI2T and STI2B, and the input terminal of control signal C has two terminals STCT and STCB. , The output terminal of the output data O is
The terminal STOT and the terminal STOB have two terminals, the terminal connected to the output of the inverter SI1 has the terminal STM1T and the terminal STM1B, and the terminal connected to the input of the inverter SI2 has the terminal STM2T and the terminal STM2.
If there are two terminals of B, and two layout cells are vertically stacked, each terminal is located on the upper side and the lower side of the layout cell at the position where each terminal is connected,
Conduction is performed inside the layout cell.

The input data I1 and the input data I2 are input from the terminals STI1T and STI2T, respectively, and one of them is selected by the control signal C input from the terminal STCT, and the data selected from the terminal STOT is the output data O.
Is output as

Next, regarding the means for changing the driving ability,
This will be described with reference to FIG.

FIG. 2 is a diagram showing an example in which the drive capability of the output signal of the 2-input multiplexer circuit of FIG. 1 is doubled.

According to this embodiment, two layout cells having a relatively small driving capacity shown in FIG. 1 are arranged vertically.

Referring to FIG. 2, terminals STI1B, STI2B, terminal STCB, terminal STOB, terminal STM1B, and terminal STM2B of layout cell 1 arranged on the upper side in the figure are layout cells 2 arranged on the lower side in the figure.
Corresponding terminals, that is, terminals STI1T and STI2
T, terminal STCT, terminal STOT, terminal STM1T, and terminal STM2T, respectively.

The input signals and output signals of the logic gates of layout cell 1 and layout cell 2 are connected to each other. As a result, in the logic gates of the layout cell 1 and the layout cell 2, the corresponding gates are connected in parallel, and the drive capability of the output signal of each gate is doubled.

With the above configuration, according to the present embodiment, for example, when it is desired to change the drive capability of the output signal of the 2-input multiplexer circuit, the layout cells of the 2-input multiplexer circuit can be easily arranged by vertically stacking them. The drive capability of the output signal can be changed, and the drive capability of the output signal can be changed according to the number of vertically stacked layout cells.

[0068]

Second Embodiment Next, a second embodiment of the present invention will be described. FIGS. 3 and 4 are diagrams for explaining the second embodiment of the present invention, and more specifically, a specific configuration example when the present invention is applied to a ternary state buffer circuit is shown. There is.

In this embodiment, by arranging the layout cells of the three-valued state buffer circuit continuously in a vertical stack, the drive capability of the output signal can be changed according to the number of vertical stacks of layout cells.

The three-valued state buffer circuit of FIG. 3 is an example when the driving capacity is relatively small, and is composed of the same logic gates as the three-valued state buffer circuit when the driving capacity of the conventional example is relatively small. The connection between the logic gates is similarly configured.

Referring to FIG. 3, the ternary state buffer circuit includes an inverter SI3 for generating an inverted logic of control signal E.
A NOR gate SO1 having the input data I1 and the output signal of the inverter SI3 as inputs; a NAND gate SA1 having the input data I1 and the control signal E as inputs;
An nMOS transistor SN1 whose gate electrode is connected to the output terminal of the R gate SO1 and whose source electrode is connected to GND (ground), and pMOS whose gate electrode is connected to the output of the NAND gate SA1 and whose source electrode is connected to the power supply
A transistor SP1 and a drain electrode of the nMOS transistor SN1 and a pMOS transistor S
The drain electrodes of P1 are commonly connected, the connection point and the output terminal STO are connected, and the output data O is output from the output terminal STO.
Is output.

In FIG. 3, pMO of the inverter SI3
The gate width PW of the S transistor is 10 μm and the gate length P is
L is 2.5 μm, nMOS transistor gate width NW
Is 7.5 μm, and the gate length NL is 2.0 μm.

The pMOS transistor of the NOR gate SO1 has a gate width PW of 40 μm and a gate length PL of 2.5 μ.
m, nMOS transistor gate width NW is 20 μm,
The gate length NL is 2 μm.

The pMOS transistor of the NAND gate SA1 has a gate width PW of 20 μm and a gate length PL of 2.5.
μm, gate width NW of nMOS transistor is 20μ
m, and the gate length NL is 2 μm.

Gate width N of nMOS transistor SN1
The W is 20 μm and the gate length NL is 2 μm.

Gate width P of pMOS transistor SP1
The W is 40 μm and the gate length PL is 2.5 μm.

As shown in FIG. 3, the input terminals of the input data 1 are connected to the terminals STI on the upper and lower boundaries indicated by the broken lines.
Two terminals, 1T and terminal STI1B, are provided.

When two layout cells are vertically stacked, the terminal STI1T and the terminal STI1B are located on the upper side and the lower side of the layout cell at the position where the terminal STI1T and the terminal STI1B are connected, respectively, and are electrically connected inside the layout cell. There is.

Referring to FIG. 3, similarly, the control signal E has two input terminals, a terminal STET and a terminal STEB, and data output terminals, a terminal STOT and a terminal STOB.
There are two terminals, STM3T and STM3B, which are connected to the output of the inverter SI3, and two terminals, STM4T and STM4B, are connected to the output of the NOR gate SO1. , NAN
The terminal connected to the output of the D gate SA1 is the terminal STM.
There are two terminals, 5T and STM5B, and when two layout cells are vertically stacked, each terminal is located on the upper side and the lower side of the layout cell at the position where the respective terminals are connected, and it is conductive inside the layout cell. are doing.

The input data I1 is input from the terminal STI1T and is output from the terminal STOT according to the value of the control signal E input from the terminal STE. That is, when the control signal E is at a high level, the output data O is added to the input data I.
When 1 is propagated and the control signal E is at a low level, the output data O is electrically cut off.

Next, regarding the means for changing the driving ability,
This will be described with reference to FIG.

FIG. 4 shows an example in which the drive capability of the output signal of the ternary state buffer circuit of FIG. 3 is doubled.

Two layout cells having a relatively small driving capability are arranged vertically.

Referring to FIG. 4, the terminals STI1B, STEB, STOB, STM3B, STM4B, and STM5B of the layout cell 3 arranged on the upper side of the layout cell 3 are arranged on the lower side of the layout cell 3 arranged on the lower side. The terminals are connected to the corresponding terminals, that is, the terminal STI1T, the terminal STET, the terminal STOT, the terminal STM3T, the terminal STM4T, and the terminal STM5T, respectively.

The input signal and output signal of each logic gate of layout cell 3 and layout cell 4 are connected to each other.

As a result, in the logic gates of layout cell 3 and layout cell 4, the corresponding gates are connected in parallel, and the drive capability of the output signal of each gate is doubled.

With the above configuration, for example, when it is desired to change the driving capability of the output signal of the three-valued state buffer circuit, the driving capability of the output signal can be easily achieved by arranging the layout cells of the three-valued state buffer circuit in series vertically. Can be changed, and the drive capability of the output signal can be changed according to the number of vertically stacked layout cells.

The three-valued state buffer circuit and the like described in the above embodiment can form a circuit block for processing parallel data of, for example, 8 or 16 bits by arranging a plurality of these circuits in parallel. It is an example of a bit-slice type circuit. That is, the present invention relates to the 2-input multiplexer circuit specifically dealt with in each of the above-mentioned embodiments, and the 3-input multiplexer circuit.
It is applicable not only to the value state buffer circuit but also to the bit slice type circuit, and the output signal drive capability can be easily changed by simply arranging the bit slice type circuit layout cells in series. The driving capability of the output signal can be changed according to the number of vertically stacked cells.

[0089]

As described above, according to the present invention, the CMOS
In a functional block including a plurality of logic gates of an integrated circuit, a layout cell of one functional block is
Terminals connected to the input signal and arranged on the upper and lower boundaries, terminals connected to the output signal and arranged on the upper and lower boundaries, respectively, and terminals connected to the signals between the logic gates on the upper and lower boundaries, respectively. It is characterized by having arranged terminals, and when the driving capability is low, one layout cell is sufficient, and when changing the driving capability, it is easy to arrange the layout cells in series vertically. It is possible to change the drive capability of the output signal.

According to the present invention, the lower boundary of the layout cell of the first functional block and the upper boundary of the layout cell of the second functional block having the same function as the first layout cell are connected to each other. With this configuration, the terminal of the layout cell of the first functional block and the terminal of the layout cell of the same second functional block are connected to each other, whereby the driving capability of the output signal can be easily changed. .

Further, according to the present invention, the driving capability of the output signal can be changed in accordance with the number of vertically stacked layout cells. Therefore, when the driving capability is varied, other special wiring or driving capability is required. It has an effect that a different circuit and layout cell are not required for each. Therefore, according to the present invention, when it is desired to change the drive capability of the output signal of the functional block including a plurality of logic gates, it is not necessary to design a layout cell corresponding to the drive capability for each drive capability. , To significantly reduce the design man-hours and improve the efficiency of the design process.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and is a circuit diagram of a 2-input multiplexer circuit in the case where a driving capacity is relatively small.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention, and is a circuit diagram of a two-input multiplexer circuit when the driving ability is relatively large.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and is a circuit diagram of a ternary state buffer circuit when the driving ability is relatively small.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention, which is a circuit diagram of a ternary state buffer circuit when the driving capability is relatively large.

FIG. 5 is a circuit diagram showing a first conventional example, and is a circuit diagram of a two-input multiplexer circuit when the driving capability is relatively small.

FIG. 6 is a circuit diagram showing a first conventional example, and is a circuit diagram of a 2-input multiplexer circuit in the case where the driving capability is relatively large.

FIG. 7 is a circuit diagram showing a second conventional example, which is a circuit diagram of a ternary state buffer circuit when the driving capability is relatively small.

FIG. 8 is a circuit diagram showing a second conventional example, and is a circuit diagram of a three-valued state buffer circuit when the driving capability is relatively large.

[Explanation of symbols]

SI1, SI2, SI3, LI1, LI2, LI3 Inverter SC1, SC2, LC1, LC2 Clocked inverter SA1, LA1 NAND gate SO1, LO1 NOR gate SP1, LP1 n-channel MOS transistor SN1, LN1 p-channel MOS transistor STCT, STCB , STC, STET, STEB, S
TE, LTC, LTE control signal terminals STI1T, STI1B, STI2T, STI2B, S
TI1, STI2, LTI1, LTI2 Input data terminals STOT, STOB, STO, LTO output data terminals STM1T, STM1B, STM2T, STM2B, S
TM3T, STM4T, STM4B, STM5T, ST
M4B Intermediate node terminal C, E Control signal I1, I2 Input data O Output data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 H01L 21/82 C 27/04 A

Claims (4)

[Claims] 1. A layout cell of a functional block including a plurality of logic gates of a semiconductor integrated circuit, wherein the layout cell of the functional block is connected to an input signal and arranged on a boundary line at both ends of the layout cell. A pair of terminals connected to an output signal and arranged on the boundary lines at both ends of the layout cell, and a terminal connected to a signal between logic gates included in the functional block and arranged on the boundary lines at both ends of the layout cell. A layout cell comprising a pair and. 2. A layout cell of a functional block including a plurality of logic gates in a semiconductor integrated circuit is connected to an input signal, and a pair of terminals respectively arranged on boundaries of both ends of the layout cell is connected to an output signal. A pair of terminals arranged on the boundaries of both ends of the layout cell; and a pair of terminals connected to the signals between the logic gates included in the functional block and arranged on the boundaries of both ends of the layout cell. A boundary line at one end of one layout cell and a boundary line at the other end of another layout cell of the same functional block of the same functional block are brought into contact with each other, and a terminal at one end of the one layout cell And the corresponding terminals on the other end of the other layout cell are connected to each other,
A layout cell configured to enhance the driving capability of the functional block. 3. In addition to the layout cell of the functional block, n (n is a predetermined integer) layout cells of the same functional block as the functional block are provided, and a boundary line at one side end of one layout cell, The layout signal of another layout cell is arranged so as to be in contact with the boundary line at the other end of the layout cell alternately, and the output signal has (n + 1) times the driving capability of the original functional block. Layout cell. 4. The layout cell according to claim 1, wherein the functional block is a bit slice type circuit.