JPH0862306A - Logical circuit device - Google Patents

Abstract

PURPOSE: To dispense with a terminal, pin or the like for inputting a special signal by internally generating the special signal such as a test action mode signal. CONSTITUTION: An output terminal OUT3 and an input terminal IN5 are normally used for output or even input of a signal in an action logical circuit 11. The output terminal OUT3 usually used as the output terminal is used for input of signal through a signal from the input terminal IN5. By means of a logical product of a signal inputted from the output terminal OUT3 and a signal inputted from the input terminal IN5, a special signal such as a test action mode signal is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a built-in logic circuit such as a printed circuit board or a semiconductor integrated circuit chip in which a predetermined logic circuit is incorporated, or a semiconductor integrated circuit in which the semiconductor integrated circuit chip is housed in a predetermined package. More particularly, the present invention relates to a logic circuit device, in particular, a test operation mode for testing at least a part of the internal circuit of the logic circuit device from outside the logic circuit device, and at least a part of the internal circuit of the logic circuit device. A special control mode signal for setting such a special control mode, such as a self-diagnosis mode in which the circuit is tested by a self-determination test circuit incorporated in the logic circuit device, is provided outside the logic circuit device. By generating the special control mode signal inside the logic circuit device while following the relatively simple operation from Terminals or pins or the like for inputting the part about the logical circuit device can be made unnecessary.

[0002]

2. Description of the Related Art By converting an electronic circuit into a printed circuit board,
Many advantages such as downsizing of the whole, improvement of reliability, and reduction of power consumption can be obtained. Further, in the case of making an electronic circuit into a semiconductor integrated circuit, further downsizing of the whole,
It is possible to reduce power consumption.

Further, for example, a test of an electronic circuit formed on a printed circuit board is mainly performed from the outside of the printed circuit board through terminals, pins and the like provided on the printed circuit board. Further, also for the semiconductor integrated circuit, the test of the internal circuit is performed from the outside of the semiconductor integrated circuit via the terminals, pins, etc. provided in the package.

Therefore, in order to improve the work efficiency when testing such a printed circuit board or a semiconductor integrated circuit and prevent detection failure of a defective portion therein, a circuit used for the test is formed on the printed circuit board. Or a circuit used at the time of testing is built in the semiconductor integrated circuit. Furthermore, a self-diagnosis test circuit for self-diagnosing a circuit on the printed circuit board, a self-diagnosis test circuit for self-diagnosing a circuit incorporated in the semiconductor integrated circuit, and the like are also provided. .

For example, a test method called a scan path method using a boundary scan register is used to facilitate a test of a semiconductor integrated circuit having a logic circuit. This is to use what is called a boundary scan register for inputting or outputting a semiconductor integrated circuit, setting a logical state of a net in the logical circuit, or reading the logical state.

This boundary scan register is used in a large number of circuits under test. or,
Such a large number of boundary scan registers switch the multiplexers provided in each boundary scan register in the test mode.
By switching the multiplexers in this manner, a large number of such boundary scan registers are configured as long shift registers.

Therefore, the logical state of each boundary scan register can be set by inputting a serial data pattern to the shift register. Alternatively, by sequentially shifting the data in such a shift register, the logic state read from the circuit under test into each boundary scan register can be read out to the outside of the semiconductor integrated circuit. For example, a logic circuit such as a counter or a shift register can configure its self-diagnosis test circuit relatively easily.

Further, for example, FIG. 6 shows an example of a conventional device for facilitating the test of the logic circuit device. That is,
FIG. 6 shows a semiconductor integrated circuit in which a predetermined logic circuit having a memory circuit section is built, including a test facilitation circuit.

In FIG. 6, the logic circuit device is
A desired logic circuit is built in the normal operation logic circuit 11 and the memory circuit section 12. Particularly, in the normal operation logic circuit 11, the operation is not required in the test operation mode set according to the test operation mode signal TST input from the outside of the logic circuit device,
A part of the logical operation is performed in the logic circuit device. That is, in such a test operation mode,
The operation of the normal operation logic circuit 11 is not expected. On the other hand, the memory circuit section 12 is required to operate even in the test operation mode or in the normal operation not in such a test operation mode. Specifically, in such a test operation mode, an operation test of the memory circuit section 12 is performed.

Further, the logic circuit device has an input signal IN1.
(Input terminal IN1) p input buffers I in total
B, has a total of q input buffers IB for the input signal IN2 (input terminal IN2), has a total of r input buffers IB for the input signal IN3 (input terminal IN3), and has an input signal IN4 (input It has an input buffer IB for the terminal IN4). Also, the output signal OUT
1 (output terminal OUT1) has a total of n output buffers OB, and output signal OUT2 (output terminal OUT2) has a total of m output buffers OB.
Further, the logic circuit device has an input signal IN5 (input terminal I
N5) has an input buffer IB, and the output signal O3 (output terminal OUT3) has an output buffer O.
B, and has a test operation mode signal TST (input terminal TS
It has an input buffer IB for T or the test operation mode terminal TST). Further, as shown in FIG.
The logic circuit device has a single-system multiplexer S1. The multiplexer S1 has a multiplexer for switching a total of one signal.

FIG. 7 is a logic circuit diagram of a memory circuit unit used in the logic circuit device described above with reference to FIG.

As shown in FIG. 7, the memory circuit portion 12 shown in FIG. 6 has a total of three systems of multiplexers S2 to S4 and a memory body 12a.

First, in the system shown by reference numeral S2, the total
A multiplexer that switches between p and one signal is used. The system shown by reference numeral S3 has a total of q multiplexers. In the system indicated by reference sign S4, the total
It has r multiplexers.

These lines S2 to S4 and the above-mentioned line S
The individual multiplexers used in 1 have select inputs S
, Input 0, input 1 and output U. When the selection input S becomes "0", the logic state input to the input 0 is selected and is output to the output U. On the other hand, when "1" is input to the selection input S, the logic state input to the input 1 is selected and output to the output U thereof.

Regarding the system indicated by the reference numeral S2, the signal MI output from the normal operation logic circuit 11 used as the data input signal of the memory body 12a.
1 and the input buffer I for the input signal IN1
The input signal IN1a input from B is switched for each p total of signal units. With respect to the multiplexer of the system shown by the reference numeral S3, the signal MI2 output from the normal operation logic circuit 11 used as the address signal of the memory body 12a and the input signal IN
The input signal IN2a input from the input buffer IB according to 2 is switched in q signal units in total. The multiplexer of the system shown by the reference symbol S4 is provided with a signal MI3 output from the normal operation logic circuit 11 used as a control signal for the memory body 12a and an input signal input from the input buffer IB related to the input signal IN3. IN3a is switched in units of a total of r signals.

Therefore, in the logic circuit device shown in FIGS. 6 and 7, the test operation mode signal TST input from the outside of the logic circuit device is set to the H state to cause the normal operation logic. Independently of the circuit 11, the operation of the memory circuit section 12 can be tested from outside the logic circuit device. That is, by setting the test operation mode signal TST in the H state, it is possible to switch the signals input to the multiplexers S1 to S4 from the outside of the logic circuit device to the memory circuit section 12 side. it can. As a result, the memory circuit unit 1
2 can be directly accessed from the outside of the logic circuit device by the input signals IN1 to IN3 or the output signal OUT1. That is, while controlling the data write operation and the data read operation to the memory circuit section 12 by the input signal IN3,
While the address of the memory circuit section 12 is designated by N2, data is written to the desired address from the input signal IN1, or the output OUT1 is output from the desired address.
Data can be read out to.

Therefore, in the conventional logic circuit device shown in FIGS. 6 and 7, the test of the memory circuit section 12, which is particularly difficult to test, can be relatively easily performed. Regarding the memory circuit section 12, it is difficult to test the operation of all the memory cells while operating the normal operation logic circuit 11. However, by setting the test operation mode signal TST to the H state, the memory circuit section 12 can be directly tested from the outside of the logic circuit device, and data writing and reading can be sequentially performed on many addresses. It is possible to efficiently test the memory circuit section 12 while performing the test.

[0018]

However, although the logic circuit device shown in FIGS. 6 and 7 can more easily test the memory circuit section 12 and the like as described above, it has been described above. As described above, the test operation mode signal TST must be input from the outside of the logic circuit device. Therefore, the logic circuit device must be provided with terminals, pins, etc. for inputting the test operation mode signal.

Generally, when the number of logic circuits built in a printed board or the number of logic gates built in a semiconductor integrated circuit increases and the scale of the logic circuit increases, terminals and pins provided in the printed board or semiconductor integrated circuit. And so on. Therefore, it is not desirable to provide terminals, pins, or the like for inputting the test operation mode signal TST and the like that are unnecessary during normal operation.

In some cases, the logic circuit device may have to be compatible with existing ones or comply with various predetermined specifications. For this reason, it may not be possible to use special terminals or pins. Even in such a case, it is not desirable to provide terminals, pins, or the like for inputting the test operation mode signal TST for the purpose of merely testing.

The present invention has been made to solve the above-mentioned conventional problems, and a test operation mode for testing at least a part of the internal circuits of the logic circuit device from the outside of the logic circuit device. For setting such a special control mode such as a self-diagnosis mode in which at least a part of the internal circuit of the logic circuit device is tested by a self-diagnosis test circuit incorporated in the logic circuit device. By inputting the special control mode signal from the outside of the logic circuit device by generating the special control mode signal inside the logic circuit device according to a relatively simple operation from the outside of the logic circuit device. An object of the present invention is to provide a logic circuit device that can eliminate the need for terminals, pins, etc.

[0022]

According to the present invention, there is provided a normal operation logic circuit for performing a part of logical operation in the logic circuit device, the operation of which is not required in the special control mode set according to the special control mode signal. A normal control logic circuit and a special control mode logic circuit which are required to operate at least in the special control mode and which perform a partial logical operation in the logic circuit device. And a first input terminal for inputting a first input signal from the outside of the logic circuit device to the normal operation logic circuit, and from the normal operation logic circuit to the outside of the logic circuit device. A first input / output terminal for outputting a first output signal, a signal delay circuit for delaying the first input signal and generating a delay control signal, and a first input / output terminal for the first input / output terminal Signal and, by a specific logical operation between the delay control signal, the first output signal is H state or L
The first condition of one of the predetermined logic states of the states is satisfied, and the second condition of the predetermined logic state of the delay control signal of the H state or the L state is satisfied. In this case, by setting the special control mode signal to the special control mode, a mode signal generation circuit for generating the control mode signal and a signal path from the normal operation logic circuit to the first input / output terminal are provided. A tristate output buffer which is provided and which is used for outputting the first output signal and is brought into a high impedance state when the first input signal of the logical state of the first condition for setting the special control mode is input; In a direction in which the delay control signal is generated in the signal delay circuit in a logic state opposite to the predetermined logic state side of the second condition set in the special control mode, The signal of the first input-output terminal is also used to generate the serial delay control signal, by which a misconfiguration prevention resistor to pull up or pull-down, in which to achieve the above objects.

[0023]

In the present invention, in particular, the test operation mode signal T as described above with reference to FIGS. 6 and 7 is used.
A signal for setting some special control mode such as ST is generated inside the logic circuit device according to a relatively simple operation from the outside of the logic circuit device. Therefore, terminals or pins for inputting such a test operation mode signal TST are unnecessary.

The object of the present invention is set in accordance with the test operation mode signal TST of the conventional logic circuit device described above with reference to FIGS. 6 and 7 and the test operation mode signal TST. It is not limited to the test operation mode. For example, it can be applied to a signal for switching a multiplexer included in each boundary scan register in the above-described scan path method using the boundary scan register. In addition, the present invention can be applied to a signal or the like for setting an operation mode different from usual.

In the present invention, the generation of the special control mode signal inside the logic circuit device is performed by a completely new operating method from the outside of the logic circuit device, which has never existed before. . That is, in the present invention, the operation terminal is not required in the special control mode, and the output terminal for outputting a certain signal from the normal operation logic circuit that performs a partial logic operation in the logic circuit device is particularly bidirectional. It is designed to be an input / output terminal. That is, what has been conventionally used as an output terminal is also used for inputting a signal used for an operation such as setting of the special control mode signal. Therefore, in the present invention, it is not necessary to increase the number of input terminals for inputting a signal from the outside of the logic circuit device, such as setting such a special mode signal.

By applying the present invention, the conventional logic circuit device used as an output terminal is also used as a signal input, and is used as a bidirectional input / output terminal or a pin. In this case, it is necessary to control the signal input / output direction of such bidirectional input / output terminals and pins. Therefore, in the present invention, the input terminal used for inputting the signal of the normal operation logic circuit whose output logic (operation) is not required in the special control mode is used. That is, according to the signal input from the input terminal, the bidirectional input / output terminals or pins as described above,
The input / output direction of the signal is controlled. Therefore, it is not necessary to provide a new terminal or pin for the signal input from the outside of the logic circuit device for controlling the input / output direction of such a signal.

With respect to such bidirectional input / output terminals, pins, etc., the logic circuit device does not use an external circuit connected to the logic circuit device of the present invention when the special control mode is not used. , Are treated as simple output terminals and pins. Therefore, it is assumed that the bidirectional input / output terminals, pins, etc. for inputting the special control mode signal are switched in the direction for inputting the signal, even though there is no intention of operating the special control mode. But it doesn't matter. This is because no output circuit is connected to the bidirectional input / output terminals or pins.
Therefore, as will be described later in detail with reference to the embodiment, even if the input / output pin related to the special control mode signal is switched in the input direction in this manner, the special control mode is switched to the special control mode by the erroneous setting prevention resistor or the like. The setting is prevented.

As described above, in the present invention, the operation for setting the special control mode is performed while diverting the ones used as general input terminals and output terminals in the normal non-special control mode. . For this reason,
While following a relatively simple operation from the outside of the logic circuit device and without increasing the number of terminals or pins of the logic circuit device, a special control mode signal for setting such a special control mode is internally provided. Can be generated with.

[0029]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a logic circuit device to which the present invention is applied.

As shown in FIG. 1, in the present embodiment, the present invention is applied to the conventional logic circuit device described above with reference to FIGS. 6 and 7.

Specifically, in the conventional logic circuit device shown in FIG. 6, the output terminal OUT3 is a bidirectional input / output terminal to which the present invention is applied. The input signal IN5 is also used when the test operation mode signal TST is generated. That is,
While using the signal input from the output terminal OUT3 and the signal input from the input terminal IN5, the test operation mode signal TST is generated inside the logic circuit device while applying the present invention. ing.

Therefore, in this embodiment, as shown in FIG. 1, a mode signal generator 14 is further provided in addition to the conventional ones shown in FIGS. 6 and 7. In the mode signal generation unit 14, the input buffer IB for the test operation mode signal TST input from the outside of the conventional logic circuit device shown in FIG.
The test operation mode signal TSTa generated from the above is generated.

In the present embodiment, the test operation mode signal TSTa corresponds to the special control mode signal in the present invention. The test mode signal TS
The Ta sets the test operation mode corresponding to the special control mode in the present invention. The test operation mode is a mode in which the memory circuit unit 12 can be tested while being directly accessed from outside the logic circuit device.

Further, the normal operation logic circuit 11 performs a partial logic operation in the logic circuit device, which operation is not required in the test operation mode. In the test operation mode, since the memory circuit section 12 is mainly tested, the operation of the normal operation logic circuit 11 is not particularly required.

The memory circuit section 12 is required to operate even in the test mode. Regarding the memory circuit section 12, first, the operation is required even in the normal operation other than the test operation mode. Further, even in the test operation mode, since the test operation mode is for the purpose of testing the memory circuit section 12, the operation of the memory circuit section 12 is naturally required.

In this embodiment, in the test operation mode, the input signal IN1 is used as a data input signal used for the memory body 12a of the memory circuit section 12. The input signal IN2 is used as an address signal. The input signal IN3 is used as a control signal.

The input signal IN5 and the signal input from the input / output terminal OUT3 are used as a test enable signal and a memory test signal, respectively, and are used for the operation of generating the test operation mode signal TSTa. . The output signal OUT1 corresponds to the memory body 12a.
From the test output signal from.

FIG. 2 is a circuit diagram of a first example of the mode signal generator used in this embodiment.

FIG. 2 shows a first example of the mode signal generator 14 shown in FIG.

The mode signal generator 14 of the first example is
An input terminal IN5 for inputting an input signal IN5 from the outside of the logic circuit device of this embodiment to the normal operation logic circuit 11.
It is connected to the. The input signal IN5 of this embodiment is
It corresponds to the first input signal in the present invention. Further, the input terminal IN5 of this embodiment corresponds to the first input terminal of the present invention.

The mode signal generator 14 is also connected to the input / output terminal OUT3 for outputting the output signal OUT3 from the normal operation logic circuit 11 to the outside of the logic circuit device of this embodiment. In the conventional logic circuit device shown in FIG. 6, the input / output terminal OUT3 is a unidirectional terminal, that is, the output terminal OUT3.
The input / output terminal OUT3 of the present embodiment corresponds to the first input / output terminal that outputs the first output signal of the present invention.

Further, the mode signal generator 14 of the first example.
Is a bidirectional input / output buffer B, an input buffer IB,
It is composed of a signal delay circuit 15, an AND logic gate 16A, and a resistor R. Further, the bidirectional input / output buffer B includes a tri-state output buffer OBTA,
It is composed of an input buffer IB.

First, the tristate output buffer O
BTA corresponds to the output buffer OB connected to the output terminal OUT3 shown in FIG. The tristate output buffer OBT of the present embodiment
By A, the output signal OUT3a from the normal operation logic circuit 11 is output as the output signal OUT3 to the outside of the logic circuit device of this embodiment.

Further, the input buffer IB connected to the input terminal IN5 of this embodiment corresponds to the input buffer IB connected to the input terminal IN5 of the conventional logic circuit device shown in FIG. To do. The input buffer IB inputs the input signal IN5 (corresponding to the first input signal of the present invention) as an input signal IN5a from the outside of the logic circuit device of this embodiment to the input operation logic circuit 11. Is.

Furthermore, the output of the tristate output buffer OBTA is controlled by the input signal IN5a. That is, according to the input signal IN5a,
It is selected whether the output of the tri-state output buffer OBTA is in a high impedance state or the output signal OUT3a output from the normal operation logic circuit 11 is in a logic state. Specifically, the input signal IN
When the signal 5 is in the L state and the input signal IN5a is in the L state, the output of the tristate output buffer OBTA is in the high impedance state. On the other hand, when the input signal IN5 is in the H state and the input signal IN5a is in the H state, the tri-state output buffer OBTA outputs the same logic state as the output signal OUT3a output from the normal operation logic circuit 11. It is what is done.

The signal delay circuit 15 receives the input signal I
N5a is delayed by the delay time Td to generate the delay control signal IN5b. The AND logic gate 16A of the mode signal generation unit 14 of the first example corresponds to the mode signal generation circuit of the present invention. The AND logic gate 16A receives the test operation mode signal T based on the logic state of the input / output terminal OUT3 input via the input buffer IB and the delay control signal IN5b.
STa is generated. The AND logic gate 16
A indicates that the logic state of the input / output terminal OUT3 is the H state (corresponding to the first condition of the present invention), and the delay control signal IN5b is the L state (corresponding to the second condition of the present invention). The test operation mode signal TSTa is set to the H state. When the test operation mode signal TSTa is in the H state, the test operation mode is entered. When the test operation mode signal TSTa is in the L state, the normal operation mode other than the test operation mode is set.

The resistor R is connected to the input / output terminal OU.
It is a pull-down resistor connected to T3. When the logic circuit device of this embodiment is connected to an external circuit that does not perform the test operation mode, the bidirectional input / output terminal OU
T3 is treated as a simple output terminal OUT3. That is, no output circuit is connected to the outside of the input / output terminal OUT3 on the external circuit side.

Here, the input signal IN5 is in the L state and the input signal IN5a is in the L state in the state where the test operation mode is not set in this way, and the output of the tri-state output buffer OBTA is accordingly high. It is assumed to be in an impedance state. In such a case, if the resistor R is not provided, the input / output terminal OUT3 also becomes in a high impedance state, and its logical state becomes unstable. Here, if the input / output terminal OUT3 goes into the H state due to noise or the like, the test operation mode signal TSTa also goes into the H state, and the test operation mode is erroneously set.

However, in this embodiment, the resistor R for pulling down the input / output terminal OUT3 is provided. Therefore, even if the output of the tri-state output buffer OBTA is in the high impedance state, the logic state of the input / output terminal OUT3 is set to the L state, and the test operation mode signal TSTa is erroneously set to the H state. There is no end.

FIG. 3 is a time chart showing the operation when the mode signal generator of the first example is used in this embodiment.

In FIG. 3, the input signals IN1 to IN3 shown in FIG. 1 and composed of a plurality of signal lines.
The input signals IN5 and IN5b, the output signal OUT1 composed of a plurality of signals, and the input / output terminal OUT3.
3 is a time chart of the signal related to the above and the test operation mode signal TSTa generated by the mode signal generation unit 14. Particularly, a time chart at the time of transition from the normal operation mode other than the test operation mode to the test operation mode is shown.

[0053] During such shift to the test operation mode, as the time t ₁ in FIG. 3, first, the input signal IN5 the L state. When the input signal IN5 is in the L state, the tristate output buffer OBTA
Also, the input signal IN5a input to the signal delay circuit 15 is also in the L state, and the output of the tristate output buffer OBTA is in the high impedance state.

Here, the delay time until the logic state of the input terminal IN5 changes and the output of the tri-state output buffer OBTA changes (high impedance state or output in a predetermined logic state) changes is Tr. To do. Then, after the delay time Tr from the time when the input signal IN5 is in the L state at the time t ₁ , and after the output of the tri-state output buffer OBTA is in the high impedance state, at the time t ₂ , The logic state of the input / output terminal OUT3 becomes L state due to the charge by the resistor R used as a pull-down resistor.

[0055] In the time chart of FIG. 3, after the time t _2, the at time t _3, in order to set the test operation mode, from the outside of the input and output terminals OUT3, H state is entered There is. When the logic circuit device of this embodiment is used for an external circuit which is not tested and therefore is not in the test operation mode, the input / output terminal OUT3 is exposed to the outside.
No output circuit is connected. Therefore, as of the time t ₃ after the input terminal OUT3 it is not equal to H state. That is, even if the output of the tri-state output buffer OBTA is in a high impedance state according to the input signals IN5, IN5a, etc., the input / output terminal OUT is output by the resistor R used as a pull-down resistor.
This is because the logic state of 3 is fixed to the L state.

On the other hand, from the time t ₁ to the delay time Td
After that, the signal delay circuit 15 outputs the input signal IN5a.
The delay control signal IN5 generated by delaying
b is in the L state. In the time t _4, the logic state of the input and output terminals OUT3 is in the H state, the test operation mode signal TSTa generated by the mode signal generating portion 14 has an H state, the test operation mode Will be set.

In the time chart of FIG. 3, the input / output terminal O3 is supplied from outside the input / output terminal OUT3.
Setting the logical state of UT3 to the H state is the time t ₄
It was done at time t ₃ before. However, this way of said input output terminal OUT3 to the H state, thus the delay need not be time said time t ₄ Td elapses before may be the time t ₄ after. That is, setting the logical state of the input / output terminal OUT3 to the H state from the outside of the input / output terminal OUT3 as described above does not occur after the time t ₂ at which the output of the tri-state output buffer OBTA becomes the high impedance state. Good.

In the signal delay circuit 15, the
The delay time Td takes into consideration the delay time Tr.
It That is, the delay time Td is greater than the delay time Tr.
It is set long. In this way, the delay time Td is set.
The time t ₂After that, the try stay
The output of the output buffer OBTA is surely high impedance
The input signal IN5 or IN5a
According to the test operation mode signal TSTa,
It can be.

The delay time Tr can be said to be the time until the output signal OUT3 is surely brought to the L state by the resistor R used as a pull-down resistor. That is, it can be said that the charge time of the electric charge by the resistor R with respect to the capacitance component related to the circuits connected from the output buffer OBTA to the output terminal OUT3 and further outside the output terminal OUT3. Therefore, the delay time Tr depends on such capacitances and the resistance value of the resistor R. The larger the various capacities, the longer the delay time Tr. Also, the larger the resistance value of the resistor R, the longer the delay time Tr.

For example, when the output signal OUT3 is in the H state, a current flows through the resistor R and power consumption occurs. In order to reduce such power consumption, when the resistance value of the resistor R is increased, the delay time Tr is extended accordingly. In this case, since the delay time Td must be longer than the delay time Tr, the delay time Td is extended by the extension of the delay time Tr.
Must also be extended.

Regarding the delay times Tr and Td related to the various capacitances and the resistance value of the resistor R,
The same applies to the second and third examples of the mode signal generation unit 14 described later. For example, the same applies not only to the mode signal generator 14 in which the resistor R is a pull-down resistor, but also to the third example of the mode signal generator 14 in which the resistor R is a pull-up resistor. .

In the mode signal generator 14 of the first example, the input signal IN5 is in the L state,
Moreover, by inputting the H state from the input / output terminal OUT3, the test operation mode signal TSTa is set to the H state, and the test operation mode is set. However, the present invention is not limited to this. That is, the input signal IN5 (corresponding to the first input signal in the present invention) may be positive logic or negative logic, and the signal input from the input / output terminal OUT3 (the first input in the present invention (Corresponding to the output signal) may be positive logic or negative logic, and the test operation mode signal TSTa may be positive logic or negative logic.

For example, in the mode signal generator 14 of the second example shown in FIG. 4, the input signal IN5 has a positive logic. Along with this, the AND logic gate 16B has both its two inputs in the H state and its output in the H state. Further, the test operation mode signal TSTa is in the test operation mode when it is in the H state.

FIG. 5 is a circuit diagram of the mode signal generator 14 of the third example.

As shown in FIG. 5, in the mode signal generator 14 of the third example, the signal input from the input / output terminal OUT3 to set the test operation mode has a negative logic. There is. Corresponding to this, when the two inputs of the AND logic gate 16C are both in the L state,
The output is in the H state. Also, the AN
When the output of the D logic gate 16C is in the H state and the test operation mode signal TSTa is in the H state, the test operation mode is set.

Regarding the AND logic gate 16A used in the first example of the mode signal generator 14, the AND logic gate 16B used in the second example, and the AND logic gate 16C used in the third example, This corresponds to the mode signal generation circuit in the present invention. These AN
Each of the D logic gates 16A to 16C has a 2-input AND
Although it is a logic gate, the logic of its input is partly different. However, in either case, the test operation mode signal TSTa (corresponding to the control mode signal of the present invention) is generated by the logical product of the satisfaction of the two conditions input to the two inputs. Common.

As described above, the mode signal generation circuit of the present invention may be any one as long as it generates the control mode signal by the logical product of two conditions. In addition, the generated control mode signal is the first signal of the mode signal generation unit 14.
The test operation mode signal TSTa of the examples to the third example is not limited to the positive logic (the test operation mode is set in the H state or the special control mode), but the negative logic (L In this state, the test operation mode or the special control mode) may be used.

As described above, according to the present embodiment, the same number of input terminals IN1 to IN5 as in the conventional example described above with reference to FIGS. 6 and 7 and the output terminal OUT are used.
1 to OUT3, by applying the present invention without using the input terminal for inputting the test operation mode signal TST, which was required in the conventional example, the test operation mode signal TSTa can be changed. It can be generated internally. Further, even if the test operation mode signal TSTa is internally generated in this embodiment, there is no effect on the conventional circuit.

[0069]

As described above, the test operation mode for testing at least a part of the internal circuits of the logic circuit device from the outside of the logic circuit device and at least one of the internal circuits of the logic circuit device. A special control mode signal for setting such a special control mode, such as a self-diagnosis mode for testing a partial circuit by a self-diagnosis test circuit incorporated in the logic circuit device, is supplied to the logic circuit device. By generating it inside the logic circuit device while following a relatively simple operation from the outside,
It is possible to obtain an excellent effect that it is possible to provide a logic circuit device that does not require a terminal, a pin, or the like for inputting the special control mode signal from the outside of the logic circuit device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a logic circuit device to which the present invention is applied.

FIG. 2 is a circuit diagram of a first example of a mode signal generation unit used in the above embodiment.

FIG. 3 is a time chart showing an operation when the mode signal generation section of the first example is used in the embodiment.

FIG. 4 is a circuit diagram of a second example of the mode signal generator used in the embodiment.

FIG. 5 is a circuit diagram of a third example of the mode signal generator used in the embodiment.

FIG. 6 is a circuit diagram of a logic circuit device that facilitates conventional internal testing.

FIG. 7 is a circuit diagram of a memory circuit unit used in the conventional example or the example.

[Explanation of symbols]

11 ... Normal operation logic circuit 12 ... Memory circuit section 12a ... Memory body 14 ... Mode signal generation section 15 ... Signal delay circuit 16A to 16C ... AND logic gate IN1 to IN5 ... Input signal (or input terminal) OUT1 to OUT3 ... Output signal (Or output terminals) S1 to S4 ... Multiplexer B ... Bidirectional input / output buffer OBTA, OBTB ... Tristate output buffer IB ... Input buffer OB ... Output buffer R ... Resistor (used as pull-down resistor or pull-up resistor) MI1. MI3 ... Signals from normal operation logic circuit Tr, Td ... Delay time

Claims (1)

[Claims] 1. A normal operation logic circuit which does not require its operation in the special control mode set in accordance with the special control mode signal and which performs a part of logical operation in the logic circuit device, and at least in the special control mode. In a logic circuit device provided with these normal operation logic circuit and special control mode operation logic circuit, with a special control mode operation logic circuit that performs a part of logical operation in the logic circuit device whose operation is required, A first input terminal for inputting a first input signal from the outside of the logic circuit device to the normal operation logic circuit, and a first output signal from the normal operation logic circuit to the outside of the logic circuit device. A first input / output terminal, a signal delay circuit that delays the first input signal to generate a delay control signal, a first input / output signal at the first input / output terminal, and the delay control signal And a predetermined logical state of the first input / output signal is in the H state or the L state, and the delay control signal is in the H state or Mode signal generation for generating the control mode signal by setting the special control mode signal to the special control mode when the second condition of one of the predetermined logical states of the L state is satisfied A circuit and a logic state of the first condition for setting the special control mode, which is provided in a signal path from the normal operation logic circuit to the first input / output terminal and is used for outputting the first output signal. A tri-state output buffer that is in a high impedance state when the first input signal is input, and a logic state opposite to the side of the predetermined logic state of the second condition that is set in the special control mode. And an erroneous setting prevention resistor for pulling up or pulling down the signal of the first input / output terminal, which is also used for generating the delay control signal, in the direction in which the delay control signal is generated by the signal delay circuit. A logic circuit device characterized by being provided.