JPH0862292A - Semiconductor ic tester - Google Patents

Abstract

PURPOSE: To perform a simultaneous test at two edges by controlling both memories of waveform and timing with the data of a pattern and timing, and arbitrarily switching the applied waveform and the timing or an expected value of comparison and the timing. CONSTITUTION: Respective signal circuits of a timing part 12 and a pattern part 13 of a pattern generating stage 100 are put together in a timing-pattern signal circuit 150, and the signals are inputted to a timing memory part 15 and a waveform memory part 19. Both data of the pattern and the timing are inputted to the timing part 15 and the waveform memory part 19, respectively. A delay generating stage 200 is constituted of the timing memory part 15, a timing generating element 17, an AND gate 16 and a clock-enable terminal Q1. A waveform shaping stage 300 is constituted of an AND gate 18, OR gates 21 and 23, the memory part 19 and flip-flops 22 and 24. The total constitution is formed out of a logic comparing circuit 400 and a connecting-terminal stage 500 for testing. The change and the timing of the waveform are controlled with the pattern data, and the test can be performed at two edges.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a delay generation stage and a waveform shaping stage of a semiconductor IC tester.

[0002]

2. Description of the Related Art Conventionally, a delay generation stage of a semiconductor IC test apparatus is controlled by a timing set, and a waveform of a waveform shaping stage is controlled by pattern data. FIG. 7 shows a conventional semiconductor IC test device. Pattern generation stage 10
0, delay generation stage 200, waveform shaping stage 300
The pattern generation stage 100 includes a timing unit 12 and a pattern unit 13, and the timing unit 12 includes a timing memory unit 15 of the delay generation stage 200 and a rate (cycle). ) The generating unit 14 is used. Each signal of the timing section 12 and the pattern section 13 of the pattern generation stage 100 is input from the timing section 12 to the timing memory 15 by the timing signal circuit 10, and is also input from the pattern section 13 to the waveform memory section 15 by the pattern signal circuit 11. Delay generation stage 2
00 is the timing memory 15 of the timing memory unit 15.
a, 15b, 15c, 15d, 15e, 15f and timing generation elements 17a, 17b, 17c, 17d, 17e
, 17f and AND gates 16a, 16b, 16c, 1
It comprises 6d, 16e, 16f and a clock enable Q1. Waveform shaping stage 300 is AND gate 1
8a, 18b, 18c, 18d, 18e, 18f, 16
g, 16h, OR gates 21, 23, and waveform memory unit 19
And flip-flops 22 and 24. The logical comparison circuit stage 400 includes a logical comparison circuit section 30, a comparator 29, and a comparator 28. The test connection terminal stage 500 is composed of a buffer gate 24 and a pin terminal 25 into which the IC element under test 26 can be inserted.

The pattern generating stage 100 reads timing data and pattern data from the timing section 12 and the pattern section 13 for each test cycle. The timing data is composed of 4 bits, for example, and is supplied to the rate generator 14 and the timing memories 15a to 15f to generate a reference timing signal having a cycle (frequency) according to the timing data input from the rate generator 14. , Through gates 16a to 16f to delay circuits (timing generating elements) 17a to 17f. Further, the delay data is read from the timing memories 15a to 15f by using the timing data as an address, and the delay data read from the timing memories 15a to 15f is set in the delay circuits 17a to 17f, respectively, and the delay circuits 17a to 17f, respectively.
The amount of delay, the timing within the pinching test cycle is determined.

The waveform memory section 19 is read with the read pattern data as an address. In the waveform memory unit 19, this cycle is divided into eight for each test cycle, and these first to eighth sections (these are 0, 1, N, P, L, H,
Data is read out in each of Z and X). The designation of the first to eighth sections is 3 of the pattern data.
It is performed by bits A, B and C. For each read, the driver high level drive first data T1S, the driver low level drive third data T1R, the driver high level drive second data T2S, and the driver low level drive second data T
2R, driver low level drive third data T3R, driver enable data T3L, driver disable data T4T, and high level expected value data EXH
And the low-level expected value data EXL are read. The stored contents of the waveform memory unit 19 differ depending on the non-return waveform NRZ, its inverted waveform / NRZ, the return waveform RZ, its inverted waveform / RZ, the exclusive OR waveform XOR, its inverted waveform / XOR, etc. A type of waveform is formed according to the content.

[0005]

As described above, the timing set (TS) specializes in switching the timing, and the waveform cannot be freely switched. Further, the pattern data (PAT) switches the waveform and the expected value. It was a role, and the timing could not be switched. FIG. 5 shows the relationship between the pattern data and the timing edge. It is possible to change the waveform by the pattern data of the address names 0, 1, N and P of the waveform memory unit, but the timing information is not input to the waveform memory unit. Therefore, timing control for each waveform was impossible. Therefore, the timing edge requires three edges, T1, T2, and T3, and the timing control cannot be performed individually. FIG. 6 shows the relationship between the expected value and the comparison timing edge. The timing of performing the L, H, and Z comparison of the expected value output from the waveform memory unit has a structure in which the timing information is not input to the waveform memory unit. Requires TH, TL, TZ and 3 edges. Since the timing is fixed, the timing could not be freely controlled by the expected value during the logical comparison. In the circuit system in which timing control is commonly performed as shown in FIGS. 5 and 6, there is a limit in timing setting. In order to input the timing data into the waveform memory unit, the capacity of the conventional 8-address waveform memory may be insufficient. In order to input the pattern data into one of the timing memory units, it is 8 times larger than that of the conventional memory. There was a problem of lack of capacity. The L, H, and Z tests for device output 3-point expected value comparison are controlled by the timing edge
It was necessary to perform the test three times, one point for each of H, TL, and TZ.

[0006]

SUMMARY OF THE INVENTION A timing memory circuit and a pattern signal circuit of a pattern generation stage of a semiconductor IC test apparatus according to the present invention are collectively provided with a means for inputting from a timing pattern signal circuit to both stages, and a waveform memory section is provided. Is provided with pattern data and timing data, the timing memory section is provided with means for controlling the timing data and pattern data, and the means for increasing the memory capacity of the waveform memory section is provided. A means to increase is provided.

[0007]

FIG. 1 shows a block diagram of an embodiment of the present invention, FIG. 2 shows the relationship between pattern data and timing edges, and FIG. 3 shows the relationship between expected value comparison and timing edge during logical comparison. . It will be described with reference to FIG. The pattern generation stage 100, the delay generation stage 200, the waveform shaping stage 300, the logical comparison circuit stage 400, and the test connection pin stage 500 are included in the timing generation pattern from the pattern generation stage 100 to the delay generation stage 200 and the waveform shaping stage 300. Signal circuit 1
It is characterized in that a signal is input from 50. The pattern generation stage 100 includes a timing unit 12 and a pattern unit 13.
Of the delay generation stage 200, the timing memory unit 15, the rate (cycle) generation unit 14, and the gate unit 16
And a delay circuit section 17. The signal circuits of the timing unit 12 and the pattern unit 13 of the pattern generation stage 100 are combined into a timing / pattern signal circuit 150, and the timing memory unit 15 of the timing unit 12 is integrated.
Further, means for inputting the timing data and the pattern data to the waveform memory unit 19 of the pattern unit 13, that is, the timing data and the pattern data to the timing unit 15, and the pattern data and the timing data to the waveform memory unit 19 are provided.
The delay generation stage 200 includes the timing memories 15a, 15b, 15c, 15d, 15e of the timing memory unit 15.
, 15f and timing generation elements 17a, 17b, 17c
, 17d, 17e, 17f and AND gate 16a, 1
6b, 16c, 16d, 16e, 16f and a clock enable terminal Q1. Wave shaping stage 30
0 is an AND gate 18a, 18b, 18c, 18d, 1
8e, 18f, 16g, 16h and OR gate 21, 23
And a waveform memory section 19 and flip-flops 22 and 24. The logical comparison circuit stage 400 includes a logical comparison circuit section 30, a comparator 29, and a comparator 28. The test connection terminal stage 500 is composed of a buffer gate 24 and a pin terminal 25 into which the IC element under test 26 can be inserted.

FIG. 2 shows the relationship between the pattern data and the timing edge of the present invention, which is the address name 0 of the waveform memory section,
Since the means for changing the waveform and controlling the timing based on the pattern data of 1, N, and P is taken, the timing edge can be tested at T1, T2, and 2 edges at the same time. FIG. 3 shows the relationship between the expected value and the comparison timing edge of the present invention, which is the expected value L output from the waveform memory unit,
Since the timing for performing the H and Z comparisons has a means for inputting the timing information to the waveform memory section, the timing for the logical comparison can be switched according to the pattern data. Therefore, the timing edges are TH, TL and 2 edges. It became possible to test at the same time.

A modified embodiment is shown in FIG. The pattern generation stage 100 includes a timing unit 12 and a pattern unit 13. The pattern generation stage 100 includes a timing memory unit 15, a rate (cycle) generation unit 14, a gate unit 16 and a delay circuit unit 17 of the delay generation stage 200.
Timing signal circuit 10 and pattern signal circuit 15 from 0
To form a timing pattern signal circuit 150, and the connection portions thereof are connected to the pattern generation stage 100 and the waveform shaping stage 3 via multiplexers 160 and 170, respectively.
00, which is the pattern generation stage 100.
The signal circuits of the timing section 12 and the pattern section 13 of FIG.
Delay generation stage 2 from multiplexers 160 and 170
00 and the waveform shaping stage 300, an arbitrary bit of the timing pattern signal is taken out by a multiplexer and used as an address of the timing memory and the waveform memory, so that the respective memory amounts of the timing memory and the waveform memory are reduced.

[0010]

Since the present invention is constructed as described above, it has the following effects. 1. Conventionally, the timing is switched with the timing set,
The configuration is such that the waveform and the comparison expected value are switched according to the pattern data. According to the present invention, the waveform and the comparison expected value are switched in the timing set by using the pattern data and the timing data as the address of the waveform memory. 2. By using the pattern data and the timing set as the address of the timing memory, the timing data can be arbitrarily switched by the pattern data for each pin. 3. The relationship between the conventional pattern data and the timing edge is shown in FIG. 5. The timing for activating the pattern data with the address names 0, 1, N and P in the waveform memory section is configured to switch the timing with the timing set. Three edges, T1, T2 and T3, were required as edges. In the present invention, since the timing data can be arbitrarily switched by the pattern data for each pin by addressing the pattern data, the timing set and the timing memory, the timing edges are T1, T2 as shown in FIG. The test can be done at the same time with two edges, and the fact that it can be done with two edges makes it possible to mount the entire device in a compact size. 4. Fig. 6 shows the relationship between the conventional expected value and the comparison timing edge.
, The expected values L, H, and
When performing Z comparison, the timing of logical comparison is performed by TH, TL, and TZ of the timing set, and the test of L, H, and Z of the 3-point expected value comparison of the device output is TH, TL, and TZ by controlling the timing edge. The test had to be repeated three times, one point at a time. In the present invention, since the means for inputting the timing information to the waveform memory unit is used as the timing for performing the L, H, Z comparison of the expected values output from the waveform memory unit, the timing of the logical comparison is set as the pattern data as shown in FIG. The fact that it is possible to perform one test by switching by the above has an effect of shortening the test time. As shown in FIG. 6, the signal circuits of the timing section 12 and the pattern section 13 of the pattern generation stage 100 are combined into a timing / pattern signal circuit 150, which is delayed by the multiplexers 160 and 170. By the operation of the multiplexers 160 and 170 input to the generation stage 200 and the waveform shaping stage 300, it is possible to effectively set the memory amounts of the waveform memory unit and the timing memory unit.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing an example of the relationship between pattern data and timing edges according to the present invention.

FIG. 3 is a diagram showing an example of a relationship between an expected value and a comparison timing edge according to the present invention.

FIG. 4 is a block diagram of a modified example of the present invention.

FIG. 5 is a diagram showing an example of a relationship between pattern data and a timing edge according to the related art.

FIG. 6 is a diagram illustrating an example of a relationship between an expected value and a comparison timing edge according to the related art.

FIG. 7 is a block diagram of an embodiment of the prior art.

[Explanation of symbols]

10 timing signal circuit 11 pattern signal circuit 12 timing unit 13 pattern unit 14 rate generation unit 15 timing memory unit 15a, 15b, 15c, 15d, 15e, 15f timing memory 16a, 16b, 16c, 16d, 16e, 16f AND gate 17 delay Generating section 17a, 17b, 17c Timing generating element 17d, 17e, 17f Timing generating element 18a, 18b, 18c, 18d AND gate 18e, 18f, 18g, 18h AND gate 19 Waveform memory section 21, 23 OR gate 22, 27 Flip-flop 24 Driver 25i Pin terminal 26 IC element under test 28, 29 Comparator 30 Logic comparison circuit section 100 Pattern generation stage 150 Timing pattern signal circuit 160, 170 Multi Lexus 200 delay generating stage 300 waveform shaping stage 400 connected pins stage Q1 clock enable logic comparator circuit stage 500 tests

Claims (2)

[Claims] 1. A test connection terminal stage 500 comprises a buffer gate 24 and a pin terminal 25 into which an IC device under test 26 can be inserted, and a logic comparison circuit stage 400 comprises a logic comparison circuit section 30, a comparator 29 and a comparator 28. The AND gates (18a to 18h) are connected to the waveform memory unit (1
9), OR gates (21, 23) and flip-flops (22, 27), and AND gates (18a-1).
8h) is the delay generation unit (1) of the delay generation stage (200)
Connect to the timing element (17a-17f) of 7),
The waveform memory unit (19) includes a pattern generation stage (10
0) timing pattern signal circuit (150), which is formed by AND gates (18a-18h), waveform memory section (19), OR gates (22, 23) and flip-flops (22, 27). Stage (3
00) and the timing memory (15) of the timing memory unit (15).
a to 15f) are connected to the timing elements (17a to 17f) of the delay generator (17), and the timing elements (17a to 17f) and the clock enable (Q1) of the delay generator (17) are AND gates (16a). To 16f), the timing memory (15a to 15f) of the timing memory unit (15), the timing elements (17a to 17f) of the delay generating unit (17), and the clock enable terminal (Q).
The delay generation stage (200) composed of 1), the timing signal circuit (10) is connected to the timing unit (12), and the pattern signal circuit (11) is connected to the pattern unit (13). ), A timing pattern signal circuit (150) in which the timing signal circuit (10) and the pattern signal circuit (11) are connected to the pattern generation stage (100) is provided, which inputs the signal of the timing pattern signal circuit (150). Timing memory units (15a to 15f) of the timing memory unit (15) of the delay generation stage (200)
And a rate (cycle) generator (14), and the other side is connected to the waveform memory section (19) of the waveform shaping stage (300). 2. The timing pattern signal circuit (15)
0) and the timing memories (15a to 15f) of the timing memory unit (15) of the delay generation stage (200) are provided with a multiplexer (170), and the waveform memory unit (19) of the waveform shaping stage (300) is provided. The semiconductor IC test apparatus according to claim 1, further comprising a multiplexer (160) connected between the timing pattern signal circuit (150) and the timing pattern signal circuit (150).