JPH0856355A - Digital image compressing device and digital image expanding device - Google Patents

Abstract

PURPOSE:To improve compression efficiency and prevent a reproduced image from having screen distortion. CONSTITUTION:A system decision circuit 22 decides whether or not an input video signal is of the NTSC system or a 2nd generation EDTV system and outputs a decision signal. On the basis of the decision signal, an address generating circuit 24 generates the address of a frame memory 23. When the video signal of the 2nd generation EDTV system is inputted, the address generating circuit 24 controls the frame memory 23 and alters the data array of the vertically reinforced signal of a non-picture part so that the correlation becomes high. Consequently, the compression efficiency of compression by a DCT circuit 6 and a quantizing circuit 7 is improved.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image compression apparatus and a digital image expansion apparatus suitable for recording and reproducing second generation EDTV broadcasting.

[0002]

2. Description of the Related Art In recent years, second-generation EDTV (Extended Definition TV) broadcasting aimed at high image quality and high sound quality has been studied. Second-generation EDTV broadcasting is compatible with current broadcasting and has a screen aspect ratio of 1
The horizontal aspect ratio of 6: 9 makes it possible to watch programs with a realistic feel. The effective scanning line of the second generation EDTV signal corresponds to the vertical center 16: 9 portion of the current NTSC signal having an aspect ratio of 4: 3. Therefore, for example, when a second-generation EDTV broadcast is projected by a television receiver for current broadcasting having an aspect ratio of 4: 3,
Letterbox display is performed with a non-image area at the top and bottom of the screen and a main image area at the center.

FIG. 7 shows a screen display when such a letter box type video signal is received by a current NTSC television receiver.

The aspect ratio of the display screen 1 of an NTSC television receiver is 4: 3. In the vertical center of the display screen 1 where the aspect ratio is 16: 9, the main image portion 2 having 180 scanning lines per field is displayed, and the upper and lower scanning lines of the display screen 1 are 30 lines each. The non-image part 3 (mesh line part) of a predetermined black level is displayed in the area of. Since the aspect ratio of the main image portion 2 is 16: 9, the roundness of the projected effective image is 1.

This image has an aspect ratio of 16: 9.
When displayed on the display screen of, as shown in FIG.
Display is performed on the entire screen at a roundness of 1.

The second generation EDTV has an aspect ratio of 4:
Since only the central 16: 9 portion of the current NTSC signal of No. 3 is the effective scanning line, the number of effective scanning lines of the current NTSC signal is 480, whereas the second generation ED for transmission
The number of effective scanning lines for TV signals is 360. Second generation E
In a television receiver compatible with the DTV system,
At the time of decoding, these effective scanning lines of 360 lines are converted into 3 to 4 scanning lines and returned to 480 lines. By simply converting the scan lines,
Since the second-generation EDTV signal has a lower vertical resolution than the current NTSC signal, it has been decided to multiplex and transmit a vertical reinforcement signal for improving the vertical resolution during transmission.

In the second generation EDTV system, a progressive scanning signal of 480 lines / screen height is converted into an interlaced scanning signal and transmitted on the transmitting side. In this case, in order to make the letterbox format, that is, to make the number of effective scanning lines 360, the luminance signal of 480 lines / screen height is band-limited to 360 lines / screen height signal by the vertical low-pass filter. To do. Further, in order to convert to the interlaced scanning signal, the luminance signal is band-limited to the signal of 180 lines / screen height by the vertical low pass filter. The band limitation prevents the generation of aliasing distortion at the time of scanning line conversion. The component YL of 4.2 MHz or less in the horizontal low range of the luminance signal of 180 lines / screen height is transmitted as the main image portion signal. Also, 180 to 3 lost due to band limitation during conversion from progressive scanning to interlaced scanning
60 lines / temporal vertical high frequency component (VT signal)
Is transmitted as a vertical reinforcement signal.

The main picture portion signal and the VT signal are SSK
Separated by F (Symmetric Short Kernel Filter). As SSKF, a 3-tap or 5-tap filter is used. Further, a vertical high frequency component (VH signal) of a luminance signal of 360 to 480 lines / screen height, which is lost due to band limitation during conversion to the letterbox format, is also transmitted as a vertical reinforcement signal. These components VH and VT are added according to the movement of the image and compressed to 1/3 in the horizontal direction (time direction).

In this case, in order to allow the receiving side to separate the VT signal and the VH signal, the VH signal is line-inverted to be shifted by 15 Hz in the time axis direction and then added to the VT signal. Next, the added signal is modulated using the color subcarrier, band limited using the Nyquist filter, and multiplexed in the non-image parts at the top and bottom of the screen. In order to prevent the multiplex signal of the non-image part from standing out on the screen, a component having a correlation with the VT signal is generated from the main image part signal, and this component is subtracted from the VT signal and then added to the VH signal. It is supposed to do.

It should be noted that the component YH in the band of 4.2 to 6 MHz in the horizontal high range of the luminance signal of 180 lines / screen height is multiplexed with the main picture portion signal as the horizontal reinforcement signal HH. In this case, the frequency of the horizontal high frequency component YH is 16
The carrier is suppressed and modulated using a carrier of / 7fsc (fsc is a color subcarrier frequency), further frequency-shifted, and frequency-multiplexed with the main picture portion signal.

FIG. 8 is an explanatory diagram for explaining the multiplexed state of these horizontal and vertical reinforcement signals. FIG. 8 shows scan lines in the vertical and odd fields,
The horizontal direction indicates pixels in the horizontal direction of the screen.

One screen is composed of horizontal 910 pixels × vertical 525 lines. Of the 525 vertical lines, the number of effective scanning lines is 480, which is 240 per field. The HH signal of the horizontal reinforcement signal is multiplexed on the main image portion of the center 180 of the 240 effective scanning lines in each field. In addition, the vertical reinforcement signal VT and VH signals are multiplexed in the upper non-picture area of 30 scanning lines and the lower non-picture area of 30 scanning lines in each field. VT and VH signals are 1
The time is compressed to / 3, and the resolution of the main image portion for three lines is improved by the VT and VH signals multiplexed on one line. That is, for example, the VT and VH signals multiplexed in the period ⅓ on the left side of the screen of the first line of the upper non-picture part of each field correspond to the first line of the main picture part and ⅓ of the center.
The VT and VH signals multiplexed in the period of 1) correspond to the second line of the main image portion, and the VT and VH signals multiplexed in the right third period correspond to the third line of the main image portion.

In the second generation EDTV broadcasting,
In order to improve the YC separation performance, three-dimensional precoding is performed on the transmitting side. Incidentally, these techniques are disclosed in Japanese Patent Publication No. 208783/1992.

By the way, it is conceivable to record or reproduce the second generation EDTV broadcast signal in a consumer VTR (video tape recorder). If a digital VTR is adopted in this case, it is necessary to compress and record the second generation EDTV broadcast signal.

FIG. 9 shows a digital VTR incorporating a conventional digital image compression device and digital image expansion device.
FIG.

The consumer VTR enables high-quality recording for a long time by high-density recording and high-efficiency coding. The analog input video signal is given to the video processing circuit 5. The video processing circuit 5 converts the input video signal into a digital signal and frames it. As a result, one frame is, for example, 72
It is composed of 0 pixels × 480 lines of effective pixels. In this case, the video processing circuit 5 is adapted to shuffle the input video signal. The video signal from the video processing circuit 5 is separated into a luminance signal component and a color difference signal component for processing.
In FIG. 9, only the luminance signal component is shown for the sake of simplicity.

The image processing circuit 5 divides the framed image signal into blocks of 8 pixels × 8 lines (DCT blocks) and supplies them to the DCT circuit 6. FIG. 10 is an explanatory diagram showing blocking, FIG. 10A shows a luminance block, and FIG. 10B shows a color difference block. Since the number of effective pixels of the luminance signal is 720 pixels × 480 lines, one frame is divided into 90 × 60 luminance blocks as shown in FIG. On the other hand, due to the difference in sampling clocks between the color difference signal and the luminance signal, the sizes of the luminance block and the color difference block are different.
For example, assuming that the sampling clock of the color difference signal has a frequency of 1/4 of the sampling clock of the luminance signal, one frame of the color difference signal is composed of 180 pixels × 480 lines. Therefore, each of the color difference blocks Cb and Cr of 8 pixels × 8 lines is 1 as shown in FIG.
Only 22.5 × 60 blocks are configured in a frame.

The DCT circuit 6 converts the spatial coordinate axis component into a frequency axis component by subjecting the block data from the video processing circuit 5 to two-dimensional DCT (discrete cosine transform) processing. The transform coefficient from the DCT circuit 6 is given to the quantizing circuit 7 and quantized by using a predetermined quantizing coefficient. In this case, considering the human visual characteristics, the quantization coefficient is set larger for the higher frequency component of the transform coefficient. This reduces signal redundancy.

The output of the quantizing circuit 7 is a variable length coding circuit 8.
The variable-length coding circuit 8 gives a predetermined variable-length code table,
For example, the quantized output is variable-length coded based on the Huffman code table or the like and output to the error correction coding circuit 9. As a result, short bits are assigned to data with a high appearance probability, long bits are assigned to data with a low appearance probability,
Further reduce the amount of transmission.

In consideration of special reproduction and the like, the encoded output from the variable length encoding circuit 8 is designed to have a fixed length. This fixed length is performed, for example, in macroblock units. FIG. 11 shows the structure of a macro block. In consideration of the difference in size between the luminance block and the color difference block, the luminance 4 block and the color difference 2 block are divided into 6 blocks.
A macro block is composed of DCT blocks. Then, for example, by fixing the length to 5 macroblocks at discrete positions on the screen, the code amount is appropriately assigned regardless of the pattern.

On the other hand, the input voice signal is given to the voice processing circuit 11. The audio processing circuit 11 A / D-converts the input audio signal, synchronizes it with the video signal, performs mixing processing, and outputs it to the error correction encoding circuit 9. The error correction encoding circuit 9 encodes the compressed video data and audio data into a product code such as a Reed-Solomon code, and outputs the product code to the modulation circuit 10. The modulation circuit 10 modulates the input data by a modulation method suitable for high density recording and records it on the magnetic tape 12 via a magnetic head (not shown).

During reproduction, reproduction data from the magnetic tape 12 is given to the demodulation circuit 13 from the magnetic head. Demodulation circuit
Reference numeral 13 demodulates the reproduced data, and the demodulated data is subjected to error correction processing by the error correction decoding circuit 14. The video data from the error correction decoding circuit 14 is given to the variable length decoding circuit 15,
The audio data is given to the audio processing circuit 16. The variable length decoding circuit 15 variable length decodes the video data and supplies it to the inverse quantization circuit 17, and the inverse quantization circuit 17 inversely quantizes the variable length decoding output and supplies it to the inverse DCT circuit 18. The inverse DCT circuit 18 performs inverse DCT processing on the input data, expands the original coordinate axis data before DCT processing, and outputs it to the video processing circuit 19.

The decompressed data is subjected to deshuffling within the frame by the video processing circuit 19 to be returned to the original data array, and then D / A converted to obtain an analog output video signal. On the other hand, the audio data from the error correction decoding circuit 14 is given to the audio processing circuit 16, and after time adjustment with the video signal and correction processing, D / A conversion is performed to obtain an analog output audio signal.

Here, the second generation ED is used as an input video signal.
A TV signal shall be input. In this case, the video processing circuit 5 frames the input video signal,
The frame screen shown in FIG. 12 is obtained from the screen shown in FIG. FIG. 13 is an explanatory diagram for explaining the data of 60 lines in the upper non-image part of the frame screen. As described above, since the vertical reinforcement signal is compressed to ⅓ in the time axis direction, as shown in FIG. 13, the vertical reinforcement signal of the n-th line of the upper non-image area is the third of the main image area. (N-1) +1 to 3
Corresponds to (n-1) +3 lines.

When the video processing circuit 5 is divided into blocks, the horizontal and vertical 8 × 8 64 pixel data corresponds to 1 DCT.
Make up a block. Therefore, for example, the data of the DCT block at the upper left corner of the upper non-picture area is as shown in FIG.
The first to the eighth of the 22nd line of the first, fourth, seventh, ...
It corresponds to the pixels in the column and is discontinuous in the vertical direction. Since the number of scanning lines in the upper non-image area is 60,
If one block is composed of 8 × 8, a block in which the vertical reinforcement signal and the main image portion signal are mixed occurs. FIG. 15 is an explanatory diagram showing a DCT block in this case. As shown in FIG. 15, the main image portions 169, 172, 175, 178
Vertical reinforcement signals corresponding to lines and first to fourth main image parts
A 1DCT block is composed of the main image portion signal of the line.

By the way, in a general image, the correlation between adjacent lines is extremely high. In other words, in general video, high compression efficiency can be obtained by performing the DCT transform and then quantizing the high frequency component of the transform coefficient with a relatively large quantization coefficient. However, in the second-generation EDTV signal, since the DCT block including the non-picture portion is composed of the data of the discontinuous lines, the correlation between the vertically adjacent data is relatively low. Therefore, D
The compression using the orthogonal transformation such as the CT transformation has a problem that sufficient compression efficiency cannot be obtained.

Further, when compression is performed using data which is discontinuous in the vertical direction on the screen, distortion is likely to occur on the reproduced screen. Furthermore, in the second generation EDTV signal, VT and VH
Since the signals are frequency-modulated and multiplexed, A /
There is also a problem that the VT and VH signals may not be accurately sampled during D conversion.

[0028]

As described above, in the above-described conventional digital image compression apparatus and digital image expansion apparatus, when it is attempted to compress the second generation EDTV signal by using the orthogonal transformation, the line is generated in the non-image portion. There is a problem that the compression efficiency is significantly reduced because the data between the two are uncorrelated. Further, in this case, there is a problem that the reproduced screen is likely to be distorted. Furthermore,
There is also a problem that the VT and VH signals multiplexed in the non-picture portion cannot be sampled correctly.

The present invention compresses the second generation EDTV signal without lowering the compression efficiency, prevents the screen distortion of the reproduced image, and further correctly reproduces the VT and VH signals. The purpose is to provide.

Another object of the present invention is to provide a digital image decompression device capable of preventing screen distortion of a reproduced image and reproducing the VT and VH signals correctly.

[Constitution of Invention]

A digital image compression apparatus according to claim 1 of the present invention is a wide aspect television signal in which a vertical reinforcement signal for improving the resolution of a main image portion is multiplexed in a non-image portion period. Alternatively, a system discriminating means for discriminating the system of the input video signal on the basis of the identification signal, which is inputted with an input video signal based on a current television signal, and a storage means for storing the input video signal and outputting it in blocks. Compressing means for orthogonally modulating block data from the storing means and compressing the compressed data to output an encoded output, and writing and reading of the storing means on the basis of the discrimination result of the system discriminating means to control the block data in the vertical direction. The digital image compression apparatus according to claim 3 of the present invention is provided with a control means for improving the correlation of the main image portion during the non-image portion period. Inputting an input video signal based on a wide aspect television signal or a current television signal, in which a vertical reinforcement signal for frequency improvement is frequency-modulated and multiplexed, and a method of the input video signal is determined based on the identification signal. System discrimination means, vertical reinforcement signal demodulation means for demodulating the vertical reinforcement signal multiplexed in the non-picture portion period of the input video signal, and the input video signal is selected in the main picture portion period to Is a selection means for selecting the output of the vertical reinforcement signal demodulation means, a storage means for storing the output of the selection means, outputting the block data in blocks, and orthogonally modulating and compressing the block data from the storage means to output the encoded data. And the compression means for outputting the block data and the correlation of the block data in the vertical direction by controlling writing and reading of the storage means based on the determination result of the method determining means. It is obtained by and control means for improving a digital image decompression apparatus according to claim 5 of the present invention, any one of claims 1 or 3 1
Decoding means for decoding the encoded output from the digital image compression apparatus described in No. 1 to output block data, and data arranging means for storing the block data from this decoding means and outputting in block order. It was done.

[0032]

In the first aspect of the present invention, the system discrimination means discriminates the system of the input video signal. The input video signal is stored in the storage means, divided into blocks, and then supplied to the compression means. The compression means orthogonally modulates the block data from the storage means and compresses it. When the input video signal is a wide aspect television signal, the control unit controls writing and reading of the storage unit so as to improve the vertical correlation of the block data, for example. This improves the compression efficiency of the compression means.

In the third aspect of the present invention, the input video signal is applied to the vertical reinforcement signal demodulation means to demodulate the vertical reinforcement signal. The selecting means selects the input video signal during the main image portion period and selects the output of the vertical reinforcement signal demodulating means during the non-image portion period and supplies it to the storage means. This ensures that the vertical reinforcement signal is sampled and stored in the storage means.

In claim 5 of the present invention, the encoded output is decoded by the decoding means. The data arrangement means outputs the block data from the decoding means in raster order.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital image compression apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 9 are designated by the same reference numerals. In addition,
In FIG. 1, the color signal system is not shown.

The analog input video signal is an A / D converter 21.
And to the system discriminating circuit 22. The A / D converter 21 converts the input video signal into a digital signal and outputs it to the frame memory 23. By the A / D converter 5,
One frame is sampled so as to be composed of, for example, 720 pixels × 480 lines of effective pixels.

By the way, at the beginning of the second generation EDTV broadcasting, a signal of the current NTSC system having an aspect ratio of 4: 3 and a signal of the second generation EDTV system having an aspect ratio of 16: 9 are mixed and broadcast for each program. Expected to be done. Therefore, on the receiving side, the current NTSC system and the second generation E
It is necessary to perform control corresponding to each DTV system. Therefore, it has been decided on the transmitting side to multiplex and transmit an identification signal indicating that a second generation EDTV system broadcast signal is being transmitted. The identification signal indicates the aspect ratio of the broadcast signal and the presence / absence of various reinforcing signals, and the phase reference for demodulating the reinforcing signal is obtained.

The identification signal is at the top of the image area (22H,
285H) in the horizontal scanning period. The identification signal is
It has bit areas B1 to B27 for 27 bits.
The bit width of each bit is 7 times the color subcarrier period. The bit areas B1 to B5 and B24 are identification codes transmitted in the NRZ (non-return zero) format, and the bit area B6.
To B23 are identification codes of the color subcarrier format (frequency is fsc)
Is.

In the bit areas B25 to B27, a confirmation signal for determining the existing video signal is transmitted.
The confirmation signal has a frequency of 2.04 MHz (= (4/7) fs
It is the sine wave of c). According to the explanation on the identification control signal specifications issued by the Broadcasting Technology Development Council, the zero-cross point of the rising edge of the confirmation signal is the I-axis or Q of the color subcarrier fsc.
It is synchronized with the axis phase.

The system discriminating circuit 22 detects whether or not the identification signal is superimposed on 22H or 285H of the input video signal to determine whether the input video signal is the second generation EDTV system signal or the current NTSC system. It is configured to determine whether the signal is a signal and output a determination signal to the address generation circuit 24. The address generation circuit 24 outputs the address output for the NTSC system or the second generation EDTV system to the frame memory 23 based on the discrimination signal. In the frame memory 23, the write and read addresses are controlled by the address output from the address generation circuit 24, and the input video signal from the A / D converter 21 is shuffled into a frame and, for example, 8 pixels × 8 lines. The data is output to the DCT circuit 6 in DCT block units.

2 to 4 are explanatory diagrams for explaining the block formation by the address generation circuit and the frame memory in FIG.

When the discrimination signal indicates that the NTSC system signal is input, the address generation circuit 24 returns to A
By changing the data array of the video data from the / D converter 21 and writing to the frame memory 23 to create a frame screen, and controlling the reading, 8 × 8 DC
The data is output to the DCT circuit 6 in units of T blocks.

On the other hand, when the discrimination signal indicates that the signal of the second generation EDTV system is input, the address generation circuit 24 changes the data arrangement of the frame screen shown in FIG. A write address is given to the frame memory 23 so that the data array shown in FIG. That is, the address generation circuit 24 continuously arranges the data of the main image portion of 360 lines in the frame memory 23, and the data of the upper and lower non-image portions of 60 lines continuously after the data of the main image portion. Arrange. Further, the address generation circuit 24
Gives a write address so that the non-image part has the data array shown in FIG. That is, in the area of 720 pixels × 120 lines set as the storage area of the non-image part, 2
Write the data of 40 pixels x 360 lines. In this case, the vertical reinforcement signals (VT and VH signals) corresponding to the first line of the main picture portion are arrayed as the data of 240 pixels of the first line, and the data of 240 pixels of the second line are mainly used. The vertical reinforcement signal corresponding to the second line of the image area is arranged. Thereafter, in the same manner, 24 of the third to 360th lines
As data for 0 pixels, vertical reinforcement signals corresponding to the third to 360th lines of the main picture portion are arranged.

The address generation circuit 24 sequentially reads the data of the main picture portion in units of 8 × 8 DCT blocks. 45 × 90 DC depending on the data of the main image section
A T block is constructed. Similarly, the address generation circuit 24 also reads out the data of the non-image portion in block units of 8 × 8 lines as shown in FIG. As a result, the frame memory 23 outputs 45 × 30 DCT blocks for the non-picture portion to the DCT circuit 6.

The DCT circuit 6 performs a two-dimensional DCT (discrete cosine transform) process on the block data from the frame memory 23 to transform the spatial coordinate axis component into a frequency axis component. The transform coefficient from the DCT circuit 6 is given to the quantization circuit 7. The quantizing circuit 7 quantizes the transform coefficient using a predetermined quantized coefficient and outputs the quantized transform coefficient to the variable length coding circuit 8. The variable length coding circuit 8 variable length codes the quantized output using a predetermined variable length code table and outputs a coded output.

Next, the operation of the embodiment thus constructed will be described.

It is assumed that a current NTSC system signal is input as an input video signal. The A / D converter 21 converts the input video signal into a digital signal and outputs it to the frame memory 23. The input video signal is also given to the system discrimination circuit 22, and the system discrimination circuit 22 discriminates that the input video signal is a signal of the current NTSC system and outputs the discrimination signal to the address generation circuit 24. As a result, the address generation circuit 24 outputs an address output for framing the input video signal to the frame memory 23. Framed data is stored in the frame memory 23. The address generation circuit 24 reads data from the frame memory 23 in 8 × 8 block units and supplies the data to the DCT circuit 6.

This block data is subjected to DCT processing by the DCT circuit 6, quantized by the quantizing circuit 7 and given to the variable length coding circuit 8. The variable length coding circuit 8 performs variable length coding on the quantized output and outputs it as a coded output.

Here, it is assumed that the signal of the second generation EDTV system is input as the input video signal. Method discrimination circuit 22
Outputs to the address generation circuit 24 a discrimination signal indicating that the signal of the second generation EDTV system has been input. Second generation E
The DTV system signal is converted into a digital signal by the A / D converter 21 and then given to the frame memory 23. In the present embodiment, the address generation circuit 24 makes the data of the main image portion and the data of the upper and lower non-image portions continuous, and the data of the upper and lower non-image portions is changed to the array shown in FIG. Write to 23.

The address generation circuit 24 includes a frame memory 23.
To read data in 8 × 8 DCT block units. The block data from the frame memory 23 is supplied to the DCT circuit 6 for DCT processing, and further supplied to the quantization circuit 7 for quantization. In this case, the data of the upper and lower non-image parts is VT,
This is a VH signal and has a high correlation between adjacent lines, as in the case of the main image portion signal. As shown in FIG. 3, the address generation circuit 24 arranges the vertical reinforcement signals of the non-picture portion so as to have a high correlation in the vertical direction, and the high-frequency components of the DCT transform coefficient for the block of the non-picture portion. The power is relatively small. Therefore, also in the non-picture portion, the code amount of the quantized output can be sufficiently reduced as in the main picture portion. The quantized output is given to the variable length coding circuit 8 to be variable length coded, and then output as a coded output.

As described above, in the present embodiment, when the signal of the second generation EDTV system is input, the writing and reading of the frame memory are controlled so that the data of each line of the non-image part is vertically changed. The blocks are arranged so as to have a high correlation in the direction, and the non-picture portion can also be encoded at a high compression rate. In addition, since the DCT block is composed of continuous images, it is possible to prevent distortion on the playback screen.

FIG. 5 is a block diagram showing another embodiment of the present invention. 5, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

This embodiment is different from the embodiment of FIG. 1 in that a vertical reinforcement signal demodulation circuit 31 and a selector 32 are added. The input video signal is given to the vertical reinforcement signal demodulation circuit 31 and the selector 32. The vertical reinforcement signal demodulation circuit 31 receives an input video signal, demodulates the vertical reinforcement signal multiplexed in the non-picture portion, and outputs the demodulated vertical reinforcement signal to the selector 32. A signal indicating the timing of the non-image area is input to the selector 32 from the address generation circuit 24. The selector 32 selects the input video signal during the main image section, and the vertical reinforcement signal demodulation circuit during the non-image section.
The output of 31 is selected and output to the A / D converter 21.

In the embodiment constructed as described above,
The input video signal is A /
The signal is supplied to the D converter 21, and the output of the vertical reinforcement signal demodulation circuit 31 is supplied to the A / D converter 21 during the non-image part period. The vertical reinforcement signal demodulation circuit 31 demodulates the frequency-modulated and multiplexed vertical reinforcement signal to output a baseband vertical reinforcement signal. Since the baseband vertical reinforcement signal is applied to the A / D converter 21 during the non-image part period, the A / D converter 21 can reliably sample and digitize the vertical reinforcement signal.

Other functions and effects are similar to those of the embodiment shown in FIG.

FIG. 6 is a block diagram showing an embodiment of the digital image expanding apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 9 are designated by the same reference numerals. In addition,
In FIG. 1, the color signal system is not shown.

For example, the video signal compressed by the digital image compression apparatus shown in FIG. 1 is supplied to the variable length decoding circuit 15 as an encoding input. The variable-length decoding circuit 15 performs variable-length decoding on the coded input to restore fixed-length data and dequantizes it.
Output to 17. The inverse quantizing circuit 17 reproduces the pre-quantized transform coefficient by dequantizing the input data and outputs it to the inverse DCT circuit 18. The inverse DCT circuit 18 performs inverse DCT processing on the inverse quantized output to return the frequency axis component to the spatial coordinate axis component and store the block data in the frame memory 44.
Output to.

In this embodiment, the encoded input is NTS.
It is a coded signal of the C system or the second generation E
A discrimination signal indicating whether the signal of the DTV system is encoded is given to the address generation circuit 45.
The address generation circuit 45 controls the frame memory 44 by generating a write address and a read address based on the discrimination signal. When the discriminating signal indicating the encoded input of the NTSC system is given, the address generating circuit 45 reads the data stored in the frame memory 44 in the field order and outputs it to the D / A converter 46.

On the other hand, when the discrimination signal indicating the coding input of the second generation EDTV system is given, the address generating circuit 45 changes the data stored in the frame memory 23 to the data array shown in FIGS. An address output for converting and reading in the normal field order is output.

The video data read from the frame memory 44 is given to the D / A converter 46. The D / A converter 46 converts the digital video signal into an analog video signal and outputs it as an output video signal.

In the embodiment thus constructed,
The encoded output obtained by the embodiment of FIG. 1 or 5 is expanded. The encoded input is variable length decoded by the variable length decoding circuit 15, inversely quantized by the inverse quantization circuit 17, and the inverse D
The CT circuit 18 performs inverse DCT processing to restore the original pixel data in block units. The output of the inverse DCT circuit 18 is written in the frame memory 44 based on the write address from the address generation circuit 45.

The address generation circuit 45 creates a read address based on the discrimination signal and reads the data written in the frame memory 44 in the field order. This data is D
The A / A converter 46 restores the analog signal and outputs it as an output video signal.

In this embodiment, an image can be reproduced by decoding the encoded output created by the embodiment of FIG. 1 or FIG.

[0064]

As described above, according to the present invention, the second generation EDTV signal is compressed without lowering the compression efficiency, the screen distortion of the reproduced image is prevented, and the VT is further reduced.
And VH signals can be reproduced correctly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital image compression apparatus according to the present invention.

FIG. 2 is an explanatory diagram for explaining an example.

FIG. 3 is an explanatory diagram for explaining an example.

FIG. 4 is an explanatory diagram for explaining an example.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing an embodiment of a digital image expanding device according to the present invention.

FIG. 7 is an explanatory diagram for explaining a signal of the second generation EDTV system.

FIG. 8 is an explanatory diagram for explaining a multiplexed state of horizontal and vertical reinforcement signals.

FIG. 9 is a block diagram showing a digital VTR incorporating a conventional digital image compression device and digital image expansion device.

FIG. 10 is an explanatory diagram showing blocking.

FIG. 11 is an explanatory diagram showing a macro block.

FIG. 12 is an explanatory diagram showing a configuration of a frame screen.

FIG. 13 is an explanatory diagram for explaining data of 60 lines in the upper non-image part of the frame screen.

FIG. 14 is an explanatory diagram for explaining blocking of an upper non-image area.

FIG. 15 is an explanatory diagram showing a DCT block including a non-picture portion.

[Explanation of symbols]

6 ... DCT circuit, 7 ... Quantization circuit, 8 ... Variable length coding circuit, 21 ... A / D converter, 22 ... System discrimination circuit, 23 ... Frame memory, 24 ... Address generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Minoru Yoneda, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Kanagawa Prefecture, Multimedia Technology Research Laboratories, Inc. (72) Takashi Terui, 8th, Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Incorporated company Toshiba Multimedia Technology Laboratory (72) Inventor Yoshihisa Sakazaki 8 Shinsita-cho, Isogo-ku, Yokohama City, Kanagawa Prefecture Incorporated Toshiba Multimedia Technology Laboratory (72) Inventor Shuji Abe Shinsugita-cho, Isogo-ku, Yokohama City, Kanagawa Prefecture 8 Incorporated company Toshiba Multimedia Technology Laboratories (72) Inventor Shinichi Osawa 3-3-9 Shimbashi, Minato-ku, Tokyo Within Toshiba Abu E., Ltd.

Claims (5)

[Claims] 1. A wide aspect television signal in which a vertical reinforcement signal for improving the resolution of a main image portion is multiplexed during a non-image portion period, or an input video signal based on a current television signal is input and based on the identification signal. System discriminating means for discriminating the system of the input video signal, storage means for storing the input video signal and dividing it into blocks, and outputting the coded data by orthogonally modulating the block data from the storage means. And a control means for controlling the writing and reading of the storage means based on the discrimination result of the system discriminating means to improve the vertical correlation of the block data. Image compression device. 2. The wide aspect television signal is a signal of the second generation EDTV system, and the control means changes the data arrangement of the vertical reinforcement signals multiplexed in the non-picture portion period to thereby obtain the block data. 2. The digital image compression apparatus according to claim 1, wherein the vertical correlation of the above is improved. 3. A wide aspect television signal in which a vertical reinforcement signal for improving the resolution of a main image portion is frequency-modulated and multiplexed during a non-image portion period, or an input video signal based on a current television signal is input, A system discriminating means for discriminating the system of the input video signal based on an identification signal, a vertical reinforcing signal demodulating means for demodulating the vertical reinforcing signal multiplexed in the non-picture part period of the input video signal, and a main picture part period Means for selecting the input video signal and for selecting the output of the vertical reinforcing signal demodulating means during the non-image part period, storage means for storing the output of the selecting means and outputting it in blocks, and the storing means. Compression means for quadrature-modulating the block data from and compressing and outputting an encoded output, and controlling writing and reading of the storage means based on the discrimination result of the system discrimination means. Digital image compression apparatus characterized by comprising a control means for improving the vertical correlation of said block data. 4. The vertical reinforcement signal is time-compressed to ⅓ and multiplexed in the non-image portion period, and the control means ⅓ sets data of each scanning line in the non-image portion period. 4. The vertical correlation of the block data of the vertical reinforcement signal is improved by dividing each block into vertical arrays and returning to the original raster order before time compression. 2. A digital image compression apparatus according to any one of the above. 5. Decoding means for decoding the encoded output from the digital image compression apparatus according to claim 1 and outputting block data, and block data from this decoding means. A digital image decompressing device, comprising: a data arranging means for storing and outputting in raster order.