JPH0856017A - Semiconductor device, manufacture thereof, and mask for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electrode from hanging, by drawing back an outer rim portion of an upper electrode from an edge of an insolation groove forming pattern in a direction of higher etch rate in element isolation. CONSTITUTION:A semiconductor chip 32 is formed by sequentially epitaxial- growing an n-AlGaInP layer 22, a p-GaInP active layer 23, a p-AlGaInP layer 24, a p-GaAs layer 25 and a p-GaAs cap layer 26 on an n-GaAs substrate 21 in the (100) orientation. Then, a light outputting window 30 is opened in a p-side electrode 29 formed on the upper side of the chip 32. Surrounding four sides of the electrode 29 are formed to be inner by q than surrounding four sides of the chip 32. Corner parts of the electrode 29 are chamfered in a triangular shape. A corner of the chip 32 is at a distance x from the triangularly chamfered edge. Then, isolation grooves 33 in the [010] direction and in the [001] direction are formed in element isolation regions between light emitting elements C, so that each element is isolated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method for manufacturing the same, and a mask for manufacturing a semiconductor device. In particular, the present invention relates to a semiconductor light emitting device such as a light emitting diode (LED) important in the fields of optical communication or optical information processing. Further, the present invention relates to a method for manufacturing a semiconductor device including the semiconductor light emitting device and a mask for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art FIGS. 1A and 1B are a sectional view and a plan view showing a surface emitting semiconductor light emitting device A. In this semiconductor light emitting device A, on the n-semiconductor substrate 1, an n-lower clad layer 2, a p-active layer 3, a p-first upper clad layer 4,
After sequentially epitaxially growing the p-second upper cladding layer 5 and the p-cap layer 6, a partial region (for example, the central portion)
Except for the above, n-type ions are implanted into the second upper cladding layer 5 to form an n-inversion layer 7 of the opposite conductivity type in the p− second upper cladding layer 5, and the inversion layer 7 is not formed. Is used as the current passage region 8 to realize a current constriction structure. Further, a light extraction window 10 is opened in the p-side electrode 9 formed on the cap layer 6, and an n-side electrode 11 is formed on the lower surface of the lower cladding layer 2.

However, when a voltage is applied between the p-side electrode 9 and the n-side electrode 11, a reverse bias is applied between the inversion layer 7 and the second upper cladding layer 5, so that no current flows and the inversion layer 7 A current flows only in a region opposed to the current passage region 8 surrounded by, the current is injected into the active layer 3 only in that region to emit light, and this light is emitted to the outside from the light extraction window 10 on the upper surface. That is, the semiconductor light emitting device A having a small light emission diameter having the current constriction structure is constituted.

2A and 2B show an end face emission type semiconductor light emitting device B having the same current constriction structure, and the p-side electrode 9 is formed on the entire upper surface of the cap layer 6. Therefore, the light emitted from the active layer 3 is emitted to the outside from the end face of the active layer 3.

In the manufacturing process of these semiconductor light emitting devices A and B, a large number of semiconductor light emitting devices A and B are generally manufactured on one semiconductor wafer 12, but in this manufacturing process, the wafer 12 is manufactured. In order to electrically separate the elements A and B from each other and check the characteristics, as shown in FIG. 3, isolation grooves 13 are provided between the elements on the upper surface side of the wafer to separate the elements. The isolation groove 13 is formed by etching, and is generally made of GaAs or AlGaA.
In the case of s-based element, a sulfuric acid-based etchant is used,
In the case of an AlGaInP-based or GaInP-based element, a hydrochloric acid-based etchant is used. After the elements A and B are separated (isolated) by the isolation groove 13 to check the element characteristics, they are individually separated along the isolation groove 13 by the scribe method or the dicing method.

[0006]

However, in the process of manufacturing such a semiconductor light emitting device, when the wafer is isolated-etched by an etchant such as sulfuric acid or hydrochloric acid, the etching rate varies depending on the plane orientation of the wafer. In the direction in which the etching rate is high, the lower part of the p-side electrode 9 is also etched. For example, when the (100) plane wafer is used to form the isolated groove along the [010] direction and the [001] direction, the lower part of the corner of the p-side electrode 9 of each element is largely etched. It will be. When the p-side electrode 9 is etched below in this manner, as shown in FIG. 4, the p-side electrode 9 hangs downward to lower the semiconductor layer (for example, the second upper cladding layer 5 or the inversion layer 7). ), The semiconductor light emitting element is short-circuited, and the light output efficiency is reduced. Therefore, there is a problem in that yield and reliability are reduced.

The present invention has been made in view of the drawbacks of the above-mentioned conventional examples, and an object thereof is to prevent sagging of electrodes due to chipping of the chip due to isolation etching and improve the yield of semiconductor elements. Especially.

[0008]

The semiconductor device of the present invention comprises:
A semiconductor layer composed of a plurality of layers is formed on the semiconductor substrate,
In a semiconductor element in which an upper surface electrode and a lower surface electrode are provided on the upper surface of the semiconductor layer and the lower surface of the semiconductor substrate, respectively, and the elements are separated by an isolation groove from the upper surface electrode side,
It is characterized in that the outer peripheral portion of the upper surface electrode is retracted in a direction in which the etching rate at the time of element isolation is higher than that of the isolation groove formation pattern.

In particular, the structure of the semiconductor device of the present invention is suitable for use in a semiconductor light emitting element.

For example, the semiconductor layer is formed on a semiconductor substrate having a (100) plane orientation, and the [010] direction and the [00] direction are formed.
[1] In the above-mentioned semiconductor element separated between elements by an isolation groove along the direction,
In the [011] direction from the isolated groove formation pattern or

[Outside 2] It is recommended to retract in the direction (hereinafter referred to as [01 ^* 1] direction).

Specifically, in the semiconductor element in which the corners of the upper surface electrode are chamfered in a triangular shape and retracted, the distance x from the corner of the isolation groove forming pattern to the triangularly chamfered edge of the upper surface electrode is , X ≧ 3d with respect to the etching depth d of the isolation groove.

Alternatively, in the semiconductor element in which the corners of the upper surface electrode are chamfered in an arc shape and retracted, the radius of curvature ρ of the edge of the chamfered arc shape portion of the upper surface electrode is defined by the etching depth d of the isolation groove. However, ρ ≧ (3 + 3√2) d may be set.

The method of manufacturing a semiconductor device according to the present invention is
By forming a semiconductor layer composed of a plurality of layers on a semiconductor substrate and providing an upper surface electrode and a lower surface electrode on the upper surface of the semiconductor layer and the lower surface of the semiconductor substrate, respectively, a plurality of semiconductor elements can be formed on the semiconductor substrate by separating element isolation regions. After the formation, the element isolation region is etched to form an isolation groove so that the semiconductor elements are electrically separated from each other, and thereafter, the semiconductor elements are individually divided. In the method, on the upper surface of each semiconductor element, after forming the upper surface electrode so that the outer peripheral portion is recessed from the edge of the isolation groove forming pattern in the direction in which the etching rate during element isolation is large, from the upper surface electrode side The feature is that an isolation groove is formed in the element isolation region.

Further, the mask for manufacturing a semiconductor device of the present invention is a mask for forming the upper surface electrode of the above semiconductor device on the upper surface of the semiconductor layer, and in the pattern region for forming the upper surface electrode, the element separation is performed. Is characterized in that the edge in the direction in which the etching speed is high is recessed inward from the position corresponding to the edge of the pattern of the mask for forming the isolated groove.

[0015]

In the present invention, since the upper surface electrode is retracted in the direction in which the etching rate of the isolation etching for electrically isolating the elements is large, even if the semiconductor layer is largely etched in the direction, Since the upper surface electrode is not present thereon, the upper surface electrode does not hang downward, and there is no possibility that the semiconductor element is short-circuited due to the hanging upper surface electrode. For example, the structure according to the present invention is applied to a surface-emitting type semiconductor light emitting device in which the upper surface electrode is formed on almost the entire surface of the semiconductor layer, and thereby a great effect can be obtained.

Particularly, in the case of a semiconductor element formed on a wafer having a (100) plane orientation and having isolation grooves formed in the [010] direction and the [001] direction, the etching rate is in the diagonal direction of the upper surface electrode. Is larger, the corners of the upper surface electrode are diagonally aligned, that is, in the [011] direction or [011] direction.
^{* It} is recommended to retract in the [1] direction. For this purpose, the corners of the upper surface electrode may be chamfered into a triangular shape or an arc shape,
This can prevent the top electrode from hanging down. Furthermore, if the corners of the upper surface electrode are chamfered, even if the corners of the semiconductor layer are chipped and chipped when the element is divided by the dicing method or the scribing method, the upper surface electrode does not sag.

Further, since the etching depth of the isolation groove is controlled by time, the chamfered dimension of the corner portion of the upper surface electrode is
It is defined by the ratio of the etching rate in the depth direction of the isolated groove to the maximum etching rate and the depth of the isolated groove. For example, in the semiconductor element in which the corners of the upper surface electrode are chamfered in a triangular shape and retracted, x ≧ 3d may be set as described above, and the semiconductor in which the corners of the upper surface electrode are chamfered in an arc shape and retracted. In the element, ρ ≧ (3 + 3√2) d may be set as described above.

Further, by using the mask for manufacturing a semiconductor element of the present invention, the upper surface electrode can be retracted in the direction in which the etching rate is high, and the semiconductor element having the upper surface electrode having the above structure can be manufactured.

[0019]

5A and 5B are a sectional view and a plan view showing the structure of a surface emitting semiconductor light emitting device C according to an embodiment of the present invention. This semiconductor light emitting device C will be described according to the manufacturing procedure with reference to FIG. 5A. First, a 1 μm thick n-AlGaInP lower cladding layer 22 is formed on an n-GaAs substrate (wafer) 21 having a (100) plane orientation. 1 μm thick p-
GaInP active layer (light emitting layer) 23, 5 μm thick p-Al
A GaInP first upper clad layer 24, a p-AlGaAs second upper clad layer 25, and a 0.2 μm thick p-GaAs cap layer 26 are sequentially epitaxially grown to form a semiconductor chip 32. Then, the region on the upper surface of the cap layer 26 where the light extraction window 30 is to be formed is covered with an AZ resist film (not shown), and n-type ions are implanted into the semiconductor chip 32 using the AZ resist film as a mask.
At this time, n-type ions are implanted in the second upper cladding layer 25 so that the upper and lower ends of the ion implantation region are located. As a result, the n-type inversion layer (ion implantation region) 27 is formed in the second upper cladding layer 25, and the portion where the inversion layer 27 is not formed becomes the current passage region 28. At this time, the implantation depth of the n-type ions is set so as not to reach the boundary surface between the second upper cladding layer 25 and the first upper cladding layer 24. After that, the AZ resist film is removed, a new AZ resist film (not shown) is formed again on the upper surface of the cap layer 26 so as to match the opening pattern of the light extraction window 30, and an electrode metal is formed on the AZ resist film. Evaporation is performed and a p-side electrode (upper surface electrode) 29 is formed by a lift-off method. Also,
Similarly, the electrode metal is vapor-deposited to form the n-side electrode (lower surface electrode) 31 on the entire lower surface of the GaAs substrate 21.

The shape of the p-side electrode 29 thus formed on the upper surface of the semiconductor chip 32 is shown in FIG. 5 (b). p
A light extraction window 30 is opened in the side electrode 29.
The four sides of the side electrode 29 are recessed inward by q from the four sides of the semiconductor chip 32. Further, the corners of the p-side electrode 29 are chamfered in a triangular shape, and the semiconductor chip 32
Is separated by a distance x from the corner of the triangle and the chamfered edge. In order to form the p-side electrode 29 in such a shape, when the light extraction window 30 is formed by lifting off with the AZ resist film as described above, the AZ resist film is also formed around each semiconductor chip 32 (and It may be applied to the element isolation region between the elements so that the p-side electrode 29 is not formed around the semiconductor chip 32 and at the corners (and the element isolation region) by lift-off. Alternatively, only the light extraction window 30 is opened in the p-side electrode 29 by lift-off to form the p-side electrode 29, and then, the periphery of the p-side electrode 29 and the region excluding the corners are covered with a photoresist film to form the p-side electrode 29. The periphery and corners may be removed by etching with an appropriate etchant.

Thus, one GaAs substrate (wafer)
When the semiconductor light emitting devices C for a plurality of devices are formed on the device 21, the isolation grooves 33 along the [010] direction and the [001] direction are formed in the device isolation region between the devices, as shown in FIG. Are formed by etching to separate the elements. Then, after the characteristics of the semiconductor light emitting device C are checked while the devices are electrically isolated, the isolation groove 3
Individual semiconductor light emitting devices C are obtained by separating the semiconductor light emitting devices C at positions 3 by a dicing method using a dicing saw or a scribe method using a scriber.

FIG. 7 is an enlarged plan view showing a part of FIG. 6 in an enlarged manner. As shown in this figure, the corners of the p-side electrode 29 are chamfered in a triangular shape, and the edge thereof is the semiconductor chip 3
It is retracted diagonally from the corner 2 by x. Of course, FIGS. 6 and 7 show the case where the isolation groove 33 is etched only in the depth direction in a planar shape according to the pattern of the mask. However, in practice, when the isolated groove 33 is formed by etching, the etching rate varies depending on the crystal orientation. In the case of this semiconductor light emitting device C, the [011] direction and the [01 ^*
The etching rate is highest in the 1] direction. Since this is in the diagonal direction of the semiconductor chip 32, the corners 34 of the four corners of the semiconductor chip 32 are largely scraped by the isolation etching as shown in FIG. Even if the corner 34 of the semiconductor chip 32 is scraped in this way, the semiconductor light emitting device C
Since the corner portion of the p-side electrode 29 is chamfered further and retracts, the corner portion of the p-side electrode 29 is recessed in the semiconductor chip 3
There is no risk of sticking out from the sharpened corner of 2 and dripping downward to cause a short circuit accident. Also, when the semiconductor light emitting device C is cut by dicing with a dicing saw, the corners of the semiconductor chip 32 may be chipped due to chipping. In that case, however, the p-side electrode 29 jumps out from the chipped corner and hangs down. There is no fear of causing Therefore, according to the present invention, it is possible to prevent a decrease in the luminous efficiency of the semiconductor light emitting device C and reduce the defective product rate.

Next, how much the corner of the p-side electrode 29 should be retracted will be considered. The distance (diagonal distance) x for removing the corners of the p-side electrode 29 is the depth d of the isolation groove 33 and the etching rates V _V and p in the depth direction ([100] direction) of the isolation groove 33. It is determined by the ratio κ = V _H / V _V of the etching rate V _{H in} the diagonal direction ([011] direction and [01 ^* 1] direction) of the side electrode 29. That is, since the corners of the semiconductor chip 32 are diagonally etched by κd while the isolation groove 33 is etched by the depth d, the corners of the p-side electrode 29 are recessed by x ≧ κd. You can leave it. Since the value of κ is usually about 3, x ≧ 3d can be set. On the other hand, if the p-side electrode 29 is retracted too much, the electrode area is reduced, the resistance is increased, and the forward applied voltage is increased. Therefore, it is preferable to set an appropriate value within the range satisfying the above conditions. Therefore, the value of x is preferably about 3d to 10d.

As is apparent from the above description, the p-side electrode 29 is not retracted from the end of the semiconductor chip 32, but rather, to be precise, it is a semiconductor chip formed by an ideal and complete isolation groove 33. It is retracted from the corner of 32 by a distance x. To be precise, this can be explained as the relationship between the mask 35 that determines the pattern of the p-side electrode 29 and the mask 36 that determines the pattern of the isolation groove 33. What is indicated by a solid line in FIG. 9 is a mask 35 for forming the p-side electrode 29, that is, a photomask for patterning a photoresist film when etching the periphery of the p-side electrode 29, and the outside of the p-side electrode 29. A mask or the like for patterning an AZ resist film that lifts off the electrode metal with, for example, has the same pattern 35a as the outer peripheral shape of the p-side electrode 29. Further, what is indicated by the alternate long and short dash line is a mask 36 for forming the isolation groove 33, and has, for example, a pattern 36a for patterning a resist film or the like covering a region other than the isolation groove 33. Figure 9
In the figure, the mask 35 and the mask 36 are shown in alignment with each other. In these masks 35 and 36, if the distance x from the corner of the pattern 36a for the isolation groove to the oblique corner of the pattern 35a for the p-side electrode is designed to satisfy the expression or the expression, The semiconductor light emitting device C as described above can be manufactured.

FIGS. 10A and 10B are a sectional view and a plan view showing the structure of an edge emitting semiconductor light emitting device D according to another embodiment of the present invention. This semiconductor light emitting device D
In this case, the [010] direction of the p-side electrode 29 and [00]
1] The edge parallel to the direction (side in contact with the isolation groove 33) is not retracted from the edge of the semiconductor chip 32,
P at the corners of the [011] direction and the [01 ^* 1] direction
The side electrode 29 is chamfered so that only the corner of the p-side electrode 29 is retracted from the corner of the semiconductor chip 32.

Therefore, even in this semiconductor light emitting device D, the semiconductor chip 32 has the [011] direction and [011] direction.
^* 1] The semiconductor chip 32 is largely etched in the direction
Even if the corner of the p-side electrode is missing, the corner of the p-side electrode 29 is unlikely to hang down, and a short-circuit accident of the semiconductor light emitting element D can be prevented. On the other hand, the edges in the [010] direction and the [001] direction are not recessed, but the etching rate in this direction is not as high as that in the [011] direction or [01 ^* 1],
Further, even if each side of the semiconductor chip 32 is etched, the p-side electrode 29 is less likely to hang down as much as when the corners are etched. Therefore, the p-side electrode 29 may not be retracted in this portion.

Further, the chamfered shape of the corner portion of the p-side electrode 29 is not limited to the triangular shape as in the above embodiment, and may have any shape. For example, the p-side electrode 29
The corners in the [011] direction and the [01 ^* 1] direction may be chamfered in an arc shape. The case of the surface emission type semiconductor light emitting element E is shown in FIG. 11, and the case of the edge emission type semiconductor light emitting element F is shown in FIG.

In the case where the corners of the p-side electrode 29 are formed in an arc shape, if only the corners are recessed, ρ ≧ (√2 + 1) κd ... You know what you need to do. Further, as shown in FIGS. 11 and 12, when the edges of the p-side electrode 29 other than the corners are retracted by q, ρ ≧ (√2 + 1) [κd− (√2) q] ... Good. The value of κ is usually about 3, so if there is no recess other than the corners, ρ
It is sufficient that ≧ (3 + 3√2) d, and in particular, the value of ρ is preferably about 8d to 25d. Κ is the etching rate V _V and p in the depth direction of the isolation groove 33.
Diagonal direction of the side electrode 29 ([011] direction and [011]
^* 1] direction) etching rate V _H ratio κ = V _H / V _V.

In a semiconductor light emitting device epitaxially grown on a GaAs substrate having a (100) plane orientation, the etching rate is high in the [011] direction and the [01 ^* 1] direction when separating the devices, and among them, AlGaInP and GaInP are among the above.
Is remarkable when etching is performed with a hydrochloric acid-based etchant. In particular, a semiconductor light emitting element is generally a wafer having a (100) plane orientation as in the above embodiment, and is often divided in the [010] direction and the [001] direction. In that case, the p side is used. Since the semiconductor chip 32 is scraped off at the corners of the electrode 29, the effect of preventing the p-side electrode 29 from sagging is great as in the above-described embodiments. However, as shown in FIG. 13A, a wafer 37 having a (100) plane orientation is used and [01
In some cases, the isolation groove 33 is formed in parallel with the [1] direction and the [01 ^* 1] direction to perform element isolation. In the case of such a semiconductor light emitting device G, the isolation groove 33
Since the etching rate increases in the direction orthogonal to the longitudinal direction of the semiconductor chip 32, the semiconductor chip 32 is largely etched in the direction perpendicular to each side as shown in FIG. Therefore, in this case, the p-side electrode 29 may be patterned so as to retract not only the corners of the p-side electrode 29 but also the entire side or the central part of each side.

The present invention is not limited to a semiconductor light emitting device such as a light emitting diode or a semiconductor laser device, but a semiconductor device such as a Schottky barrier diode in which electrodes are formed on the entire upper surface and the entire lower surface. Can be generally applied to.

[0031]

According to the present invention, since the upper surface electrode is retracted in the direction in which the etching rate of the isolation etching for separating the elements is large, even if the semiconductor layer is largely etched in the direction, Since the upper surface electrode does not exist on the upper side, the upper surface electrode does not hang downward, and there is no possibility of causing a short circuit accident due to the hung upper surface electrode of the semiconductor element. In particular, the structure according to the present invention is applied to a surface-emitting type semiconductor light emitting device in which the upper surface electrode is formed on almost the entire surface of the semiconductor layer, and thereby a great effect can be obtained.

Particularly, a general semiconductor element, that is, (1
Formed on the (00) plane wafer and in the [010] direction and [0] direction.
In the case of a semiconductor element in which an isolation groove is formed in the [01] direction, the etching rate increases in the direction of the corners of the upper surface electrode, so if the corners of the upper surface electrode are chamfered in a triangular shape or an arc shape, the upper surface It is possible to prevent sagging of the electrodes. Further, if the corners of the upper surface electrode are chamfered, the upper surface electrode does not sag even when the semiconductor layer is chipped when the element is divided by the dicing method or the scribing method.

Therefore, according to the present invention, it is possible to prevent a short-circuit accident of the semiconductor element due to the upper surface electrode and improve the yield rate of the semiconductor element. In particular, in the case of a semiconductor light emitting device, it is possible to prevent a decrease in light emitting efficiency due to a short circuit and improve the yield of semiconductor light emitting devices such as light emitting diodes and semiconductor laser devices. Moreover, since it is only necessary to change the shape of the electrode and it is not necessary to change the manufacturing process or the like, the quality of the semiconductor element can be improved by a simple method.

[Brief description of drawings]

1A and 1B are a cross-sectional view and a plan view showing a conventional surface-emitting type semiconductor light emitting device.

2A and 2B are a cross-sectional view and a plan view showing a conventional edge-emitting semiconductor light emitting device.

FIG. 3 is a cross-sectional view showing a semiconductor light emitting device separated from each other by an isolation groove.

FIG. 4 is an enlarged cross-sectional view illustrating a problem of a conventional example.

5A and 5B are a cross-sectional view and a plan view of a semiconductor light emitting device according to an embodiment of the present invention.

FIG. 6 is a plan view showing a state in which a plurality of semiconductor light emitting elements formed on a wafer are separated by isolation grooves.

FIG. 7 is a partially enlarged plan view of FIG.

FIG. 8 is an explanatory view of the operation of the present invention.

FIG. 9 is a diagram showing a mask for forming a p-side electrode and a mask for forming an isolation groove in an overlapping manner.

10A and 10B are a sectional view and a plan view of a semiconductor light emitting device according to another embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor light emitting device according to another embodiment of the present invention.

FIG. 12 is a plan view of a semiconductor light emitting device according to another embodiment of the present invention.

13A is a view showing a (100) plane wafer and an isolation groove on the wafer, and FIG. 13B is a schematic perspective view showing one element of the semiconductor light emitting element having the isolation groove formed therein.

[Explanation of symbols]

 21 GaAs substrate 23 Active layer 29 p-side electrode 30 Light extraction window 31 n-side electrode 32 Semiconductor chip 33 Isolation groove 35, 36 Mask

Claims (7)

[Claims] 1. A semiconductor layer having a plurality of layers is formed on a semiconductor substrate, and an upper surface electrode and a lower surface electrode are provided on an upper surface of the semiconductor layer and a lower surface of the semiconductor substrate, respectively. In the semiconductor element separated from each other, the outer peripheral portion of the upper surface electrode is recessed in the direction in which the etching rate at the time of element separation is higher than the edge of the isolation groove forming pattern. 2. The semiconductor device according to claim 1, which is a semiconductor light emitting device. 3. The device according to claim 1, wherein the semiconductor layer is formed on a semiconductor substrate having a (100) plane orientation, and elements are separated by isolation grooves along the [010] direction and the [001] direction. In the semiconductor element of, the corner portion of the upper surface electrode is formed in the [011] direction or A semiconductor device characterized by being retracted in the direction. 4. The semiconductor device according to claim 3, wherein the corners of the upper surface electrode are chamfered in a triangular shape and retracted, and from the corner of the isolation groove forming pattern to the triangularly chamfered edge of the upper surface electrode. A semiconductor element, wherein the distance x is set to x ≧ 3d with respect to the etching depth d of the isolation groove. 5. The semiconductor element according to claim 3, wherein a corner of the upper surface electrode is chamfered in an arc shape and retracted, and a radius of curvature ρ of an edge of the chamfered arc shape portion of the upper surface electrode is isolated. A semiconductor element characterized in that ρ ≧ (3 + 3√2) d with respect to the etching depth d of the groove. 6. A semiconductor layer having a plurality of layers is formed on a semiconductor substrate, and an upper surface electrode and a lower surface electrode are provided on an upper surface of the semiconductor layer and a lower surface of the semiconductor substrate, respectively, thereby separating element isolation regions on the semiconductor substrate. After forming a plurality of semiconductor elements, the element isolation region is etched to form an isolation groove to electrically isolate the semiconductor elements from each other, and thereafter, each semiconductor element is divided into individual parts. In the method for manufacturing a semiconductor element, the upper surface electrode is formed on the upper surface of each semiconductor element such that the outer peripheral portion is recessed from the edge of the isolation groove forming pattern in the direction in which the etching rate during element isolation is large. A method of manufacturing a semiconductor device, characterized in that an isolation groove is formed in the device isolation region from the upper surface electrode side. 7. A mask for forming an upper surface electrode on the upper surface of a semiconductor layer in the semiconductor element according to claim 1, 2, 3, 4 or 5, comprising: a pattern region for forming the upper surface electrode; A mask for manufacturing a semiconductor device, characterized in that an edge in a direction of a high etching rate for separating elements is recessed inward from a position corresponding to an edge of a pattern of a mask for forming an isolated groove.