JPH0855143A - Vhdl simulator - Google Patents

Abstract

PURPOSE:To simulate a VHDL model which includes a two-way signal in itself by generating a model wherein the two-way signal is divided into an input dedicated signal and an output dedicated signal and outputting a simulation result from the output dedicated signal when the output dedicated signal is active. CONSTITUTION:In a VHDL simulator, a VHDL model A8 which has the two- way signal or two-way terminal is divided into the input dedicated signal and output dedicated signal. On the basis of test pattern A7 input information and a VHDL model A8, a two-way signal input/output mode deciding function A4 decides the input/output mode of the two-way signal; and an input test pattern is extracted and passed as the input dedicated signal to a simulation part in input mode and the simulation result is outputted as an output dedicated signal in output mode. Consequently, the design restrictions of the VHDL model that the control signal of the two-way signal should be led out of the model are made unnecessary.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a V with bidirectional signals.
HDL (V HSIC H ardware D escription L anguage)
The present invention relates to a VHDL simulator that is useful when performing a simulation on a model.

[0002]

2. Description of the Related Art RTL (register trans
fer level) description or behavior level (behavioral leve
The conventional configuration of a VHDL simulator for simulating a logic circuit written in VHDL, which is a dedicated language described in l), is shown in FIG.
A parsing function E1 for parsing the DL description, a code conversion function E2 for converting the VHDL model of the analysis result into a code readable by the CPU, and a VH for interpreting the converted code.
It has a simulation function E3 for simulating the operation described in the DL model and an output function E4 for outputting the simulation result. The VHDL language specification is standardized as, for example, IEEE1076.

[0003]

In the conventional VHDL simulator described above, the VHDL using each of the functions described above is used.
When handling a bidirectional signal existing in the model, the value of the control signal for controlling the input / output mode of the bidirectional signal must be referenced from outside the model.

That is, when the input / output mode of the bidirectional signal existing in the VHDL model is determined and a control is given to the bidirectional signal or control is performed so as to output the simulation result, the control is performed in the VHDL model. The value of the control signal for controlling the input / output mode of the existing bidirectional signal must be referenced from outside the VHDL model.

However, according to the VHDL description specification, VH
There is a constraint that the signal value existing inside the DL model cannot be referenced from outside the model.
Therefore, there is a design constraint that the control signal for controlling the input / output mode of the bidirectional signal existing in the VHDL model has to be extracted to the outside of the VHDL model.

If the above design restrictions are not accepted in circuit design, it is impossible to simulate a VHDL model including bidirectional signals.

Therefore, the present invention solves the above problems,
An object is to provide a VHDL simulator that enables simulation of a VHDL model including bidirectional signals in the model.

[0008]

In order to achieve the above object, the present invention, when a bidirectional signal is detected in an input VHDL model, converts the bidirectional signal into an input dedicated signal and an output dedicated signal. A divided model is generated, and a test pattern is input to the input-only signal when the input-only signal is active for the bidirectional signal based on the model and the input test pattern information. There is provided a VHDL simulator configured to output a simulation result from the output-only signal when active.

Also, the VHDL simulator of the present invention is
Syntax analysis means for performing syntax analysis on the input VHDL model, and the VH analyzed by the syntax analysis means
Code conversion means for converting the DL model into a code readable by the CPU, and the VHDL for interpreting the converted code.
A simulation means for simulating the operation described in the model, and further, the input V
A bidirectional signal input / output mode determination means for determining, when a bidirectional signal exists in the HDL model, whether the bidirectional signal is in an input signal receivable state or a signal value output state at the current simulation time. A test pattern inputting means for giving an input test pattern to the bidirectional signal when the input / output mode judgment result of the bidirectional signal input / output mode judging means indicates that the input signal can be received; And an output unit for outputting the simulation result of the bidirectional signal to a file when the determination result of the input / output mode by the mode determination unit is a signal output state.

In the VHDL simulator of the present invention, preferably, the code conversion means registers the code of the model obtained by dividing the bidirectional signal into an input-only signal and an output-only signal in the storage means in the conversion of the VHDL model. It has a feature.

Further, the VHDL simulator of the present invention preferably comprises a test pattern input means for outputting a bidirectional signal name when a test pattern is input and a bidirectional signal is detected based on the test pattern information. There is.

Further, in the VHDL simulator of the present invention, preferably, the bidirectional signal input / output mode determination means registers the bidirectional signal name output from the test pattern input means in the storage means by the code conversion means. Bidirectional signal searching means for searching in the code of the VHDL model is provided.

Further, in the VHDL simulator of the present invention, preferably, the bidirectional signal input / output mode determination means is based on the model recorded in the storage means and the test pattern information input from the test pattern input means. When the divided input-only signal is active, the bidirectional signal is determined as an input mode, and when the divided output-only signal is active, the bidirectional signal is determined as an output mode. is there.

The VHDL simulator of the present invention, as a preferred mode, is a syntactic analysis means for performing syntactic analysis on the input VHDL model, and the CPU analyzes the VHDL model analyzed by the syntactic analysis means. A code converting means for converting into a possible code, said VH
Code conversion means for converting a bidirectional signal in the DL model into a model in which it is divided into an input-only signal and an output-only signal, and a simulation means for interpreting the converted code and simulating the operation described in the VHDL model, Test pattern input means for inputting a test pattern and outputting at least a bidirectional signal name when a bidirectional signal is detected based on the input test pattern information, and the bidirectional signal output from the test pattern input means VH output by the code conversion means based on the name
A bidirectional signal searching means for searching a bidirectional signal for the code of the DL model, and a bidirectional signal in the VHDL model found by the bidirectional signal searching means,
For the bidirectional signal divided into the input-only signal and the output-only signal, based on the test pattern information, when the input-only signal is active, the input mode is determined, and when the output-only signal is active, the input mode is input. Input / output mode determination means for determining the mode, test pattern input means for applying the test pattern to the bidirectional signal when the input / output mode determination result by the input / output mode determination means indicates that the input signal can be received, Output means for outputting the simulation result of the bidirectional signal to a file when the input / output mode determination result by the entry output mode determination means is a signal output state.

[0015]

According to the present invention, a VHDL model having a bidirectional signal or a bidirectional terminal is divided into an input-only signal and an output-only signal inside the VHDL simulator, and based on the test pattern input information and the VHDL model, Determine the input / output mode of the bidirectional signal, extract the input test pattern in the input mode and pass it to the simulation section as the input-only signal, and output the simulation result as the output-only signal in the output mode. Therefore, the design constraint of the VHDL model that the control signal of the bidirectional signal has to be extracted outside the model is unnecessary.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention.
With reference to FIG. 1, in the present embodiment, a test pattern input function A1 for inputting a test pattern A7, a parsing function A2 for parsing an input VHDL description, and a VHD of an analysis result.
A code generation function A3 for converting the L model into a code readable by the CPU and generating it, a bidirectional signal input / output mode determination function A4 for determining the input / output mode of the bidirectional signal, and a determination for the bidirectional signal input / output mode determination function A4 Based on the results, VH
It is composed of a VHDL simulator function A5 for simulating the operation described in the DL model and an output function A6 for outputting the simulation result.

FIG. 2 is a flow chart showing details of the processing in the configuration of this embodiment shown in FIG.

Referring to FIG. 2, the test pattern input function A1 includes a test pattern interpretation unit B1, an instruction interpretation unit B2,
It has a test pattern application unit B3.

The syntax analysis function A2 has a VHDL model syntax interpretation unit B4, and the code generation function A3 has a code conversion unit B5.

The bidirectional signal input / output mode determination function A4 has a bidirectional signal search section B6 and an input / output mode determination section B7. Further, the VHDL simulator function A5 has a simulation unit B8, and an output function A6.
Has an instruction interpretation unit B9 and an output unit B10.

FIG. 3 shows the bidirectional signal C2 and the bidirectional signal C2.
FIG. 6 is a diagram for explaining an example of an input VHDL model having a control signal C1 with respect to FIG.

FIG. 4 shows a syntax interpretation function A2 and a code generation function A shown in FIG. 1 for the input VHDL model example shown in FIG.
3 is a diagram for explaining a model having a bidirectional signal expanded on a memory B14 (see FIG. 2) after applying No. 3; FIG.

Next, the operation of this embodiment will be described with reference to the drawings.

First, the VHDL model having the bidirectional signal C2 shown in FIG. 3 is input to the syntax interpreting unit B4 and converted into a code which can be interpreted by the CPU in the code converting unit B5. The signal is shown in Figure 4.
The input dedicated signal D2 and the output dedicated signal D3 are divided and registered in the memory B14.

The test pattern interpretation unit B1 is provided with a signal name, a signal attribute, and a signal name defined in the input test pattern B12.
When the test pattern information such as the signal value for the signal name is read and registered in the memory B13 and the read information includes the information for the bidirectional signal C2, the bidirectional signal name is transmitted to the bidirectional signal search unit B6. To do. The test pattern information is given in the event table in the event-driven simulator.

The bidirectional signal search section B6 extracts the signal information of the input-only signal D2 and the signal information of the output-only signal D3 for the bidirectional signal C2 from the model registered in the memory B14, and determines the input / output mode. The extracted signal information is passed to the section B7.

The input / output mode determination unit B7 determines the input / output mode for the bidirectional signal C2 from the contents of the signal information for the input dedicated signal D2 and the output dedicated signal D3, and the determination result is the instruction interpretation unit B2, the instruction interpretation unit. Transmit to B9.

More specifically, the input / output mode determination section B7 determines that the bidirectional signal C2 is in the input mode when the test pattern for the input-only signal D2 is active, and the test pattern for the output-only signal D3 is active. At this time, it is determined that the bidirectional signal C2 is in the output mode. The test pattern is usually represented by 1, 0, X (indefinite), Z (high impedance), or the like.

When the result of the judgment by the input / output mode judging unit B7 is the judgment for the input mode, the instruction interpreting unit B2 instructs the test pattern applying unit B3 to the memory B1.
Test pattern is extracted from 3 and simulation part B
The instruction to pass the test pattern to 8 is output.

When the determination result in the input / output mode determination unit B7 is the determination for the output mode, the instruction interpretation unit B9 extracts the simulation result from the memory B15 storing the simulation result in the simulation unit B8. A command is transmitted to the output unit B10 so as to output the simulation result, and the simulation output result B16 is obtained.

As described above, according to this embodiment,
A VHDL model with bidirectional signals or bidirectional terminals is divided into an input-only signal and an output-only signal inside the VHDL simulator, and the input / output mode of the bidirectional signal is determined based on the test pattern input and the VHDL model. However, in the input mode, the input test pattern is extracted and passed as an input signal to the simulation section, and in the output mode, the simulation result is output from the output-only signal, so that the bidirectional control signal is output from the model outside. Simulation can be performed without pulling out
It is not necessary to impose a design constraint on the VHDL model that a control signal of a bidirectional signal must be extracted outside the model.

[0033]

As described above, according to the present invention,
It is not necessary to impose on the VHDL model a design constraint that the control signal has to be drawn out of the model for the VHDL model having bidirectional signals. Can output.

Therefore, according to the present invention, conventionally, when the above design constraint is not allowed in the circuit design, it is impossible to simulate a VHDL model including a bidirectional signal. This has the effect of enabling the execution of simulation.

According to the present invention, the above-mentioned effects can be obtained similarly by the configuration having the preferable modes defined in claims 3 to 6, and the VHDL simulator defined in claim 7 can also provide the above-mentioned effect. This is effective, and the range of application of the circuit simulation by the VHDL model is expanded to significantly improve the design efficiency in large-scale logic LSI design and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing details of processing according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of an input VHDL model.

FIG. 4 is a model on a memory after applying an embodiment of the present invention to the input VHDL model shown in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional VHDL simulator.

[Explanation of symbols]

 A1 test pattern input function A2 syntax analysis function A3 code generation function A4 bidirectional signal input / output mode determination function A5 VHDL simulator function A6 output function A7 test pattern A8 VHDL model A9 output result B1 test pattern interpretation unit B2 instruction interpretation unit B3 test pattern Application section B4 Syntax interpretation section B5 Code conversion section B6 Bidirectional signal search section B7 Input / output mode determination section B8 Simulation section B9 Instruction interpretation section B10 Output section B11 VHDL model B12 Test pattern B13, B14, B15 Memory B16 Simulation output result C1 control Signal C2 Bidirectional signal D2 Input only signal D3 Output only signal

Claims (7)

[Claims] 1. When a bidirectional signal is detected in an input VHDL model, a model in which the bidirectional signal is divided into an input dedicated signal and an output dedicated signal is generated, and the model and the input test pattern information are generated. Based on the above, a test pattern is input to the input-only signal when the input-only signal is active with respect to the bidirectional signal, and a simulation result from the output-only signal is output when the output-only signal is active. VHDL simulator configured to. 2. Parsing means for parsing an inputted VHDL model; code converting means for converting the VHDL model analyzed by the parsing means into a code readable by a CPU. A simulation means for interpreting the input code and simulating the operation described in the VHDL model, and further, if a bidirectional signal exists in the input VHDL model, the bidirectional signal is simulated. A bidirectional signal input / output mode determination means for determining whether the input signal is in an acceptable state or a signal value output state at time, and the input / output mode determination result by the bidirectional signal input / output mode determination means is input. When the signal can be received, the test pattern inputting means for giving the input test pattern to the bidirectional signal And an output unit for outputting the simulation result of the bidirectional signal to a file when the result of the input / output mode determination by the bidirectional signal input / output mode determination unit is a signal output state. . 3. The code conversion means registers the code of a model obtained by dividing the bidirectional signal into an input-only signal and an output-only signal in the storage means in the conversion of the VHDL model. VHDL simulator. 4. The VHDL according to claim 2, further comprising a test pattern input means for outputting a bidirectional signal name when a test pattern is input and a bidirectional signal is detected based on the test pattern information. Simulator. 5. The bidirectional signal input / output mode determination means,
The bidirectional signal search means for searching the bidirectional signal name output from the test pattern input means in the code of the VHDL model registered in the storage means by the code conversion means is provided. VHDL described
Simulator. 6. The bidirectional signal input / output mode determination means,
Based on the model recorded in the storage unit and the test pattern information input from the test pattern input unit,
The bidirectional signal is determined as an input mode when the divided input-only signal is active, and the bidirectional signal is determined as an output mode when the divided output-only signal is active. VHD described in 3
L simulator. 7. Parsing means for parsing an input VHDL model, and code conversion means for converting the VHDL model analyzed by the parsing means into a code readable by a CPU. A code conversion means for converting a bidirectional signal in the VHDL model into a model in which an input-only signal and an output-only signal are divided; and a simulation means for interpreting the converted code and simulating the operation described in the VHDL model. A test pattern input means for inputting a test pattern and outputting at least a bidirectional signal name when a bidirectional signal is detected based on the input test pattern information; and both of the test pattern input means output from the test pattern input means. The code of the VHDL model output by the code converting means based on the direction signal name. Bidirectional signal searching means for searching for bidirectional signals, and the VHD found by the bidirectional signal searching means
For the bidirectional signal in the L model, which is divided into the input-only signal and the output-only signal, based on the test pattern information, when the input-only signal is active, it is determined as the input mode However, when the output-only signal is active, the input / output mode determination unit determines the input mode, and when the determination result of the input / output mode by the input / output mode determination unit indicates that the input signal can be accepted A test pattern inputting means for giving a directional signal, and an output means for outputting the simulation result of the bidirectional signal to a file when the input / output mode determining means determines the input / output mode is a signal output state. Characteristic VHDL simulator.