JPH085209B2 - Thermal head protection circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head protection circuit used in a device having a thermal head such as a thermal printer and a facsimile machine.

[Prior Art] A thermal head used in a thermal printer or a facsimile machine applies a current pulse to a resistor as a heating element to generate heat, thereby causing a thermal paper to color and transfer ink on a film. Although the print data is printed, this thermal head cannot be used because the resistor burns out if the pulse width of the current pulse applied to the resistor becomes abnormally long. However, systems such as thermal printers and facsimile machines are usually driven and controlled by a microcomputer, and the energizing pulse width to the resistor may become uncontrollable and the thermal head may be destroyed due to malfunctions due to noise or circuit failure. was there.

Therefore, the thermal head has conventionally been provided with a protection circuit for protecting the thermal head against abnormal pulse width. FIG. 3 is a diagram showing a conventional protection circuit of this type, in which 1 is a thermal head and 2 is a system microprocessor (hereinafter abbreviated as MPU). The thermal head 1 has a resistor divided into eight blocks,
Each block includes a head driver that heats a resistor to perform printing corresponding to print data. The head driver includes a shift register, a latch circuit, and a driver transistor. Then, the print data for one line serially transferred from the microprocessor 2 as the data signal D and the clock signal C is parallel-converted by the shift register and latched by the latch signal L in the latch circuit. In this state, when the enable signals EN1 to EN8 corresponding to each block are activated, the driver transistor is turned on, the resistor is energized / heated in each block, and the print data latched in the latch circuit is printed.

Each of the enable signals EN1 to EN8 is a one-shot multivibrator (hereinafter referred to as a one-shot circuit).
It is applied to the thermal head 1 through a protection circuit composed of 3 and an AND gate 4. The one-shot circuit 3 is MP
It is triggered when the corresponding pulse signal P1 to P8 from U2 is activated and outputs pulse signals Q1 to Q8 with a constant time width QW. This constant time width QW is a pulse signal from MPU2.
It is selected to be longer than the pulse width PW of P1 to P8 and shorter than the time until the resistor of the thermal head 1 burns out. Then, the pulse signals Q1 to Q8 from these one-shot circuits 3
And the respective logical product outputs of the pulse signals P1 to P8 from the MPU2 become the enable signals EN1 to EN8.

FIG. 4 is a signal timing diagram of this conventional circuit.
The pulse signals P1 to P8 from the MPU2 are sequentially output such that P2 becomes active when P1 becomes inactive,
The pulse signals Q1 to Q8 from the one-shot circuit 3 become active in synchronization with the rising edges of the pulse signals P1 to P8,
It becomes inactive after a certain time width QW. Therefore, as shown by the broken line in FIG. 4, even if the pulse signal P1 continues to be active due to the circuit abnormality of the MPU2 or the like, it is limited to the pulse width QW of the pulse signal Q1 from the one-shot circuit 3. Are protected from burning.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional thermal head protection circuit, a circuit having a timer function such as the one-shot circuit 3 is required for each block, and a large number of blocks are required. The system using the thermal head 1 has a problem such as an increase in size, complexity, and cost of the device. Further, in the case of the one-shot circuit 3, the resistor R and the capacitor C are required for each circuit, which is not suitable for LSI (large-scale integrated circuit).

Therefore, the present invention provides a thermal head protection circuit that can protect a burnout of a heating element with a simple and inexpensive structure even for a thermal head using a large number of blocks, can be downsized, and is suitable for LSI implementation. The purpose is to

[Means for Solving the Problems] According to the present invention, a plurality of heating elements are divided into at least two or more blocks, the enable signals having a constant pulse width are sequentially applied by shifting the timing for each block, and each block is applied. In the protection circuit of the thermal head that prints one line of print data by heating the heating element,
A processor that generates a timing pulse signal that cycles the pulse width of the enable signal and at least two or more output terminals corresponding to each block of the thermal head are provided. One shift register that activates the output signals in order, and a time that is triggered by the pulse input of the timing pulse signal and that is longer than the pulse width of the enable signal and shorter than the time until the heating element burns out, and then activate the output signal during that time. One timer circuit and a shift register are provided for each output terminal of the shift register, and the logical product output of the output signal from the output terminal and the output signal from the timer circuit is enabled to the block corresponding to the output terminal. At least 2 applied to the thermal head as a signal
The above-mentioned AND gate is provided.

[Operation] With the thermal head protection circuit having such a configuration, the output signals from the output terminals of the shift register are sequentially activated in response to the pulse input of the timing pulse signal generated from the processor. The output signal from the timer circuit becomes active. The output signal from each output terminal of the shift register is input to the corresponding AND gate, and the logical product with the output signal from the timer circuit is calculated. Then, the logical product output signal of each logical product gate is applied to the thermal head as an enable signal of each block obtained by dividing each heating element of the thermal head, and printing is performed. Here, the time when the output signal from the timer circuit becomes active is limited to the time longer than the pulse width of the enable signal and shorter than the time until the heating element burns out.

Therefore, the timing pulse signal continues to be active due to the abnormality of the processor, and even if the output signal from the one output terminal of the shift register continues to be active, the output signal from the timer circuit causes the heating element to burn. Since it becomes inactive in a time shorter than the time, the enable signal to the block corresponding to one output terminal of the shift register becomes inactive in synchronization with the output signal from the timer circuit. That is, the thermal head protection circuit having the same function as the conventional one is configured by one shift register, one timer circuit, and the number of AND gates corresponding to the number of blocks of the thermal head.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The thermal head 11 of this embodiment is exactly the same as the conventional one, and the description thereof is omitted here. The MPU 12 has a data sending circuit that serially sends the print data for one line by a data signal D and a clock signal C, a latch generating circuit that outputs a latch signal L, a synchronous pulse generating circuit that generates a synchronous pulse signal S, and timing. A timing pulse generating circuit for generating the pulse signal T is built in. The sync pulse signal is a signal which becomes active in synchronization with the fall of the data signal and is applied to the input terminal SI of the shift register 13. The timing pulse signal T is a pulse signal whose cycle is the pulse width of the enable signals EN1 to EN8 applied to each block of the thermal head 1, and is applied to the clock terminal CK of the shift register 13 at the same time. It is applied to the trigger terminal B of the one-shot circuit 14.

The shift register 13 sequentially shifts the active bits applied to the input terminal SI using the timing pulse signal T as a clock, thereby sequentially activating the outputs of the output terminals QA to QH corresponding to each block of the thermal head 1. The output of the output terminals QA to QH becomes active, which means that the corresponding block of the thermal head 1 is selected. Further, the one-shot circuit 14 is triggered by the rise of the timing pulse signal T, measures a time longer than the timing pulse signal T and shorter than the time when the resistor burns out, and activates the output of the output terminal Q during that time. Is. The AND gate group 15 ANDs the outputs of the output terminals QA to QH of the shift register 13 and the output of the output terminal Q of the one-shot circuit 14, respectively, and outputs the AND outputs of the enable signals EN1 to EN1. As EN8 is applied to each block of the thermal head 11,
Printing is performed.

FIG. 2 is a signal timing diagram in the protection circuit of this embodiment. At time t0, MPU12 to thermal head 1
When the print data for one line per 1 is serially transferred as the data signal D and the clock signal C, the synchronizing signal S from the MPU 12 to the shift register 13 becomes active.
The print data transferred to the thermal head 11 is parallel-converted by the shift register in the thermal head 11 and latched by the latch circuit according to the latch signal L.

In this state, at the time point t1, the timing pulse signal T having the energization time PW for each block as a cycle is changed to the shift register 13
When applied to the clock terminal CK and the trigger terminal B of the one-shot circuit 14, the output terminal QA of the shift register 13 becomes active, and at the same time, the one-shot circuit 14 is triggered and the output terminal Q becomes active. Therefore, the enable signal EN1 that drives the first block, which is the logical product output of both, becomes active and the print data corresponding to this block is printed. After that, time t2
When the next pulse of the timing pulse signal T rises at, the shift register 13 shifts and the output terminal
QA becomes inactive, and output terminal QB becomes active. On the other hand, the output Q of the one-shot circuit 14 is such that the clocking time QW of the one-shot circuit 14 is the period PW of the timing pulse signal T.
Since it is longer than this, it is triggered active and starts timing again. Therefore, enable signal EN1 changes to time t2.
The signal becomes inactive at, and instead, the enable signal EN which is a logical product output of the output of the output terminal QB of the shift register 13 and the output of the output terminal Q of the one-shot circuit 14
2 becomes active and the resistor in the second block generates heat.

Thereafter, similarly, the enable signals EN3, EN4, ... Are sequentially activated, and the heating element is heated in each corresponding block of the thermal head 11 to perform printing.

Now, assuming that the timing pulse signal T becomes abnormal at the time t3 due to the system abnormality of the microprocessor 12 or the like and the inactive state continues where it becomes inactive at the time t4, the shift register 13 does not shift. Therefore, the output terminal QF remains active. On the other hand, in the one-shot circuit 14, at the time point t3, the output terminal Q is held active by being triggered before the time is up, and the output terminal Q becomes inactive when the time count QW elapses. Therefore, the enable signal EN6 becomes active at the time point t3 and becomes inactive at the time point t4, so that there is no possibility that the resistor of the sixth block corresponding to the enable signal EN6 is burned out.

After that, when the timing pulse signal T returns to normal at time t6, the shift register 13 shifts and the one-shot circuit 14 is triggered to activate the enable signal EN7.

As described above, in the present embodiment, the timing pulse signal T having the cycle of the energization time PW of each block in the thermal head 11 is generated, the pulse signal is used as the clock signal of the shift register 13, and the energization time PW The trigger signal of the one-shot circuit 14 that measures a fixed time that is longer than the time at which the resistor burns out, and the active output of the shift register 13 is sequentially triggered in synchronization with the clock signal so that each of the thermal heads 11 is triggered. The blocks are sequentially selected, and a logical product output of the selected output and the time output of the one-shot circuit 14 is used as enable signals EN1 to EN8 of the corresponding block. Therefore, when the timing pulse signal T is normal, the active state of the enable signals EN1 to EN8 is limited by the period PW of this pulse signal T,
When the timing pulse signal T continues to be in the active state, the time period QW of the one-shot circuit 14 limits the active state of the enable signals EN1 to EN8. As a result, the enable signals EN1 to EN8 do not remain in the active state longer than the time period QW of the one-shot circuit 14, so that the resistors corresponding to each block of the thermal head 11 can be protected from burning and the thermal head 11 can be protected. Maintainability can be improved.

Thus, according to this embodiment, one shift register
13, one one-shot circuit 14, and thermal head 11
The number of blocks (8 in this case) and the number of AND gates 15 corresponding to the number of blocks can be combined with each other to reliably protect the thermal head 11 from burning. Simplification, miniaturization, and cost reduction can be achieved. Further, since only one one-shot circuit 14 as an analog element is required, it can be made into an LSI, and this circuit itself does not require a highly accurate one, so that it can be realized at a low cost. Further, since the MPU 12 may output the timing pulse signal T having the pulse width of the enable signal instead of the enable signals EN1 to EN8 of each block from one output terminal, the program configuration for controlling the MPU 12 is also simplified. Can be converted.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the thermal head is divided into 8 blocks is shown, but the number of output terminals of the shift register and the number of AND gates are changed for the thermal head divided into any number of blocks. It is possible to deal with it easily by itself, and it does not cause the circuit to become complicated or large. Further, in the above-described embodiment, the case where a plurality of blocks of the thermal head are sequentially driven one by one has been shown, but it can be applied to a thermal head in which a plurality of blocks are driven at the same time by simply changing the configuration of the shift register. There is no. Further, although the one-shot circuit is used as the circuit having the time counting function in the present embodiment, it goes without saying that the same effect can be obtained even if another circuit having the time counting function is used. In addition, it goes without saying that various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, the processor has one circuit for protecting the heating elements from burnout regardless of the number of blocks into which a large number of heating elements constituting the thermal head are divided. Since the shift register, one timer circuit, and the number of AND gates corresponding to the number of blocks can be used, the structure can be simplified and the cost can be reduced. In addition, miniaturization is possible, and LSI is suitable. Moreover,
Instead of the enable signal for each block, the processor
Since the timing pulse signal having the pulse width of the enable signal as a cycle may be output from one output terminal, the program configuration for controlling the processor can be simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a signal timing diagram of the same embodiment, FIG. 3 is a circuit diagram showing a configuration of a conventional example, and FIG. 4 is a signal of a conventional example. It is a timing diagram. 11 ... Thermal head, 12 ... MPU, 13 ... Shift register, 14 ... One-shot circuit, 15 ... AND gate group.

Claims (1)

[Claims] 1. A plurality of heating elements are divided into at least two or more blocks, and an enable signal having a constant pulse width is sequentially applied to each block by shifting the timing to heat each heating element of each block. In a thermal head protection circuit for printing print data for a line, a processor for generating a timing pulse signal having a pulse width of the enable signal as a cycle, and at least two or more output terminals corresponding to respective blocks of the thermal head are provided. And a shift register that sequentially activates the output signals from the output terminals in response to a pulse input of the timing pulse signal, and a pulse width of the enable signal triggered by the pulse input of the timing pulse signal. Is longer and shorter than the time it takes for the heating element to burn out. And a timer circuit that activates an output signal during that time, and a logical product output of an output signal from the output terminal provided for each output terminal of the shift register and an output signal from the timer circuit. A thermal head protection circuit comprising: at least two AND gates applied to the thermal head as enable signals to the blocks corresponding to output terminals.