JPH0851354A - Pass transistor type selector circuit and logic circuit - Google Patents

Abstract

PURPOSE:To realize a stable operation at high speed. CONSTITUTION:A circuit 4 which individually supplies the two kinds of control signals with phases opposite each other is connected to the gate electrodes of a pair of signal selecting nMOS transistors 1 and 2 with mutually connected drain electrode as an output terminal and the above circuit is provided with means 11 and 12 for generating the control signal and the means for executing an operation synchronously with a clock signal clk and stopping the supply of the control signal to the signal selecting transistors 1 and 2 during a period when the clock signal is at a low level. The supply stop of the control signal is realized, for example, by connecting discharging nMOS transistors 13 and 14 between the control signal generating means 11, 12 and a grounded terminal, and permitting the transistors to be a conductive state during the period when the clock signal is at the low level and discharging the control signal. The output terminal is connected to charging pMOS transistors 7 and 8 and the high level voltage reduced by a threshold value voltage is restored as a power source potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pass transistor type selector circuit and a digital logic circuit constructed by using the circuit.

[0002]

2. Description of the Related Art A pass transistor type selector circuit is constructed by connecting drain electrodes D of a pair of signal selecting nMOS transistors 1 and 2 (pass transistors) to each other, as shown in FIG. By supplying an input signal to the source electrode S of each transistor and a control signal to the gate electrode G, it is possible to function as a two-input exclusive OR circuit [eg, 1985.
Published by Addison-Wesley Publisher “Principles of CMOS VLS
First of "I Design" (co-authored by N. Weste and K. Eshraghian)
See pages 72 to 175].

Since a pass transistor type selector circuit can realize a desired logical function with a small number of elements, it is particularly useful for VLSI (very large scale integration).
In addition to being suitable for the case of, it is possible to use an nMOS transistor having a high operation speed as a signal selection transistor, and thus it has an excellent feature that a high-speed logic circuit can be realized. When the conduction / non-conduction of the pair of signal selection transistors 1 and 2 is switched, there is an unfavorable problem that both transistors are simultaneously conducted and the high speed operation is hindered.

An example of the waveform of the control signal used in the pass transistor type selector circuit is shown in FIG. 9a. First control signal Z (signal supplied to the gate electrode of the transistor 1)
Is high level while the logical value "1" is expressed,
The signal is at a low level during the period in which the logical value "0" is expressed. On the other hand, the second control signal Z ^* (signal supplied to the gate electrode of the transistor 2) is a negative signal obtained by inverting the phase of the first control signal Z, and is low when the first control signal Z is at high level. It is a signal that becomes high level while the signal becomes low and the signal is low level. When one of the control signals makes a transition from high to low, the other control signal makes a transition from low to high at the same time, but during the transition, the signal levels are both constant threshold values. Since there is a period T that exceeds, both transistors 1 and 2 are simultaneously turned on, although temporarily. When this phenomenon occurs, the two input signals supplied to the source electrode S pass through both the transistors 1 and 2 and the drain electrode D
As a result of collision on the side (output terminal), stabilization of the circuit is delayed,
It causes high speed operation obstruction. The same phenomenon occurs when the phase of one control signal is inverted by the inverter circuit and used as the other control signal. This is because the delay time due to the inverter circuit delays the timing at which the other phase-inverted control signal changes from the high level to the low level, during which both transistors 1 and 2 are simultaneously turned on.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pass transistor type selector circuit which can solve the above-mentioned problems of the prior art and realize a high speed and stable operation, and the selector circuit. It is to provide a novel digital logic circuit used.

[0006]

The object of the present invention is to operate in synchronism with a clock signal and to stop the supply of a control signal to a signal selecting transistor during the period when the signal is at a low level. Can be solved by providing. To stop the supply of the control signal, for example, a discharging nMOS transistor is connected between the control signal generating means and the ground terminal, and the transistor is made conductive during the period when the clock signal is at the low level to discharge the control signal. The control signal supply circuit including the interrupting means of this kind will be described in detail later with reference to an embodiment.
Known Domino type logic circuits (pages 168 to 1 of the above document)
(See page 69) and the like.

[0007]

By discharging the control signal during the period when the clock signal is at the low level, the waveform of the control signal is as shown in FIG.
It changes as shown in b. Only when the control signals change from the high level to the low level, the transitions of the both control signals are shifted in the directions indicated by the arrows in the figure, and the waveforms of the alternate long and short dash line become the waveforms of the solid line. This shift is about the time of the low level period of the clock signal. The transition from the low level to the high level of the signal is not lost and remains unchanged. Therefore, it is possible to eliminate the time T existing between the control signals that are inverted with each other, and avoid the inconvenience that both transistors are simultaneously turned on and the input signals collide. This ensures high-speed operation of the selector circuit.

The control signal generating / supplying circuit includes an inverter circuit which has means for charging the output terminal thereof while the clock signal is at a low level and inverts the output signal of the terminal to obtain a control signal. Is desirable. This is because the discharging nMOS transistor forming the inverter circuit is in a conductive state while the clock signal is at the low level, and the control signal can be discharged.

It is desirable to connect a voltage compensating pMOS transistor between the output terminal of the signal selecting transistor and the power supply terminal. The high level of the signal at the output terminal
This is because it is possible to avoid the problem that the threshold voltage of the transistor is lowered. That is, when the control signal supplied to the gate electrode of the signal selection transistor and the input signal supplied to the source electrode are both at high level, the output signal becomes high level, but the MOS transistor has a threshold voltage, The high-level potential of the output signal decreases by that amount. When the selector circuits are used in a cascade connection, the amount of voltage drop is accumulated and the amount of voltage drop is large, and a through current may flow to the next stage that is in a non-conducting state, resulting in an increase in power consumption. The voltage compensating pMOS transistor operates in synchronization with the clock signal, and is conductive during the low level period of the signal to restore the potential of the output terminal to the power supply voltage.

By using a plurality of the selector circuits described above,
It is desirable to connect a circuit for forming a logical operation circuit network and supplying a necessary input signal to the circuit network to the source electrode of the signal selection transistor of each selector circuit. A desired logical operation can be performed.

A circuit for supplying a control signal to the signal selecting transistor of the selector circuit forming the logical operation circuit network can be formed by combining a plurality of the above selector circuits. A highly functional logical operation circuit network can be realized.

A circuit for supplying an input signal connected to the source electrode of the signal selecting transistor will be described in detail later with reference to an embodiment. For example, a known dynamic logic circuit (see the above-mentioned document). (See page 168, 169) and the like. Connect a charging pMOS transistor to the power supply side of the logic circuit,
While the clock signal is at low level, the same charging pMOS
It is desirable for the transistor to conduct and charge the input signal generating means. The input signal becomes high level while the clock signal is low level, while the gate electrode of the signal selecting transistor maintains low level as described above during the same period. This is because the operation of the signal selection transistor can be made stable and reliable. Since charging is performed while the clock signal is at the low level, the input signal can be a signal that transits from the low level to the high level only by the clock signal. With this, it is possible to avoid the transition from the low level to the high level of the input signal, which occurs during the period when the clock signal is at the high level, which causes the malfunction of the signal selecting transistor.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The pass transistor type selector circuit and logic circuit according to the present invention will be described below in more detail with reference to some embodiments shown in the drawings. Note that the same symbols in FIGS. 1, 3 and 5 to 7 indicate the same or similar items.

<Embodiment 1> In FIG. 1, reference numerals 1 and 2 designate a pair of signal selecting nMOs of a pass transistor type selector circuit.
S transistor, 3 is an output terminal in which drain electrodes of the same transistor are connected to each other, 4 is a control signal supply circuit configured by a domino type circuit, 5 and 6 are inverter circuits, 7,
8, 17, 18 are pMOS transistors for charging, 11,
Reference numeral 12 is an nMOS logic circuit network of a domino type logic circuit used as control signal generating means, 15 is a pMOS transistor for voltage compensation, 16 is an input signal supply circuit using a dynamic type circuit, and 21 and 22 are used as input signal generating means. 3 shows an nMOS logic circuit network of a dynamic logic circuit that operates.

The output terminals of the inverter circuits 5 and 6 are connected to the gate electrodes of the signal selecting nMOS transistors 1 and 2. PMO for charging the input terminals of the inverter circuits 5 and 6
The drain electrodes of the S transistors 7 and 8 are connected to one output terminals 9 and 10 of the nMOS logic networks 11 and 12 of the domino type logic circuit used as the control signal generating means.
Thereby, the nMOS transistors 1 and 2 for signal selection
The output signals of the nMOS logic circuits 11 and 12 are inverted and supplied to the gate electrode of the control signal. nMOS
The logic networks 11 and 12 generate logic signals having mutually opposite phases.

The inverter circuits 5 and 6 are, as shown in FIG. 2, composed of a discharging nMOS transistor 24 and a charging pMOS.
Using the transistor 25, the gate electrodes are connected to each other to form the input terminal 23, and the drain electrodes are connected to each other to form the output terminal 26. The source electrode of the discharging nMOS transistor 24 is grounded, and the source electrode of the charging pMOS transistor 25 is connected to the power supply terminal. When the signal at the input terminal 23 is at a high level, the discharging nMOS transistor 24 becomes conductive, and the electric charge accumulated in the electric capacitance at the output terminal 26 is discharged to the ground. As a result, the output terminal 2
6 goes low. Electrical capacity is nM for signal selection
It is formed by the gate capacitance of the gate electrodes of the OS transistors 1 and 2, the junction capacitance of the drain electrodes of the discharge nMOS transistor 24 and the charging pMOS transistor 25, and the floating capacitance of the wiring. Further, when the signal at the input terminal 23 is at low level, the charging pMOS transistor 25 becomes conductive, charges the electric capacity of the output terminal 26, and the output terminal 26 becomes high level.

The clock signal clk is supplied to the gate electrodes of the charging pMOS transistors 7 and 8 and the source electrodes are connected to the power supply terminals. While the clock signal clk is at the low level, the charging pMOS transistors 7 and 8 are in the conducting state, and the discharging nMOS transistors 13 and 14 connected to the other output terminals of the nMOS logic networks 11 and 12 are in the non-conducting state. Then, the output terminals 9 and 10 are opened. Therefore, the charging pMOS transistors 7 and 8 are connected to the output terminal 9,
The electric capacity of 10 is charged, and the output terminals 9 and 10 are set to high level.

Subsequently, when the clock signal clk becomes high level, the charging pMOS transistors 7 and 8 become non-conductive, the discharging nMOS transistors 13 and 14 become conductive, and the nMOS logic networks 11 and 12 are formed. The other output terminal of is grounded. On the other hand, the nMOS logic circuit network 1
1 and 12 are clock signals clk according to the logical operation result.
Becomes high level, the two output terminals are made non-conductive or conductive. As a result, the output terminals 9 and 10
Holds the electric charge charged to its electric capacity and stays at the high level (when there is no conduction between both output terminals), or discharges the same electric charge and becomes the low level. (When both output terminals are in a conductive state). Here, the fact that the clock signal remains at the high level is nothing but because the clock signal precedes during the period of the low level and becomes the high level due to charging. nMO
Since the S logic networks 11 and 12 generate logic signals having mutually opposite phases, for example, when the nMOS logic network 11 becomes non-conductive, the nMOS logic network 12 becomes conductive,
The output terminal 9 becomes high level and the output terminal 10 becomes low level. This output terminal 9 is preceded by the clock signal by about the time of the low level period of the clock signal,
It is at a high level. That is, when the output terminal 10 becomes low level, the output terminal 9 precedes to high level and a time lag occurs between them. Therefore, the inverted control signal is as shown in FIG. When the output terminal 9 goes low and the output terminal 10 goes high, the output terminal 10 goes high first. As described above, it is possible to avoid the inconvenience that the pair of signal selecting nMOS transistors 1 and 2 are turned on at the same time and the input signals collide, and the high speed operation of the selector circuit can be ensured.

If the nMOS logic circuit network 11 or 12 may change from conducting to non-conducting in the middle of the high level period of the clock signal clk, the terminal 9
Or, 10 should maintain the high level, but the level is lowered due to discharge, which may cause a malfunction. In order to prevent such inconvenience, the nMOS logic circuit network 11,
The state of the input signal to 12 must be completed at least until the clock signal clk becomes high level. The circuit of FIG. 3 is a waveform shaping circuit adopted to obtain such an input signal. An input signal is applied to the terminal 27 so that the flip-flop circuit 28 determines the state when the clock signal clk goes high. The signal is changed to the cycle low level and output to the terminal 29.

Next, the voltage compensating pMOS transistor 15 is connected to the output terminals 3 of the signal selecting nMOS transistors 1 and 2. The clock signal clk is supplied to the base electrode, and the source electrode is connected to the power supply terminal. While the clock signal clk is at a low level, the voltage compensating pMOS transistor 15 conducts to charge the output terminal 3 and maintain the level of the signal selecting transistors 1 and 2 lower by the threshold voltage at the power supply potential. To do.

In addition, the signal selection nMOS transistor 1
To the source electrode of the nMOS logic circuit network 21 of the dynamic logic circuit used as the input signal generating means, and the source electrode of the signal selecting nMOS transistor 2 is connected to one of the nMOS logic circuit networks 22. The output terminal 20 of is connected through a buffer circuit having a large driving force. As a result, the nMOS logic circuits 21 and 2 are
2 output signals are signal selection nMOS transistors 1 and 2.
Is supplied as an input signal to both source electrodes. The charging pMOS transistor 1 is connected to the output terminals 19 and 20.
The drain electrodes of 7 and 18 are connected. The clock signal clk is supplied to the gate electrode of the transistor and the source electrode is connected to the power supply terminal. While the clock signal clk is at the low level, the charging pMOS transistors 17 and 18 become conductive, charge the electric capacitances of the output terminals 19 and 20, and set the output terminals 19 and 20 to the high level.

Subsequently, while the clock signal clk is at the high level, the charging pMOS transistors 17 and 18 are rendered non-conductive, while the nMOS logic circuit networks 21 and 22 output their output terminals in accordance with the result of the logical operation. It is made non-conducting or conducting between. As a result, the output terminals 19 and 20 either hold the electric charge charged in the electric capacitance and remain at the high level, or discharge the electric charge and become the low level. As the input signal to the nMOS logic circuit networks 21 and 22, the signal passed through the circuit of FIG. 3 is used. As a result, the signals at the output terminals 19 and 20 are clock signals.
When clk is low level, it goes high every cycle, and when the clock signal clk goes high nM
It goes low according to the result of the logical operation of the OS logic circuits 21 and 22. Therefore, the input signal to the signal selecting nMOS transistors 1 and 2 becomes a signal synchronized with the clock signal clk as well as the control signal, and the clock signal clk
In the middle of the period when k is at the high level, the signal is such that the level does not fall accidentally. As a result, the malfunction of the signal selecting nMOS transistors 1 and 2 can be avoided and the operation can be ensured.

In this embodiment, specifically, the signals A,
B, C, D and their negation signals A ^* , B ^* , C ^* , D ^* are given, and the logical product A∧B of A and B (hereinafter, the logical product operation is ∧
, And a logical sum C∨D of C and D (hereinafter, the logical sum operation is represented by ∨). The two control signals are A∧B and its negation (A∧B) ^* . Actually, using a power supply voltage of 2.5V, as shown in FIG. 4, the low potential level is 0V, the high potential level is + 2.5V,
It was confirmed that the signal F was stably obtained by using the same clock signal with the repetition frequency of 400 MHz, the period of the low potential level and the period of the high potential level being 1.25 ns.

<Embodiment 2> In FIG. 5, reference numeral 30 is a control signal supply circuit constituted by the pass transistor type selector circuit of the present invention, 31 is an input signal supply circuit utilizing a dynamic logic circuit, and 32 and 33 are. , NMOS logic circuit networks 1a and 2a of the dynamic logic circuit used as the input signal generating means are signal selection nMOS transistors which have the same configuration as the signal selection nMOS transistors 1 and 2 and which output logic signals of opposite phases. .

The control signal supply circuit 30 basically has the same configuration as that of the first embodiment, but uses two sets of selector circuits in which the connection to the source electrode is inverted, and the signal F and the inverted signal F are used. Output ^* . This control signal is used for signal selection n
It is supplied to the gate electrodes of the MOS transistors 1, 2, 1a and 2a. N for signal selection in the control signal supply circuit 30
A voltage compensating pMOS is connected to the output terminal of the MOS transistor.
After connecting the transistor, through the inverter circuit,
The control signal is output. The inverter circuit is of the same type as the inverter circuits 5 and 6 described above.
The S-transistor interrupts and discharges the signal, and the charging pMOS transistor charges.

Output terminals of the signal selection nMOS transistors 1 and 2, and signal selection nMOS transistors 1a,
A voltage compensating pMOS transistor is connected to each of the output terminals of 2a to restore the high level lowered by the threshold voltage to the level of the power supply voltage.

Signal selection nMOS transistors 1, 2,
An input signal supply circuit 31 using a dynamic logic circuit is connected to the source electrodes 1a and 2a as in the first embodiment. However, the buffer circuit used in one dynamic logic circuit of the first embodiment is excluded. A charging pMOS transistor is connected to the output terminals of the nMOS logic networks 32 and 33. As the input signal to the nMOS logic circuit networks 32 and 33, the signal that has passed through the waveform shaping circuit of FIG. 3 is used.

In this embodiment, specifically, the first embodiment
In addition to the above case, signals G, H, G ^* , and H ^* are newly given to obtain an exclusive OR E of F and a logical product G∧H of G and H and its negation E ^* . Also in this embodiment, 2.5
Using the power supply voltage of V, the low potential level shown in FIG.
V, high potential level + 2.5V, repetition frequency 40
0 MHz, a low potential level period and a high potential level period are equal to 1.25 ns.
It was confirmed that E and E ^* were stably obtained.

<Third Embodiment> In FIG. 6, reference numeral 34 is a control signal supply circuit using a domino type logic circuit, and 35 and 36.
Is an nMOS logic circuit network of a domino type logic circuit used as control signal generating means, 37 is an input signal supply circuit constituted by the pass transistor type selector circuit of the present invention, and 38 and 39 are buffer circuits.

The control signal supply circuit 34 is a circuit utilizing a domino type logic circuit having the same configuration as that of the first embodiment, and nMOS logic circuit networks 35 and 36 used as control signal generating means.
To the same signal G, H, G ^* , H ^* as in the second embodiment,
It is possible to obtain control signals of G∧H and its negation (G∧H) ^* . This is a signal selection nMOS transistor 1,
Supply to the gate electrodes 2, 1a and 2a.

NMOS transistors 1 and 2 for signal selection,
And the output terminals of 1a and 2a have pMs for voltage compensation, respectively.
Connect the OS transistor.

NMOS transistors 1 and 2 for signal selection,
An input signal supply circuit 37 of a pass transistor type selector circuit is connected to the source electrodes of 1 and 2a. This circuit is the same type of circuit as that used as the control signal supply circuit 30 in the second embodiment, but the inverter circuits are replaced with buffer circuits 38 and 39. Input signal supply circuit 37
Are the same signals F and F ^* as those in the second embodiment,
It is output as an input signal to the OS transistors 1 and 2 and 1a and 2a. In the present embodiment, with the above configuration, the exclusive OR of the signals F and G∧H is calculated, and the same signals E and E ^* as in the second embodiment are obtained. Also in this embodiment, 2.5V
, The low potential level is 0 V, as shown in FIG.
High potential level is + 2.5V, repetition frequency is 400M
It can be confirmed that the signals E and E ^* can be stably obtained by using the clock signal in which the period of Hz, the period of the low potential level and the period of the high potential level are equal to each other at 1.25 ns.

As an application example based on the above embodiment, a 4: 2 compressor circuit is constructed. The 4: 2 compressor circuit serves as a basic unit (adder array) of the multiplier, one block of which is shown at 40 in FIG. The block is a logical operation circuit that adds 4-bit input and outputs 2-bit. The 4-bit input signal is X ₁ , X ₂ , X ₃ and X ₄ , and the 2-bit addition result is S and C. In particular, C is the addition result of one digit higher. The carry signal to the digit one digit higher is Co, and the carry signal from the digit one digit lower is Ci.

In this application example, a pair of signal selecting n
Four combinations of pass transistor type selector circuits each including a MOS transistor as a pair were used. Also in this application example, it was confirmed that high-speed signals synchronized with the clock signal having the repetition frequency of 400 MHz were stably obtained.

[0035]

According to the present invention, in the pass transistor type selector circuit and the logic circuit in which a plurality of them are combined, it is possible to shift the level transition time between the control signals having mutually inverted phases. As a result, collision of signals is avoided in the operation of the signal selection nMOS transistor, and high-speed operation of the circuit can be ensured. Further, it is possible to eliminate the decrease in the level of the output signal which is decreased by the threshold voltage, and further to avoid the malfunction that may occur during the high level period of the clock signal, and to realize the stable operation of the circuit. As described above, the circuit of the present invention is suitable for a large-scale integrated circuit that makes use of the feature that the pass transistor type selector circuit has a small circuit scale.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a first embodiment of a MOS transistor logic circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of an inverter circuit.

FIG. 3 is a circuit diagram for explaining the configuration of a circuit used to shape the waveform of a signal from the outside.

FIG. 4 is a circuit diagram for explaining a clock signal used in this embodiment.

FIG. 5 is a circuit diagram for explaining a second embodiment of the MOS transistor logic circuit according to the present invention.

FIG. 6 is a circuit diagram for explaining a third embodiment of a MOS transistor logic circuit according to the present invention.

FIG. 7 is a circuit diagram for explaining an application example of a MOS transistor logic circuit according to the present invention.

FIG. 8 is a circuit diagram for explaining a conventional pass transistor type selector circuit.

FIG. 9 is a signal waveform diagram for explaining conventional control signals and control signals by the control signal generation circuit of the present invention.

[Explanation of symbols]

1, 2, 1a, 2a ... Signal selection nMOS transistor 3 ... Output terminal of pass transistor type selector circuit 4, 30, 34 ... Control signal supply circuit 5, 6 ... Inverter circuit 7, 8, 17, 18 ... Charging pMOS Transistors 9, 10 ... One output terminal of nMOS logic circuit network using domino type logic circuit 11, 12, 35, 36 ... nMOS logic circuit network 13, 14 of domino type logic circuit used as control signal generating means NMOS transistor for discharge 15 ... pMOS transistor for voltage compensation 16, 31, 37 ... Input signal supply circuit 19, 20 ... nM using dynamic logic circuit
OS logic circuit network output terminals 21, 22, 32, 33 ... nMOS logic circuit network of dynamic type logic circuit used as input signal generating means 23 ... Inverter circuit input terminal 24 ... Inverter circuit discharging nMOS transistor 25 ... Inverter Circuit charging pMOS transistor 26 ... Inverter circuit output terminal 27 ... Waveform shaping circuit input terminal 28 ... Waveform shaping circuit flip-flop circuit 29 ... Waveform shaping circuit output terminal 38, 39 ... Buffer circuit 40 ... 4: 2 Compressor 1 block of circuit

Claims (13)

[Claims] 1. A pair of signal selecting n having drain electrodes connected to each other as output terminals and each source electrode as input terminals.
A MOS transistor and at least a circuit for individually supplying two types of control signals having opposite phases to the gate electrode of the transistor are provided, and the control signal supply circuit supplies means for generating a control signal and supply of the control signal. The control signal connecting / disconnecting means of the latter operates in synchronization with the clock signal, and supplies the control signal to the signal selecting transistor during the period when the signal is at the low level. A pass-transistor type selector circuit, which is characterized in that 2. The control signal connecting / disconnecting means comprises a discharging nMOS transistor connected between the control signal generating means and a ground terminal, and the transistor has a clock signal at a low level. 2. The pass transistor type selector circuit according to claim 1, wherein the pass transistor type selector circuit is configured to be conductive during the period to discharge the control signal. 3. The control signal supply circuit includes means for charging the control signal generating means, in addition to the control signal generating means and the control signal interrupting means, and the charging means includes: It operates in synchronization with the clock signal,
3. The pass transistor type selector circuit according to claim 1, wherein the pass transistor type selector circuit functions to charge the control signal generating means during a period when the signal is at a low level. 4. The charging means comprises a charging pMOS transistor connected between the control signal generating means and a power supply terminal, and the transistor is provided during a period when a clock signal is at a low level. 4. The pass transistor type selector circuit according to claim 3, wherein the pass transistor type selector circuit is configured to be conductive so as to charge the control signal generating means. 5. A pair of signal selecting n having drain electrodes connected to each other as output terminals and each source electrode as input terminals.
A pass transistor type selector circuit including a MOS transistor and a circuit for individually supplying two types of control signals of opposite phases to the gate electrode of the transistor, wherein the control signal supply circuit comprises a domino type logic circuit. Thus, the nMOS logic circuit network of the same logic circuit is used as the control signal generating means, and the charging pMOS transistor connected to the power supply side of the same logic circuit is used as the charging means of the control signal generating means. A pass transistor type selector circuit characterized in that a discharging nMOS transistor connected to the ground side of is used as a discharging means of the control signal generating means. 6. The charging pMOS transistor operates in synchronization with a clock signal and functions to charge the control signal generating means by conducting during a period in which the signal is at a low level. The discharge nMOS transistor operates in synchronization with a clock signal and conducts to discharge a control signal while the signal is at a low level. 5. A pass transistor type selector circuit according to item 5. 7. The control signal supply circuit includes an inverter circuit connected to the output terminal side thereof, and the circuit inverts the phase of the output signal of the control signal generation means, and then outputs the inverted signal to the control signal. The pass transistor type selector circuit according to any one of claims 1 to 6, wherein the pass transistor type selector circuit functions as supplying a signal to the signal selecting transistor. 8. A voltage compensating pMOS transistor is connected between an output terminal and a power supply terminal of the signal selecting transistor, the transistor operating in synchronization with a clock signal, and the signal is low. 8. The device functions as conducting during a period of being at a level so as to restore the potential of the output terminal of the signal selection transistor to the power supply voltage. Pass transistor type selector circuit. 9. A desired logical operation circuit network is constructed by using one or a plurality of selector circuits according to any one of claims 1 to 8 and is required for the circuit network. A pass transistor type logic circuit characterized in that a circuit for supplying an input signal is connected to a source electrode of a signal selecting transistor of each selector circuit. 10. A circuit for supplying a control signal to a signal selecting transistor of the selector circuit which constitutes a logical operation circuit network, comprises a plurality of selector circuits according to any one of claims 1 to 8. 10. The pass transistor type logic circuit according to claim 9, wherein the pass transistor type logic circuit is configured by combining them. 11. A circuit for supplying an input signal connected to a source electrode of a signal selecting transistor of a selector circuit according to claim 1, comprising a dynamic logic circuit. A pass transistor characterized by using an nMOS logic circuit network of the same logic circuit as an input signal generating means and using a charging pMOS transistor connected to a power supply side of the same logic circuit as a charging means of the input signal generating means. Type selector circuit. 12. The charging pMOS transistor according to claim 11 operates in synchronization with a clock signal, and conducts during the period when the clock signal is at a low level to charge the input signal generating means. 12. The pass transistor type selector circuit according to claim 11, which functions, and becomes non-conductive during a period in which the clock signal is at a high level to open the input signal generation means. 13. A circuit for supplying an input signal to a signal selecting transistor of the selector circuit which constitutes a logical operation circuit network, according to any one of claims 1 to 8, claim 11 and claim 12. 11. The pass transistor type logic circuit according to claim 9 or 10, which is configured by combining a plurality of the selector circuits according to claim 9.