JPH0851117A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0851117A
JPH0851117A JP18734094A JP18734094A JPH0851117A JP H0851117 A JPH0851117 A JP H0851117A JP 18734094 A JP18734094 A JP 18734094A JP 18734094 A JP18734094 A JP 18734094A JP H0851117 A JPH0851117 A JP H0851117A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
semiconductor substrate
impurity concentration
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18734094A
Other languages
Japanese (ja)
Inventor
Kazufumi Shimauchi
一文 島内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP18734094A priority Critical patent/JPH0851117A/en
Publication of JPH0851117A publication Critical patent/JPH0851117A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a semiconductor device having high breakdown voltage and excellent characteristics by improving the junction breakdown voltage between the well and an element isolation region of an IC, and eliminating the influence of the substrate resistance of a semiconductor substrate to a ground electrode. CONSTITUTION:A one conductivity type epitaxially grown layer having different conductivity type of a semiconductor substrate 1 is formed on a semiconductor substrate 1, and an element isolation region 3 reaching the substrate 1 is formed on the grown layer thereby to form a plurality of wells 2 partitioned by the region 3 and the substrate 2, semiconductor elements are respectively formed at the wells 2, and an electrode 12 is formed on the rear surface of the substrate 1 in a semiconductor device. The impurity concentration of a predetermined thickness of the grown layer side of the substrate 1 is smaller than that of the grown layer, and the impurity concentration of the residual part of the substrate is formed higher than that of the grown layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はICやLSIなどの複数
個の素子を有する半導体装置に関する。さらに詳しく
は、半導体基板の裏面を接地するICなどでウェルと半
導体基板間の耐圧を向上し、かつ、動作特性を低下させ
ない半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of elements such as IC and LSI. More specifically, the present invention relates to a semiconductor device that improves the breakdown voltage between the well and the semiconductor substrate and does not deteriorate the operating characteristics, such as an IC that grounds the back surface of the semiconductor substrate.

【0002】[0002]

【従来の技術】従来、パワートランジスタなど個別半導
体ではpn接合部の耐圧向上策が種々施されている。た
とえば、トランジスタのベース領域とコレクタ領域のp
n接合では曲率部や半導体層表面でのpn接合がとくに
耐圧に弱く、曲率部ではコレクタ領域の不純物濃度を薄
くすることにより空乏層を拡げたり、半導体層表面のベ
ース領域の周囲に隣接してベース領域と同じ導電型でベ
ース領域と電気的に独立したフィールド リミッティン
グ リング(FLR)を設け、半導体層表面での空乏層
の端部がフィールド リミッティング リングを迂回し
てベース領域から遠ざかるようにすることにより耐圧を
向上させている。
2. Description of the Related Art Conventionally, various measures for improving the breakdown voltage of a pn junction have been taken in individual semiconductors such as power transistors. For example, p in the base region and collector region of the transistor
In the n-junction, the pn junction at the curved portion and the semiconductor layer surface is particularly weak against breakdown voltage, and at the curved portion, the depletion layer is expanded by reducing the impurity concentration in the collector region, or adjacent to the periphery of the base region on the semiconductor layer surface. A field limiting ring (FLR) that has the same conductivity type as the base region and is electrically independent of the base region is provided so that the end of the depletion layer on the semiconductor layer surface bypasses the field limiting ring and moves away from the base region. By doing so, the breakdown voltage is improved.

【0003】一方ICにおいても、複雑な機械や精密機
器に用いられるのに伴って、従来の35〜50Vの耐圧
から200Vあるいは300V程度の高耐圧が要求され
てきている。通常のICは図4に断面図で一素子部が示
されているように、p型半導体基板21上に設けられた
エピタキシャル成長層を素子分離領域(アイソレーショ
ン)3で分離してウェル2を形成し、各ウェル2内に設
けられたベース領域4、エミッタ領域5、コンタクト領
域6からなるトランジスタなどの各半導体素子が形成さ
れる。なお、7はコレクタ領域の抵抗を低減するための
埋込層で、設けられないばあいもある。また、8、9、
10はそれぞれコレクタ電極、ベース電極、エミッタ電
極で、11、12はそれぞれアース電極、13は空乏層
の拡がりである。
On the other hand, ICs are also required to have a high withstand voltage of about 200V or 300V from the conventional withstand voltage of 35 to 50V as they are used in complicated machines and precision equipment. An ordinary IC has a well 2 formed by separating an epitaxial growth layer provided on a p-type semiconductor substrate 21 by an element isolation region (isolation) 3 as shown in a sectional view of FIG. Then, each semiconductor element such as a transistor including the base region 4, the emitter region 5 and the contact region 6 provided in each well 2 is formed. Reference numeral 7 is a buried layer for reducing the resistance of the collector region, which may not be provided. Also, 8, 9,
10 is a collector electrode, a base electrode, and an emitter electrode, 11 and 12 are earth electrodes, and 13 is a depletion layer spread.

【0004】このような構造のICで、前述のように高
耐圧のものが要求されると、ウェル2内に形成される各
素子の耐圧、たとえばコレクタベース間耐圧BVCBO
コレクタエミッタ間耐圧BVCEO もさることながら、ウ
ェル2と素子分離領域3間の耐圧を大きくする必要があ
る。前記トランジスタの各耐圧と素子分離領域3との接
合耐圧BVISO とのあいだには一般につぎの関係があ
る。
When an IC having such a structure is required to have a high breakdown voltage as described above, the breakdown voltage of each element formed in the well 2, for example, the collector-base breakdown voltage BV CBO and the collector-emitter breakdown voltage BV. It is necessary to increase the breakdown voltage between the well 2 and the element isolation region 3 as well as the CEO . Generally, the following relationship exists between each breakdown voltage of the transistor and the junction breakdown voltage BV ISO of the element isolation region 3.

【0005】 BVCEO <BVCBO <BVISO (1) pn接合の耐圧を上げるためには、pn接合の空乏層が
形成される部分の不純物濃度を下げることが空乏層が拡
がるため効果的で一般に行われている。そのため(1)
式より半導体基板を含めた素子分離領域接合での耐圧を
上げるためには、ベース領域4よりエピタキシャル成長
層を、エピタキシャル成長層より半導体基板の不純物濃
度を低くすることが必要となる。
BV CEO <BV CBO <BV ISO (1) In order to increase the breakdown voltage of the pn junction, it is effective to lower the impurity concentration in the portion of the pn junction where the depletion layer is formed, because the depletion layer expands, and is generally Has been done. Therefore (1)
From the equation, in order to increase the breakdown voltage in the element isolation region junction including the semiconductor substrate, it is necessary to lower the impurity concentration of the epitaxial growth layer than the base region 4 and the impurity concentration of the semiconductor substrate than the epitaxial growth layer.

【0006】[0006]

【発明が解決しようとする課題】しかしICでは半導体
基板21の裏面に電極12を設けてリードフレームなど
に直接ボンディングし、基板21の裏面側をアース電極
として使用されており、半導体基板の不純物濃度が低く
なると基板抵抗RSUB が直列に挿入されたことになり、
これが寄生抵抗となってIC全体としての特性が低下す
るばあいがある。しかも半導体基板21の厚さはエピタ
キシャル成長層(ウェル2)である実効層の厚さdの5
〜7倍以上であり、また、半導体基板21は不純物濃度
の均一なものが使用されるため、不純物濃度を低下させ
ることによる半導体基板21の基板抵抗RSUB は深刻な
問題となり、耐圧の向上とICの特性維持という相反す
る問題を有している。
However, in the IC, the electrode 12 is provided on the back surface of the semiconductor substrate 21 and is directly bonded to a lead frame or the like, and the back surface side of the substrate 21 is used as a ground electrode. When becomes lower, it means that the substrate resistance R SUB is inserted in series.
This may become a parasitic resistance and deteriorate the characteristics of the IC as a whole. Moreover, the thickness of the semiconductor substrate 21 is 5 which is the thickness d of the effective layer which is the epitaxial growth layer (well 2).
.About.7 times or more, and since the semiconductor substrate 21 having a uniform impurity concentration is used, the substrate resistance R SUB of the semiconductor substrate 21 due to the reduction of the impurity concentration becomes a serious problem, and the breakdown voltage is improved. It has the conflicting problem of maintaining the characteristics of ICs.

【0007】本発明はこのような問題を解決し、ICの
ウェルと素子分離領域間の接合耐圧を向上させるととも
に、アース電極に至る半導体基板の基板抵抗の影響をな
くし、高耐圧で高特性の半導体装置を提供することを目
的とする。
The present invention solves such a problem, improves the junction breakdown voltage between the IC well and the element isolation region, eliminates the influence of the substrate resistance of the semiconductor substrate reaching the ground electrode, and has a high breakdown voltage and high characteristics. An object is to provide a semiconductor device.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に該半導体基板の導電型と異なる導電型の
エピタキシャル成長層が形成され、該エピタキシャル成
長層に前記半導体基板に達する素子分離領域が形成され
ることにより該素子分離領域と半導体基板で区画された
ウェルが複数個形成され、該ウェルの各々に半導体素子
が形成され、前記半導体基板の裏面に電極が形成されて
なる半導体装置であって、前記半導体基板のエピタキシ
ャル成長層側の所定厚さの不純物濃度は前記エピタキシ
ャル成長層の不純物濃度より低く、かつ、前記半導体基
板の残余の部分の不純物濃度は前記エピタキシャル成長
層の不純物濃度より高く形成されている。
According to the present invention, there is provided a semiconductor device comprising:
An epitaxial growth layer having a conductivity type different from that of the semiconductor substrate is formed on the semiconductor substrate, and an element isolation region reaching the semiconductor substrate is formed in the epitaxial growth layer, so that the element isolation region is separated from the semiconductor substrate. A semiconductor device comprising a plurality of wells, a semiconductor element formed in each well, and an electrode formed on the back surface of the semiconductor substrate, wherein an impurity concentration of a predetermined thickness on the epitaxial growth layer side of the semiconductor substrate. Is lower than the impurity concentration of the epitaxial growth layer, and the impurity concentration of the remaining portion of the semiconductor substrate is higher than the impurity concentration of the epitaxial growth layer.

【0009】前記不純物濃度が低い半導体層の不純物濃
度が1014〜1016/cm3 で、その厚さが5〜30μ
mであることが、100〜200V以上の高耐圧をうる
のに好ましい。
The semiconductor layer having a low impurity concentration has an impurity concentration of 10 14 to 10 16 / cm 3 and a thickness of 5 to 30 μm.
It is preferable that m is to obtain a high breakdown voltage of 100 to 200 V or more.

【0010】[0010]

【作用】本発明によれば、半導体基板のエピタキシャル
成長層側の表面の不純物濃度をエピタキシャル成長層の
不純物濃度より低くしているため、エピタキシャル成長
層により形成されたウェルと素子分離領域とのあいだの
pn接合の空乏層は広がり耐圧が向上する。一方半導体
基板における不純物濃度の低い領域は接合部の所定厚さ
だけで、残余部分は全て不純物濃度が高く形成されてい
るため、比抵抗は非常に小さくなり、半導体基板の裏面
をアース電極としても基板抵抗をほとんど無視すること
ができ、ICとしての特性を劣化させることはない。
According to the present invention, since the impurity concentration of the surface of the semiconductor substrate on the epitaxial growth layer side is set lower than that of the epitaxial growth layer, the pn junction between the well formed by the epitaxial growth layer and the element isolation region is formed. The depletion layer spreads and the breakdown voltage is improved. On the other hand, the region where the impurity concentration is low in the semiconductor substrate is formed to have only the predetermined thickness of the junction and the remaining portion is formed to have a high impurity concentration. Substrate resistance can be almost ignored, and characteristics as an IC are not deteriorated.

【0011】[0011]

【実施例】つぎに添付図面に基づいて本発明の半導体装
置を説明する。
The semiconductor device of the present invention will be described below with reference to the accompanying drawings.

【0012】図1は本発明の半導体装置の一実施例を示
す断面説明図、図2は図1における半導体基板の一製法
を示す説明図、図3は図1における半導体基板の他の製
法を示す説明図である。
FIG. 1 is an explanatory sectional view showing an embodiment of a semiconductor device of the present invention, FIG. 2 is an explanatory view showing one manufacturing method of the semiconductor substrate shown in FIG. 1, and FIG. 3 is another manufacturing method of the semiconductor substrate shown in FIG. It is an explanatory view shown.

【0013】本発明の半導体装置は、たとえば不純物濃
度が1017〜1018/cm3 程度で不純物濃度が高いp
++型の高濃度の半導体層1aと、該半導体層の表面側
に、不純物濃度が1014〜1016/cm3 程度で所定の
厚さ、たとえば5〜30μm程度に形成された不純物濃
度が低いp型の低濃度の半導体層1bとからなる半導体
基板1の低濃度の半導体層1b側にn型のエピタキシャ
ル成長層が設けられ、p型不純物の拡散により形成され
た素子分離領域3と半導体基板1とにより区画されたウ
ェル2が形成され、ウェル2内にはベース領域4、エミ
ッタ領域5、コレクタ領域のオーミックコンタクト領域
6、埋込層7などからなるトランジスタなどが形成され
る。また、図4に示された従来例と同様にこれらの領域
に電極8、9、10、11、12が接続されている。
The semiconductor device of the present invention has a high impurity concentration of, for example, 10 17 to 10 18 / cm 3 and a high impurity concentration.
The ++ type high-concentration semiconductor layer 1a and the impurity concentration formed on the surface side of the semiconductor layer to have a predetermined thickness of about 10 14 to 10 16 / cm 3 and, for example, about 5 to 30 μm. An n-type epitaxial growth layer is provided on the low-concentration semiconductor layer 1b side of a semiconductor substrate 1 including a low-p-type low-concentration semiconductor layer 1b, and an element isolation region 3 and a semiconductor substrate formed by diffusion of p-type impurities. A well 2 defined by 1 and 1 is formed, and in the well 2, a transistor including a base region 4, an emitter region 5, an ohmic contact region 6 of a collector region, a buried layer 7 and the like is formed. Further, electrodes 8, 9, 10, 11, and 12 are connected to these regions as in the conventional example shown in FIG.

【0014】本発明では半導体基板1として、たとえば
++型の高濃度の半導体層1aの上にp型の低濃度の半
導体層1bが所定の厚さだけ設けられ、該低濃度の半導
体層1b上にウェル2となるn型の半導体層がエピタキ
シャル成長されていることに特徴がある。
In the present invention, as the semiconductor substrate 1, for example, a p + type low concentration semiconductor layer 1b is provided on a p + + type high concentration semiconductor layer 1a by a predetermined thickness. The n-type semiconductor layer to be the well 2 is epitaxially grown on 1b.

【0015】この高濃度の半導体層1aは、不純物濃度
がたとえば1017〜1018/cm3程度で、すなわち比
抵抗は0.06〜0.3Ω・cm程度、その厚さは通常
200〜400μm程度である。この高濃度の半導体層
1aはインゴット製造時に不純物濃度が前述の程度にな
るように不純物を添加してインゴットを製造し半導体ウ
ェハに切り出したものを使用してもよく、不純物濃度が
低いウェハにさらに不純物を拡散などにより導入して高
濃度にすることもできる。
The high-concentration semiconductor layer 1a has an impurity concentration of, for example, about 10 17 to 10 18 / cm 3 , that is, a specific resistance of about 0.06 to 0.3 Ω · cm, and a thickness thereof is usually 200 to 400 μm. It is a degree. As the high-concentration semiconductor layer 1a, an ingot may be manufactured by adding impurities so that the impurity concentration becomes the above-mentioned level during manufacturing of an ingot, and a semiconductor wafer cut out may be used. It is also possible to introduce impurities by diffusion or the like to increase the concentration.

【0016】また、低濃度の半導体層1bは、不純物濃
度が1014〜1016/cm3 程度、すなわち比抵抗が
1.5〜200Ω・cm程度で、その厚さは所定の厚
さ、すなわち、要求される耐圧に必要な空乏層13の幅
W程度、具体的には、たとえば100〜300Vの耐圧
に対して5〜30μm程度の厚さに形成される。一般に
耐圧と空乏層の幅とのあいだには、
The low-concentration semiconductor layer 1b has an impurity concentration of about 10 14 to 10 16 / cm 3 , that is, a specific resistance of about 1.5 to 200 Ω · cm, and has a predetermined thickness, that is, The width W of the depletion layer 13 required for the required breakdown voltage is formed to a thickness of about 5 to 30 μm for a breakdown voltage of 100 to 300 V, for example. Generally, between the breakdown voltage and the width of the depletion layer,

【0017】[0017]

【数1】 [Equation 1]

【0018】ここで、qは電子電荷、εは誘電率、NA
はアクセプタ濃度、W1 はアクセプタ側空乏層幅、ND
はドナー濃度、W2 はドナー側空乏層幅の関係があり、
耐圧を高くするためには、空乏層の幅を広く、すなわち
半導体基板の不純物濃度を低くする必要がある。たとえ
ば、耐圧が35〜50Vでは空乏層の幅は数μm程度必
要で、耐圧が100V以上では空乏層13の幅Wが5μ
m以上になることが必要である。
Where q is electronic charge, ε is permittivity, N A
Is the acceptor concentration, W 1 is the width of the depletion layer on the acceptor side, N D
Is the donor concentration, and W 2 is the width of the depletion layer on the donor side.
In order to increase the breakdown voltage, it is necessary to widen the width of the depletion layer, that is, reduce the impurity concentration of the semiconductor substrate. For example, when the breakdown voltage is 35 to 50 V, the width of the depletion layer needs to be about several μm, and when the breakdown voltage is 100 V or more, the width W of the depletion layer 13 is 5 μm.
It is necessary to be m or more.

【0019】この高濃度の半導体層1aと低濃度の半導
体層1bとからなる半導体基板1をうるには、低濃度の
半導体層1bの不純物濃度の半導体基板を準備し、一方
の面からさらに基板と同一導電型の不純物を導入し、拡
散することにより所定の厚さだけを残して高濃度の半導
体層1aを形成するか、高濃度の半導体層1aの不純物
濃度の半導体基板を準備し、その一方の面に低濃度の半
導体層1bをエピタキシャル成長することによってえら
れる。
In order to obtain the semiconductor substrate 1 composed of the high-concentration semiconductor layer 1a and the low-concentration semiconductor layer 1b, a semiconductor substrate having an impurity concentration of the low-concentration semiconductor layer 1b is prepared, and the substrate is further provided from one side. An impurity of the same conductivity type is introduced and diffused to form a high-concentration semiconductor layer 1a leaving a predetermined thickness, or a semiconductor substrate having an impurity concentration of the high-concentration semiconductor layer 1a is prepared. It can be obtained by epitaxially growing the low-concentration semiconductor layer 1b on one surface.

【0020】本発明によれば、エピタキシャル成長層が
形成される半導体基板1がエピタキシャル成長層(ウェ
ル2)の形成される面側の所定厚さ(所望耐圧に要求さ
れる空乏層の厚さ)だけウェル2の不純物濃度、たとえ
ば1015〜1017/cm3 より低い不純物濃度である1
14〜1016/cm3 程度に形成された低濃度の半導体
層1bと残部はウェル2の不純物濃度より高い不純物濃
度の1017〜1018/cm3 程度に形成された高濃度の
半導体層1aからなる半導体基板1を使用しているた
め、ウェル2とのpn接合に形成される空乏層は低い不
純物濃度により充分拡がり、耐圧が向上する。また低濃
度の半導体層1bは空乏層が形成される5〜30μm程
度のみで半導体基板1の残部は不純物濃度が1017〜1
18/cm3 程度の高濃度の半導体層1aであるため、
比抵抗は0.06〜0.3Ω・cmと抵抗分としてはほ
とんど現われず、半導体基板1の裏面をアース電極とし
て使用する半導体装置でも何らの特性の低下を生じな
い。
According to the present invention, the semiconductor substrate 1 on which the epitaxial growth layer is formed has a well of a predetermined thickness (thickness of the depletion layer required for a desired breakdown voltage) on the surface side where the epitaxial growth layer (well 2) is formed. An impurity concentration of 2, for example, an impurity concentration lower than 10 15 to 10 17 / cm 3 1
The low-concentration semiconductor layer 1b formed to have a concentration of 0 14 to 10 16 / cm 3 and the remaining portion has a high-concentration semiconductor layer having an impurity concentration of 10 17 to 10 18 / cm 3 which is higher than the impurity concentration of the well 2. Since the semiconductor substrate 1 made of 1a is used, the depletion layer formed at the pn junction with the well 2 is sufficiently expanded due to the low impurity concentration, and the breakdown voltage is improved. Further, the low-concentration semiconductor layer 1b has only a depletion layer of about 5 to 30 μm, and the rest of the semiconductor substrate 1 has an impurity concentration of 10 17 to 1 μm.
Since the semiconductor layer 1a has a high concentration of about 0 18 / cm 3 ,
The specific resistance of 0.06 to 0.3 Ω · cm hardly appears as a resistance component, and the characteristics of the semiconductor device using the back surface of the semiconductor substrate 1 as the ground electrode are not deteriorated.

【0021】つぎに本発明の半導体装置に用いる高濃度
の半導体層1aと低濃度の半導体層1bとからなる半導
体基板の具体的な製法について図2および図3を参照し
ながら説明する。
Next, a specific method for manufacturing a semiconductor substrate which is used in the semiconductor device of the present invention and is composed of the high-concentration semiconductor layer 1a and the low-concentration semiconductor layer 1b will be described with reference to FIGS.

【0022】実施例1 図2は不純物濃度が低い低濃度の半導体層1bからなる
基板の一方の面からさらに同じ導電型の不純物を拡散し
て高濃度の半導体層1aを形成するもので、まず図2
(a)に示される、たとえば不純物濃度が1015/cm
3 程度、厚さが200〜400μm程度の、たとえばp
型の低濃度の半導体層1bからなる基板の一方の面側に
ボロンなどのp型不純物をイオン注入または塗布などに
より導入する(図2(b)参照)。そののち1100〜
1250℃で熱処理をすることにより、5〜30μm程
度拡散されない部分が残るように拡散させて不純物濃度
が1017〜1018/cm3 程度の高濃度の半導体層1a
とし、高濃度の半導体層1a上に低濃度の半導体層1b
が薄く形成された半導体基板1がえられる。この半導体
基板1の低濃度の半導体層1b側にn型のエピタキシャ
ル成長層を設け、素子分離領域を形成し、ウェル内に各
素子を形成することにより本発明の半導体装置がえられ
る。
Example 1 FIG. 2 shows that a high-concentration semiconductor layer 1a is formed by further diffusing impurities of the same conductivity type from one surface of a substrate formed of a low-concentration semiconductor layer 1b having a low impurity concentration. Figure 2
For example, the impurity concentration shown in (a) is 10 15 / cm 3.
3 and a thickness of about 200 to 400 μm, for example p
A p-type impurity such as boron is introduced by ion implantation or coating on one surface side of the substrate formed of the low-concentration type semiconductor layer 1b (see FIG. 2B). After that, 1100-
By heat treatment at 1250 ° C., the high concentration semiconductor layer 1a having an impurity concentration of about 10 17 to 10 18 / cm 3 is diffused so as to leave a portion not diffused to about 5 to 30 μm.
And the low-concentration semiconductor layer 1b is formed on the high-concentration semiconductor layer 1a.
A semiconductor substrate 1 having a thin thickness can be obtained. The semiconductor device of the present invention can be obtained by providing an n-type epitaxial growth layer on the low-concentration semiconductor layer 1b side of the semiconductor substrate 1, forming an element isolation region, and forming each element in the well.

【0023】実施例2 図3は高濃度の半導体層1aからなる基板の表面にエピ
タキシャル成長により低濃度の半導体層1bを設けたも
ので、まず図3(a)に示されるように、不純物濃度が
1017〜1018/cm3 程度で200〜400μmの厚
さのp型の高濃度の半導体層1aからなる基板を準備す
る(図3(a)参照)。その基板の表面に不純物濃度が
1014〜1016/cm3 になるように、たとえばボロン
をドーピングしたp型の低濃度の半導体層1bを5〜3
0μm程成長し、半導体基板1とする(図3(b)参
照)。
Example 2 FIG. 3 shows a case where a low-concentration semiconductor layer 1b is provided by epitaxial growth on the surface of a substrate composed of a high-concentration semiconductor layer 1a. First, as shown in FIG. A substrate composed of a p-type high-concentration semiconductor layer 1a having a thickness of about 10 17 to 10 18 / cm 3 and a thickness of 200 to 400 μm is prepared (see FIG. 3A). For example, boron-doped p-type low-concentration semiconductor layer 1b having a concentration of 10 14 to 10 16 / cm 3 is formed on the surface of the substrate in an amount of 5 to 3
The semiconductor substrate 1 is grown to have a thickness of about 0 μm to form the semiconductor substrate 1 (see FIG. 3B).

【0024】そののち実施例1と同様に低濃度の半導体
層1b側にn型のエピタキシャル成長層を設け、ウェル
内に各素子を形成することにより本発明の半導体装置が
えられる。
After that, as in Example 1, an n-type epitaxial growth layer is provided on the side of the low-concentration semiconductor layer 1b, and each element is formed in the well to obtain the semiconductor device of the present invention.

【0025】[0025]

【発明の効果】本発明の半導体装置によれば、不純物濃
度が高い半導体基板の表面に不純物濃度が低い層を設
け、その上に基板と異なる導電型のエピタキシャル成長
層を設けてウェルとしているため、ウェルの境界となる
pn接合の空乏層は不純物濃度が低い層により拡がり、
耐圧が向上する。一方、半導体基板の他の部分は不純物
濃度が高く抵抗が小さいため、半導体基板の裏面をアー
ス電極にして使用しても基板抵抗が問題となることはな
い。その結果、高耐圧で高特性の半導体装置がえられ
る。
According to the semiconductor device of the present invention, a layer having a low impurity concentration is provided on the surface of a semiconductor substrate having a high impurity concentration, and an epitaxial growth layer having a conductivity type different from that of the substrate is provided thereon to form a well. The depletion layer of the pn junction, which becomes the boundary of the well, expands due to the layer with a low impurity concentration,
Withstand voltage is improved. On the other hand, since the other portions of the semiconductor substrate have a high impurity concentration and a low resistance, the substrate resistance does not pose a problem even when the back surface of the semiconductor substrate is used as a ground electrode. As a result, a semiconductor device having high breakdown voltage and high characteristics can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の一実施例を示す断面説明
図である。
FIG. 1 is a cross-sectional explanatory view showing an embodiment of a semiconductor device of the present invention.

【図2】図1における半導体基板の一製法を示す説明図
である。
FIG. 2 is an explanatory view showing one manufacturing method of the semiconductor substrate in FIG.

【図3】図1における半導体基板の他の製法を示す説明
図である。
FIG. 3 is an explanatory view showing another method for manufacturing the semiconductor substrate in FIG.

【図4】従来の半導体装置を示す断面図である。FIG. 4 is a sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 1a 高濃度の半導体層 1b 低濃度の半導体層 2 ウェル 3 素子分離領域 1 semiconductor substrate 1a high-concentration semiconductor layer 1b low-concentration semiconductor layer 2 well 3 element isolation region

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に該半導体基板の導電型と
異なる導電型のエピタキシャル成長層が形成され、該エ
ピタキシャル成長層に前記半導体基板に達する素子分離
領域が形成されることにより該素子分離領域と半導体基
板で区画されたウェルが複数個形成され、該ウェルの各
々に半導体素子が形成され、前記半導体基板の裏面に電
極が形成されてなる半導体装置であって、前記半導体基
板のエピタキシャル成長層側の所定厚さの不純物濃度は
前記エピタキシャル成長層の不純物濃度より低く、か
つ、前記半導体基板の残余の部分の不純物濃度は前記エ
ピタキシャル成長層の不純物濃度より高く形成されてな
る半導体装置。
1. An epitaxial growth layer having a conductivity type different from that of the semiconductor substrate is formed on a semiconductor substrate, and an element isolation region reaching the semiconductor substrate is formed in the epitaxial growth layer, thereby forming the element isolation region and the semiconductor. A semiconductor device comprising a plurality of wells partitioned by a substrate, a semiconductor element formed in each of the wells, and an electrode formed on the back surface of the semiconductor substrate, wherein the semiconductor device has a predetermined epitaxial growth layer side. A semiconductor device in which the impurity concentration of the thickness is lower than that of the epitaxial growth layer, and the impurity concentration of the remaining portion of the semiconductor substrate is higher than that of the epitaxial growth layer.
【請求項2】 前記不純物濃度が低い半導体層の不純物
濃度が1014〜1016/cm3 で、その厚さが5〜30
μmである請求項1記載の半導体装置。
2. The semiconductor layer having a low impurity concentration has an impurity concentration of 10 14 to 10 16 / cm 3 and a thickness of 5 to 30.
The semiconductor device according to claim 1, which has a thickness of μm.
JP18734094A 1994-08-09 1994-08-09 Semiconductor device Pending JPH0851117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18734094A JPH0851117A (en) 1994-08-09 1994-08-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18734094A JPH0851117A (en) 1994-08-09 1994-08-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0851117A true JPH0851117A (en) 1996-02-20

Family

ID=16204292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18734094A Pending JPH0851117A (en) 1994-08-09 1994-08-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0851117A (en)

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