JPH08509344A - Field programmable gate array tiled structure - Google Patents

Abstract

(57) [Summary] An FPGA is provided with a logic element having direct connection to adjacent logic elements and indirect connection via a routing matrix. The logic elements and part of the routing matrix are formed as part of a tile and the tiles are stitched together to form an array of selectable size. The routing matrix includes routing lines that only connect one tile and routing lines that extend over longer distances through several tiles or through the entire chip. This combination is achieved by forming individual tiles that are identical to each other.

Description

Detailed Description of the Invention            Field programmable gate array tiled structure TECHNICAL FIELD OF THE INVENTION   The present invention relates to programmable logic devices formed in integrated circuits, In particular, a programmable logic device with logic blocks in the form of a repeating pattern Regarding the structure of the chair. BACKGROUND OF THE INVENTION   Field programmable gate arrays (FPGAs) are well known in the art. is there. FPGA is programmable to provide the desired logic functionality to the user It includes an array of flexible logic blocks (CLBs) that are interconnected and interconnected. US Reissue Patent No. Re. Reissued US Pat. No. 4,873,32,363 No. 0,302 describes a well-known FPGA structure, which is hereby incorporated by reference. Be incorporated into. U.S. Pat. Nos. 4,758,745, 5,243,238, And published international application WO 93/05577 also describes other FPGA structures. , Which is incorporated herein by reference. Further reference here California 95124 San Jose Logic Drive 210 Zerox, Xilinx Day, 1993, issued by Lee Corporation Tabuk "Programmable Logic Data Book" has many FPGA structures It describes several products that will be used for production.   FPGA is a general-purpose device, that is, a device that can perform any one of multiple functions. It is considered a chair and is programmed by the end user to perform the desired function. This Because of its design flexibility, general-purpose FPGAs often remain unused in many applications. Includes a number of connecting lines and transistors. In addition, FPGA has a specific function Includes an additional device that facilitates the execution of the program to exercise. These additions This is disadvantageous because the device requires a large surface area on the FPGA chip. this It is commercially important to reduce the cost of FPGA to compensate for the addition. Cost reduction One of the ways to reduce the versatility of FPGA is to use it less frequently. This is to exclude some of the circuit layout options. But the circuit layout The reduction in options above may not be predictable as to which option will be needed For some customers, the value of the FPGA will decline. Therefore, the circuit layout There is a need to reduce the surface area while maximizing the option. Summary of the invention   The field programmable gate array (FPGA) structure according to the present invention is repeated. It has tiles that can be placed back. Each tile is a programmable routing matrix And a logic block matrix having flexible circuit arrangement. Circuit layout flexibility The logical block matrix consists of a programmable routing matrix and adjacent Circuit layout in a flexible logic block matrix and programmable form You can connect with. Programmable routing matrix Programmable routing matrix and long lines across tiles Can be connected. This way, each tile has logic, connections to adjacent tiles, and With a combination of connections to the entire routing structure. Joining these tiles together Together to form an array of tiles, which constitutes the functional part of the FPGA chip. It This structure makes them different by simply connecting different numbers of tiles together. Manufacturing devices of different sizes without the expense and time-consuming design efforts. I need it. Also according to the invention, the programmable routing matrix Programmable logic block matrix Minimize the number of connection points (PIPs), reduce the chip surface area and maximize the overall chip density. Make big Further, according to the present invention, the proper positioning of the PIP is required for the routing. To maximize the functionality of the FPGA.   The tile structure comprises a set of signal lines going out of the tile at the boundaries. Shi So, for example, the signal line going out on the right side of one tile is It connects to the signal line going to the outside on the left side of. In one embodiment, they are adjacent to each other. The tiles are the same and form a repeating pattern. In another example In addition, adjacent tiles are not identical to each other, but The portions are provided with signal lines that closely match at the tile boundaries. That is, the boundary The chips can be formed as an array of modular units that match in You can easily increase the flexibility of the tile design that can be used in the design. Brief description of the drawings   FIG. 1 shows an FPGA chip including components according to the present invention.   FIG. 2A shows a single core tile included in most of the FPGA chip of FIG.   FIG. 2B shows four adjacent core tiles of the type shown in FIG. 2A.   FIG. 3A is a circuit arrangement flexible logic block matrix that is part of the tile of FIG. 2A. Show the tusks.   FIG. 3B shows connecting the output lines of a logic block having a flexible circuit arrangement to one output line. 1 shows a multiplexer structure that implements all PIPs.   FIG. 3C shows one implementation of a multiplexer configuration that drives a flexible input line. An example is shown.   FIG. 4A shows the circuit-configurable logic blocks of the matrix 4 of FIG. 3A.   FIG. 4B shows the tri-state buffer block 302 of FIG. 3A.   FIG. 4C shows the output enable block 309 of FIG. 3A.   FIG. 4D is an embodiment of the lookup table for the F, G, H and J function generators of FIG. 4A. Show.   FIG. 4E is another lookup table for the F, G, H and J function generators of FIG. 4A. An example of is shown.   FIG. 4F is a carnoma for the lookup table function generator of FIG. 4D or 4E. Shows the   4G can be implemented with the lookup table function generator of FIG. 4D or 4E.¹⁶of Indicates one of the logical functions.   FIGS. 5A-5C show the logical block having the circuit arrangement flexibility of FIG. Example of application to continuous connection decoding circuit and five-input combination function Show.   FIG. 6 shows the programmable routing matrix of FIG. 2A.   FIG. 7A is a programmable routing matrix of the present invention as shown in FIG. An example of the possibility of connection formation obtained by   FIG. 7B illustrates the programmable routing matrix of FIG. 6 and FIG. 2A or 2B. An example of connection formation possibility obtained in combination with a tile structure will be shown.   Figure 8 shows the global signal line near the corner of the chip Connection to the global signal line that extends to the four edges and is connected to the global line for driving the core tile Is shown.   FIG. 9 shows a long line divider provided on a long line in one embodiment of the present invention. Show.   10A-10D show left, upper, right and lower sides according to one embodiment of the present invention. The margin tiles are shown respectively.   11A to 11D are the upper left corner, the upper right corner, the lower right corner, and the lower left corner of the embodiment. Ill and respectively.   FIG. 12 shows a logic diagram of one embodiment of the oscillator used in FIG. 11B. Detailed description of the drawings   The following notations are used throughout the drawings. That is, the small value at the intersection of the two lines The solid black dots represent the fixed electrical connection between the two intersecting lines. The white circle surrounding the intersection of two lines is a programmable connection between the two lines. (For example, a pass transistor that turns on to form a connection). White circle Represents a bidirectional signal flow between two lines. White triangle between two lines Represents the programmable connection with the signal flow going to the line pointed by the vertex of the triangle. Forget (in this case the signal is of course present over the length of the line, ie If the opposite triangles also point to the same line, the same signal flow will occur). This According to one embodiment of the invention, the programmable connections are each programmable Is formed using an interconnection point (PIP) consisting of at least one transistor It   A triangle that overlaps one line that does not intersect another line points to the vertex of that triangle Represents a buffer that produces a directional signal flow. Global lines ENOUT and ENLL Terminate inside the tile or matrix structure (except shown in FIG. 3A). That is, the line does not extend to the boundaries of the tile or matrix. Physically terminate inside the module. Lines that extend to the boundaries of a tile or matrix Connects to a line on an adjacent tile, that is, a line that comes into contact with the joining of two tiles. Continued. How many lines extend to the edge of one tile and thus reach adjacent tiles The name is changed at the tile boundary. Circuit layout Flexible logic block matrix And the lines in the programmable routing matrix have the same reference numbers. The lines are attached to indicate the physical connection between these lines.   FIG. 1 shows an FPGA chip 100 according to the present invention. In the center of the chip 100 Has a plurality of identical core tiles 101 connected to each other by conductor lines (details will be described later). Along the four sides of the chip 100, west, north, east and south edge tiles 103, 104, 105 and 106 are arranged respectively. There are four in the four corners of this chip. Corner tiles 113, 114, 115 and 116 are respectively arranged. It In addition, the chip 100 is a pad, i.e., the edge tile 103, 104, 105, 1 06 and corner tiles 113-116 packaged (to accommodate chip 100) Pad P1-P56 connected to the external pins of. Each corner tile has one core It is also connected to the tile 101. As shown in Figure 1, the margin tiles are different from each other. Number of pads P, typically 0 to 4 pads (see FIGS. 10a-10d). Will be described in detail). FIG. 1 shows a high voltage source pad VCC and a low voltage source pad. De GND is also shown. Power and ground wiring throughout the chip (shown No) is provided by a conventional method.   FIG. 2A shows the core tile 101. Core tile 101 is a programmable path Instruction matrix 201 and circuit block flexible logic block matrix 2 Including 02. The programmable routing matrix 201 is described in detail with reference to FIG. As described above, the circuit layout flexible logic block 201 will be described in detail with reference to FIG. 3A.   Sufficts extending west from programmable routing matrix 201 Twelve lines with lines 0 to 11 are provided. These lines are 1X long westward lines W 1-W5, W7-W11, and double west lines DW0 and DW6 (details later Statement) is included. Extend north from programmable routing matrix 201 The double long north lines N1-N5, N5-N11 and double long north lines DN0 and DN6 Is also provided. In addition, the 1-fold length East lines E1-E5 and E7-E11 extending eastward , And double length east line DE0-DE6 are also provided. Furthermore, 1 times extending to the south Chonan line S1-S5 and S7-S11, and double Chonan line DS0 and DS6 Setting There is a mark. In addition, the double length horizontal line DH0 And DH6. In addition, double-long vertical across north-to-south tile 101 With lines DV0 and DV6.   FIG. 2B shows four adjacent core ties having the same circuit arrangement as the tile 101 shown in FIG. 2A. 10a, 101b, 101c and 101d. In FIG. 2B, Most lines are unsigned for clarity. As mentioned above, for tile 101 The lines that extend to the edges are connected to the lines in adjacent tiles. For example, programmable West of tile 101b extending west from the routing matrix 201b. Line W1b is connected to the 1x long east line E1a in the adjacent tile 101a. Tile 1 The double length horizontal line DH6a of 01a is connected to the double length horizontal line DH6b of tile 101b. In addition, although not shown in FIG. 2B, the tile placed immediately west of the tile 101a. Is connected to the double-length east line DE6 (hence the term "double-length") ). The line Q0c extending east from the CLB matrix in tile 101c is Connected to line QW0d extending west from CLB matrix 202d in file 101d Has been done. Further, in FIG. 2, the water that continuously extends from the tile 101 to the adjacent tiles. Also shown are the flat global lines GH0 and GH1 and the vertical global lines GV0 and GV1. It These global lines are connected to the common line at the edge of the tile, and signals on the global line such as GH0 are connected. Can be supplied to all tiles. As shown in Fig. 2B, vertical large Lines GV0 and GV1 and horizontal global lines GH0 and GH1 are programmed Possible routing matrix 201 and circuit layout flexible logic block mat It is connected to both of the lix 202.   Returning to FIG. 2A, the circuit block flexible logic block (CLB) matrix 2 02 is the western tile (shown in the figure) due to the output lines Q0-Q3 and the input lines QW0-QW3. Connected to the CLB matrix inside the output line Q0-Q3 and the input line Q Connect to CLB matrix in north tile (not shown) by N0-QN3 The output lines Q0-Q3 and the input lines QE0-QE3 cause CL in the east tile. It is connected to the B matrix and is connected by output lines Q0-Q3 and input lines QS0-QS3. Connected to the CLB matrix on the south tile (not shown). Output line Q0-Q3 send the same signal from CLB matrix 202 to adjacent tiles in four directions. It is communicated and is therefore given the same name. Carry input line CIN And carry output line COUT, that is, a line extending vertically in tile 101, is Connected to the carry output line and the carry input line in the cable, respectively. 349, 250 "Logic structure and circuit for high-speed carry" And forms a high-speed carry path for the arithmetic function unit. This U.S. patent is here Incorporated herein by reference. Circuit block flexible logic block matrix 202   FIG. 3A is a circuit block flexible logic block (CLB) matrix 2 of FIG. 2A. 02 is shown. CLB matrix 202 is CLB301, tri-state buffer block 302, input interconnection wiring structure 303, CLB output interconnection wiring structure 304, Return interconnection wiring structure 305, ordinary input interconnection wiring structure 306, resistor system Custom interconnect wiring structure 307, output interconnect wiring structure 308, and output enable It includes a bull block 309. Sparse PIP distribution   Programmable connections are programs with at least one transistor each Provided using a Ramtable Interconnect Point (PIP). As is well known in the art, each Transistors occupy valuable area on the chip substrate. See FIG. 3A in accordance with this invention. In comparison, the input interconnection wiring structure 303, the feedback interconnection wiring structure 305, Of the input interconnection wiring structure 306 and the register control interconnection wiring structure 307; Most of the internal horizontal and vertical lines do not have programmable connections. You That is, the PIPs in these structures are sparse and sparse "with PIPs" Is. Sparse PIP distribution minimizes chip surface area consumed by PIP Maximize overall density. Further, according to the present invention, only proper placement of PIP This significantly increases the flexibility of route provision, and PIP in interconnection wiring structure Effectively compensate for the decrease in the number of.   For example, referring to the input interconnection wiring structure 303, the position of PIP is CL. From each output line from the B-output interconnect wiring structure 304, an adjacent tag in each of four directions is provided. To allow connection to one of the function generators F, G, H or J is there. In this embodiment, the conventional input interconnect wiring structure 306 is the CLB 301. CLB input lines to (J0-J3, JB, H0-H3, HB, G0-G3, CB , F0-F3 and FB). Mutual return The connection wiring structure 305 is a function generator in the CLB 301 from one of the output lines Q0-Q3. Provides a direct connection to one of the input terminals. Output interconnection, as shown in Figure 3A Twenty-four PIPs in wiring structure 308 route output lines Q0-Q7 for tile interconnect wiring. It is connected to the lines M0-M23. In this way, the interconnection wiring lines M0-M2 Signal applied to 3 is CLB 301 and programmable routing matrix 2 01 selectively (CLB output interconnect wiring structure 304, conventional Via input interconnect wiring structure 306 and output interconnect wiring structure 308). This In one embodiment, no more than one PIP is provided for every eight interconnect lines. , Thereby minimizing the silicon surface area. Nevertheless, is it an arbitrary output line? The possibility of forming a connection to any input line can be secured by the PIP provided here. It Circuit arrangement flexible logic block 301   A circuit layout flexible logic block (CLB) 301 is shown in FIG. 4A. This practice In the example, CLB 301 includes four function generators F, G, H and J, which Each of the function generators has an output determined by the four input signals to the function generator and the stored value. It contains a 16-bit lookup table that produces the force signal. In this way, the function generator F produces an output signal which depends on the input signals applied to the lines F0-F3, and the function generator G Generates an output signal determined by the signals supplied to the CLB input lines G0-G3, and the function generation The container H produces an output signal which is determined by the signals applied to the CLB input lines H0-H3, Generator J produces an output signal determined by the signals applied to CLB input lines J0-J3. . Reference table   The operation of the lookup table function generator will be described with reference to FIGS. 4D-4G. these Figure is a US reissue patent No. Re. U.S. Pat. No. 4, reissued as 34,363. , 870, 302, which was invented by the inventor Freeman. Incorporated herein by reference.   FIG. 4D shows a reference table, that is, a 16-bit RAM in this embodiment. Shows a look-up table, which has 16 possible 4 input signals. An output signal is produced in response to any one of the combinations. More specifically, the input signal Nos. A and B are used to select any one of the four columns of 16-bit RAM. Control the coder. Similarly, the input signals C and D are four rows of 16-bit RAM. Select any one of. This 16-bit RAM has a selected row and selected Produces an output signal representative of the bits at the intersections of the columns. There are 16 such intersections , Therefore, there are 16 such bits. Therefore, 16 bits Two¹⁶Will result in a number of possible combinations. That is, four-input NOR gate When simulating with a 16-bit RAM, The Carnot map is as shown in Figure 4F. In FIG. 4F, the first row (A = 0, Bit at the intersection of B = 0) and the first column (representing C = 0, D = 0) All bits other than 0 are 0. For A = 1, B = 0, C = 0, D = 0 If a logic "1" output signal is required, then a logic "1" is placed between the second row and the first column. Store at the intersection. A = 0, B = 0, C = 0 and D = 0, and A = 1, B = If a logic "1" is required for 0, C = 0 and D = 0, then the first column and first row And store a logic "1" at each of the intersections with the second row. Look up the table like this The logic circuit represented by the loading is shown in FIG. 4G. That is, FIG. The reference table for D is 2¹⁶Represent a precise and simple realization of any one of I forgot.   FIG. 4E shows the organization of the register that yields any one of the 16 select bits. left Each of registers 0-15 labeled "16 select bits" in the vertical column is side by side. The selected signal of logic "1" or "0" is included. For signals A, B, C and D By selecting the appropriate combination of these complements, The particular bit stored in the particular one of the 16 positions in the Sent out. That is, for example, send the bit in the "1" register to the output lead. Signal A, B, C, D is applied to the marked conductor. Also, 16 selection bits To send the signal at the 16th position "15" in the register to the output conductor, signal A, Providing any one of the Noh.   Returning to FIG. 4A, the memory bits in the lookup tables F, G, H and J are common. Usually during the circuit layout of a chip, for example via a shift register, or Loaded by less means. In some embodiments, memory bits are chip behaviors. Load, thereby relocating the working chip. Circuit rearrangement The memory structure with faculty is Freeman et al. (Fr. eeman et al) US Pat. "Distributed Memory Structures for Faithful Logical Arrays and Methods of Using Distributed Memory". , Which is incorporated herein by reference.   The function generators F, G, H and J are connected to CLB output lines X, Y, Z and V, respectively. Produces output. These output signals from the function generators F, G, H and J are Lexa C1, C2, C3 and C4 are controlled respectively, and cumulative carry output COUT Cause The multiplexer C1 outputs the carry input signal to the line C1N and the input signal to the line F1. B respectively receives and produces an output signal on the line CF. The multiplexer C2 outputs the signal On the line CF, the input signal on the line GB, and the output signal on the line CG. Ma The multiplexers C3 and C4 are connected similarly to the multiplexers C1 and C2. . Multiplexer C4 produces an output signal on line COUT from CLB 301. Arithmetic For a detailed description of the surgical function, please refer to the burner assigned to the same assignee as this application. Day. New invention US Patent No. 5, 349, No. 250 for high speed carry See Logic Structure and Circuit. In addition, This patent is referred to here Incorporate.   Each CLB 301 is a function generator F, G, Four storage devices RX in addition to H and J , RY, Includes RZ and RV. These storage devices RX, RY, Of RZ and RV Each is a flip-flop with main and slave stages, From these masters and slaves An output multiplexer that receives an output as an input. That is, Device RX , RY, RZ and RV are configured to form flip-flops or latches. The circuit can be arranged with a chipplexer.   Periodic resupply of voltage to the carry signal is usually required. In this example, This To re-supply the voltage of For voltage resupply including inverters 1121 and 1122 Buffer every four multiplexers on carry path or every CLB301 Deploy. In another embodiment, The voltage resupply buffer is a carry path Provided for every two Plexers, Provide two voltage resupply buffers for each CLB To do.   In this example, CLB301 contains 5 input lines per function generator . For example, Referring to the function generator F, CLB input lines F0-F3 are function generators F Supply the input signal to The fifth CLB input line FB receives the multiplexer control input signal Supply. Function generator G, H and J are similarly arranged in the circuit. Three input lines CL K, CE and RST are Clock signal, Clock enable signal and reset Register signal RX, RY, Supply to RZ and RV respectively.   As shown in FIG. 4A, Four groups of one output signal, That is, each The four groups associated with the number generator originate from CLB 301. this The three output signals include: Ie;   .Function generator (CLB output line X, Y, Direct cash register from Z or V) Output signal not stored.   ・ CLB input signal Ie the signal from the carry chain, Or five for two Input function (CLB output line XB, YB, Supply to ZB or VB) Alternate unregistered output signal based on the signal from the chipplexer.   .Function generator or one of the sources of alternative output signals (CLB output line XQ, YQ , Registered output signal that can be loaded by (provided on ZQ or VQ). For example, the CLB output line X is a direct output signal from the function generator F without register storage. Receive. The CLB output line XB is the signal of the CLB input line FB or the multiplexer S. 1 output signal (as determined by multiplexer B1), That is, carry out Force signal CF or a five-input function generator output signal from multiplexer FG (FIG. 5C). The output signal obtained from (see below) is received. CLB output line XQ An output signal from the register RX, which has been stored in the register, That is, the D input signal is Directly from the function generator F (signal of the output line X) according to the decision of the plexer D1. Or it receives the output signal from the register RX which is derived from the alternative output signal on the line XB. Finally, The output line K becomes high or low depending on the selection of the multiplexer PG. Supply a value signal.   In the example of FIG. 4A, The multiplexers D1-D4 are Function generator F, G, Output signal from H and J (CLB output line X-V) or multiplexer B1- The output signals from B4 are supplied to the registers RX-RV, respectively. Multiplexer S1 and S3 convert the carry signals from multiplexers C1 and C3, respectively. When set to send, The multiplexers B1-B4 are CLB input lines FB-F Select either the input signal of J or the output signal of multiplexers C1-C4 .   The multiplexers C1-C4 are used for carry function in arithmetic operation. Exhibits a wide range of AND and OR functions. To demonstrate the AND function, Line FB Add a logic "0" to CLB output F function generator output signal on line X and line C1N The multiplexer C1 is programmed to produce an AND output with the carry input signal of To on the other hand, To exert the OR function, Add logic "1" to CLB input line FB hand, OR of the complement of the output signal of the CLB output line XL and the carry input signal on the line C1N Program multiplexer C1 to produce the output. According to the exact table structure , The OR output is obtained by loading the inverse value into the exact table. Multiplex Regarding the functions of the C1 to C4 and the interaction with the logic block, See here United States Application No. 08/116, incorporated herein by reference. No. 659 [M-2565] In more detail. Application example of CLB301   5A-5C, Using CLB301 (detailed above with reference to FIG. 4A), Carry Chain, Decoder circuit 2, which can be cascaded, And two five-input function generators it An application example of forming each is shown. In these figures, The thick line is the line of CLB301 Represents what was used for a particular selected function, The thin dotted line is the specific machine Represents something not used for Noh.   In FIG. 5A, CLB301 is a single number A3A2A1A0 and B3B2B Half-value sum H3H2H1H0 of 1B0 (where H3 H2 H1 and H0 are 4 bits 4 bits of sum of half-values) and carry bit C3C2C1C0. Another CLB (not shown), Ie to the right or left of the tile shown CLB, which is preferably arranged, is used for completion of addition. Operand A3 and And B3 to any two of the CLB input lines J0-J3. Operand A2 and B2 is added to any two of CLB input lines H0-H3. A1 and A2 are CLB Add to any two of input lines G0-G3. A0 and B0 are CLB input lines F0- Add to any two of F3. Keep unused lines high or low. Seki Number generator F, G, Each of H and J is a true value test of the XOR function (half-value sum of input signals). Load with a cable. The value added to the input line not used in the antilog table is included in the calculation. . If there are lower order bits than those added to the function generator F, then Those bit The carry output of the switch produces the carry input line C1N. Multiplexer C1, C2 C 3 and C4 are function generators F, G, Controlled by H and J output signals respectively . More specifically, The function generator output signal is a logic 1 (signals A and B are Not equal) The carry input value is sent to the carry output for that bit, Function If the genital output is a logic 0 (signals A and B are equal to each other), Signal A again The value of signal B is sent to the carry output of that bit. Multiplexer B1-B4 , S1 and S3 carry the carry output of each bit to the "B" CLB output line ( That is, C1B output line XB, YB, ZB and VB). For each bit Function generator output signal (CLB output line X, Y, Occurs in Z and V) Is supplied as the half-value sum for that bit.   In another application shown in FIG. 5B, CLB301 is a device that can be cascaded. The circuit is arranged to operate as a coder. 16 represented by signals A0-A15 The bit address is CLB input line F0-F3, G0-G3, And J0-J3 Get CLB input line FB, GB, HB and JB are grounded. Each function generator F, G, The 16 bits of each of H and J are set to reflect a part of a predetermined address. Contains one logic "1". Apply a logic 1 signal to the carry input line CIN. Four functions Generator F, G, H and J all output logic 1 respectively (ie address "Matches") All multiplexers C1-C4 send out a logic 1 Produces a logic one signal on the carry output line COUT.   In another application shown in Figure 5C, CLB301 is for each of the five input signals Yields two functions. The function generators F and G represent the first function of the five input signals as C Occurs on the LB output line XB, The function generators H and J generate a second function of the five input signals. Occurs on CLB output line 2B. For this first function, Four input signals A0- A3 is fed to the CLB input lines to both function generators F and G, 5th input signal No. A4 is supplied to FB. The multiplexer FG functions according to the input signal A4. Select the output signal of the generator F or the function generator G. In this example, Maru The chipplexer S1 is a memory cell for selecting the output signal of the multiplexer FG. Programmed, The multiplexer B1 selects the output signal of the multiplexer S1. Are programmed in the memory cell. In this way Function generator F and The five input function generator output signal from G appears on the CLB output line XB. Similarly, The functions of the five input signals B0-B5 to the function generators H and J are generated on the CLB output line. Cheat.   The loading of the appropriate antilogarithm tables into the two related function generators F and G requires five inputs. Produces the desired function of the force signal. More specifically, In one embodiment, 32-bit lookup table for function generators F and G (ie two 16-bit lookup tables) Reference table). In this way Many functions have different values For memory cell for function generator antilogarithmic table formation and control multiplexers FG and HJ Alternately caused by loading. Tri-state buffer 302   FIG. 4B illustrates a tri-state buffer block 302 (FIG. 4) that includes tri-state buffers B4-B7. 3A) shows a schematic diagram. The line names are the same as those used in FIG. 3A. AND Ge The output signals from the gates A4-A7 control the three-state buffers B4-B7, respectively. . For example, if AND gate A5 produces a logic 0 output signal, Buffer B5 is enable Bull, Output signal via buffer on line TQ5, That is, the corresponding input signal to line Q5 Produces a signal that matches the signal. on the other hand, Produces a logical 1 output signal to AND gate A5 When, Buffer 5 is disabled, It creates a high impedance at the output terminals. The output signals from the AND gates A4-A7 are the output signals from the OR gate OR1 and are large. Is it decided regionally, It is individually determined by the memory cells MM4 to MM7. Memory cell MM4 If MM7 is storing a logic 0, AND gate A4- The output signal of A7 also becomes logic 0 regardless of the signal from the OR gate OR1. OR The OR1 is If the ENLL signal is low, Or if the signal on line TS is high , Produces a high output. Returning to FIG. 3A, Signals on tri-state line TS are tile interconnects Programmably selected from any of the wiring lines M16-M23.   The ENLL signal is provided to all buffers 302 in all tiles 101 It is a global signal. This ENLL signal is Contention, That is, the same input signal Various TS lines for connecting to one long wire are cut unpredictably during circuit layout. To prevent contention that occurs when switching During circuit placement and It will remain low when other signals are subsequently enabled.   Voltage resupply buffer for supplying a signal to a long line while operating the buffers B4 to B7 When used as (always enabled), Memory cells MM4-MM7 Is loaded with a low value during the circuit arrangement period. That is, During circuit placement Will enable buffers B4-B7 with AND gates A4-A7. But, Input signals Q4-Q7 for sending signals TQ4-TQ7 to a long wire are circuit arrangement During the period, it carries a common signal as described below with reference to FIG. 4C, Con There is no tension. Output enable block 309   The buffer in the output enable block 309 is Driven by these buffers In order not to generate line contention, Disable during device placement Will be FIG. 4C shows the structure of block 309. Output enable block 30 Each buffer in 9 includes a 2-input AND gate. One input of each AND is global It is driven by the enable signal ENOUT. The other input has lines Q0'-Q7 ' Prepared, The output signal from CLB 301 (FIG. 3A) is supplied to this line. Times Unexpected lines may be connected to these lines Q0-Q7 during road placement. Therefore, Ko To prevent contention, Keep the ENOUT signal low during circuit layout, Line Q0 -All of the output signals to Q7 go low, and unexpected connection of other lines is inconsistent. So that it does not occur. Adjacent input matrix 303   Referring to FIG. 3A, The connection to the adjacent CLB 301 in the embodiment of the present invention is There is no direct connection, all via PIP. For example, Input signal is the input phase The CLB 301 is selectively supplied from the interconnection wiring structure 303. Each input line QS0 -QS3 can be connected to one of the CLB input lines of one function generator. This practice In the example, The line QS0 can be connected to the CLB input line F1 of the function generator F, line QS1 can be connected to the CLB input line G1 of the function generator G, Line QS2 is a function It can be connected to CLB input line H1 of Genki H, The line QS3 is the CLB of the function generator J It can be connected to the input line J1. Each function generator F, G, H and J are based on the input signal Therefore, the circuit can be arranged to generate an arbitrary function. One function generator Signals specific to the desired input terminal and its appropriately loaded lookup table for the function generator Can be supplied. Therefore, Which input signal can be supplied to which function generator input terminal It doesn't matter.   The signal on input line QW0 drives both CLB input lines F0 and FB. As well To The signal to input line QW1 drives CLB input lines G0 and GB, Input line QW The signal to 2 drives CLB input lines H0 and HB, The signal to the input line QW3 is C Drive the LB input lines J0 and JB. Input line QE0, QE1, QE2 and Q Each signal to E3 also drives two CLB input lines. More specifically, Input line The signal to QE0 drives CLB input lines F1 and FB, Signal to input line QE1 Drives lines G1 and GB, Signal to input line QE1 drives lines H1 and HB Then The signal on input line QE3 drives lines J1 and JB.   The signal to each 1 of the input lines QN0-QN3 and QS0-QS3 is the same as the CLB input line. Drive only one. In detail, The signal to the input line QN0 is the CLB input line F0. Drive The signal to the input line QN1 drives the CLB input line G0, Belief to line QN2 Drive the CLB input line H0, Signal to line QN3 drives CLB input line J0 It The signal to the input line QS0 drives the CLB input line F1, Signal to input line QS1 Drives the CLB input line G1, Signal to input line QS3 drives CLB input line J1 To do. This example Each of the input lines QE0-QE3 and QW0-QW3 Since it is connected to the two CLB input lines in a programmable manner, Multiple signal water Especially desirable for horizontal flow. Other embodiments of the invention include different numbers and locations. With programmable connection, Optimized for different signal flows. Output matrix 304   CLB301 is CLB output line X, XQ, XB, Y, YQ, YB, Z, ZQ, Z B, V, Produces output signals on VQ and VB. Also, CLB301 is Carry out Generate a signal on the force line COUT, The signal to the carry input line CIN in the upper tile Decide whether to transfer to the next CLB. CLB output line X, XQ, XB, Y, YQ, YB, Z, ZQ, ZB, V, VQ, PIP on VB and K is for CLB interconnection Selectively drive through line structure 304 to drive any number of output lines Q0-Q7. Has been programmed. CLB interconnect wiring structure 304 has full PIP distribution (That is, Carry output line COU among 13 output signals of CLB301 Anything except the signal to T can drive any of the output lines Q0-Q7). The interconnection wiring structure 304 also buffers output signals for driving lines other than the above. Please note that 1 for PIP formation of the entire interconnection wiring structure 304 It requires 08 (13 × 8) PIPs. In contrast to this, Structure 303, 305, 306 and 307 are Even if sparsely installed PIPs, a total of 200 PIPs are used There is. Access to specific input signals from tile interconnect wiring lines M0-M23 The flexibility of the CLB 301 in the is secured by the following points. Ie:   .Arbitrary CLB output signal is any of the tile interconnection wiring lines M0-M23 Distributed PIP over CLB output interconnect wiring structure 304 to be supplied to Let   Each line M0-M23 is at least one in each proximity routing matrix 201 To be connected to the lines M0-M23 of Programmable routing matrix PIPs are distributed in 201.   ・ Each output line of one CLB can be connected to at least one input line of each adjacent CLB. The PIPs are distributed in the CLB matrix 202 so that the   .Function generator F, G, Form H and J as reference tables, Each reference text All input signals to the cable are interchangeable.   ·further, Except for the five-input function, Function generator F, G, Interchangeable H and J I have to. in this way, According to this invention, The PIP sparse distribution structure 303, 305, 306 and 307 significantly reduce chip surface area and maximize flexibility.   The signals on output lines Q0-Q3 drive the CLB input lines in adjacent tiles. example If The two core tiles 101 of FIG. 2A are arranged side by side as shown in FIG. 2B. By The output line Q0 on the left side edge of the core tile 101b is It is connected to the input line QE0 on the right side edge. The other lines are correspondingly connected. Shi Therefore, 2A, When referred to in combination with 2B and 3, CLB matrix The CLB output line X (FIG. 3A) of the CLB 301 in the slot 202c (see FIG. 2B) is Out Lines of force, That is, the CLB matrix in the core tile 101c, that is, the core tile Matrices connected to input line QW0d of CLB matrix 202d in 101d Programmable to output line Q0c extending east from box 202c (and in other directions) Are connected in a simple manner. PIP connects input line QW0 (as described above) CLB301 Of the CLB input lines F0 and FB. Like this hand, From the CLB 301 output line in the CLB matrix 202c to the CLB matrix The path to the CLB 301 input line in box 202d, In one embodiment, two It is formed only by using two PIPs composed of transistors.   CLB output interconnect wiring structure 304 in another embodiment shown in FIG. 3B. In PIP inside, The signal to the CLB output line must pass through two transistors Yes (Signal K, Ie a constant voltage or ground signal will pass through four transistors Please note that). FIG. 3B shows the 12 CLB output lines (X, XQ, XB, Y, YQ, YB, Z, ZQ, ZB, V, VQ, VB) and one power supply / Multi that connects all the ground output signal lines K to the output line Q0 and activates all PIPs A plexer structure 400 is shown. The multiplexer structure 400 is a memory cell, Ie Control the first transistor bank 351 consisting of 12 transistors, So Note that selects signal K if no transistor is selected from the bank Resel 31, 32 and 33 are included. Memory cell 31, One of 32 and 33 The stored logic one is one signal from each of the three groups of signals in bank 351. Select the issue. Memory cell 31, 32 and 33 all store a logical 0 If Signal K appears at node 30. In the second stage, Memory cells 34 and 3 5 is an AND gate, Control AND1-AND4, Output line VQ, ZQ, YQ And an output signal from one of XQ and supplies the selected signal to the output line Q0. To do. Memory cell 31, 32 and 33 store a logic 0 and signal K If you choose Memory cells 34 and 35 supply signals to node 30. Must be programmed to. That is, Other than a constant value K that follows a longer route Since we only need two transistors on each path for all signals in 13 Implement the PIP with only 5 memories and 16 transistors. To line K Since the signal is not a switching signal, lengthening the signal path will not be adversely affected. Multip Lexa structure, That is, one of the 13 output signals of CLB301 is selected and A multiplexer structure 400 for driving the output lines is provided for each of the output lines Q0-Q7. is there. It is impossible to drive the output lines Q0-Q7 for any of these 13 output signals. But The multiplexer structure 400 can select two or more of the 13 output signals. I can't. In this way Avoiding contention on output lines Q0-Q7 . In another embodiment of multiplexer structure 400, Each one There are 13 memory cells that control the data. In this way, the required route for each route There is only one transistor, The signal speed is increasing. But, This example is Note that increasing the con surface area. Return interconnection wiring structure 305   Returning to FIG. 3A, The feedback interconnection structure 305 allows the output lines Q0-Q3 to be arranged in a circuit arrangement. CLB input line F2 in the logical block matrix 202 G2 H2 and And J2 selectively. In this embodiment, the output signal from CLB301 Is a function generator F in CLB301, G, To the selected CLB input line of H and J I can return. The feedback interconnection wiring structure 305 is a counter (which feeds back its own signal). Or a shift register (needs signals from adjacent circuits) to support a PIP pattern Equipped. The PIP pattern is CLB input signal line F2 G2 H2 and Signal to J2, CLB input signal line F0, G0, H0, J0, F1, G1, H1 And the signal to J1, That is, CLB matrix such as input lines QW0 and QN3 To prevent contention with signals supplied to other input lines to the switch 202. . Another embodiment of this invention is a different combination of PIPs in the return interconnection wiring structure 305. Equipped with. Normal input matrix 306   The normal input matrix 306 is input to the tile interconnection wiring lines M0-M23. Receive the signal, In addition, these input signals are applied to CLB input lines F0-F3, FB, G0-G3 , GB, H0-H3 HB, It has a PIP that feeds JO-J3 and JB. Depending on the PIP pattern, Any tie in this normal input interconnect wiring structure 306 The signals to the interconnection wiring lines M0-M23 are transmitted to the respective function generators F, G, Of H and J Allows one input line to be driven. The function generator input signals are interchangeable Yes (reference table entries are interchangeable), Tile interconnection wiring line M 0-M23 need not be coupled to more than one input line of the function generator. This normal In an embodiment of the input interconnect wiring structure 306, Each CLB input line FB, GB, HB and JB signals on one of the six tile interconnect wiring lines M0-M23 Is equipped with a PIP so as to be driven by.   As another criterion in this example, 9 or more CLB input lines Not equipped with PIP. That is, Referring to FIG. 3C, Multiplexer structure 401 is three memory cells 36, Using only 37 and 38, First tiger Select one of eight possible signals for controlling the bank 361 of registers. More detailed In detail, The memory cell 38 has input lines QW0 and QN0, M15 and M14, M9 And M8, Select one of each pair of signals to M7 and M6. Memory cell 36 and 37 generates a signal to the input terminals of AND gates AND5-AND8, These signals Allows a second transistor bank for the selection of a single signal on CLB input line F0. Control 362.   In this embodiment of the invention, PIP pattern has a function of 5 inputs (Described above in connection with FIG. 5C). For example, Tile interconnection wiring line M18 or The signal to M19 drives the input line FB, Tile interconnection wiring line M14 or M The signal to 15 drives lines F0 and G0, Tile interconnection wiring line M12 or Signal to M13 drives lines F1 and G1, Tile interconnection wiring line M16 Or a signal to M17 drives input lines F2 and G2, For tile interconnect wiring Line M20 or M21 drives input lines F3 and G3. This circuit layout smells hand, The five-input function can be easily implemented by the PIP pattern provided.   To further describe the invention with reference to FIGS. 3A and 6, With PIP, long Horizontal lines LH0-LH7 and long vertical lines LV0-LV7, And global (horizontal And vertical) line GH0, GH1, GV0, From GV1 to register RV, RZ, RY And the connection to RX is a function generator J, H, Made possible without going through G and F It More specifically, Long horizontal line LH0-LH7 and long vertical line LV0- LV7 and global horizon GH0, GH1 and global vertical GV0, GV1 Il interconnect wiring lines M0-M23 (FIG. 6). These tiles The interconnection wiring line is CLB input line FB, GB, When combined with HB and JB Is Function generator F, G, Bypass H and J respectively, Signal (intermediate multi Register RX, via Plexer) RY, RZ, Supply to each RV. Global line GH0, GH1, GV0 and GV1 are also interconnect wiring structures 307 for register control Via register RX, RY, It is selectively bound to RZ and RV. tile All of the interconnection wiring lines M0 to M23 are connected to one CLB input line FB, GB, HB Or from one long line to one tile interconnection wiring line M0- By providing a connection to M23 (discussed below in connection with FIG. 6), These long lines And the signals to the global lines drive the required registers. To this invention Anyway, With this PIP pattern, Signals for all long lines and global lines Function generator F via the usual input interconnection wiring structure 306, G, Input to H and J It becomes possible to drive the line. Output interconnect wiring matrix 308   In this example, Output lines Q4-Q7 are programmable interconnect wiring mats The output signals to the lix 201 (FIG. 2A) are transmitted to the tile interconnection wiring lines M0 to M11. Or supplied via line TQ4-TQ7. Output lines Q0-Q3 are tile interconnections The output signal is supplied to the selected one of the lines M12 to M13. The fruit shown in Figure 3A In the example, The output interconnection wiring structure 308 provides signals to the output lines Q0-Q7. It is possible to drive up to three tile interconnect wiring lines M0-M23. C The overall PHP distribution of the LB output interconnection wiring structure 304 is an arbitrary output of the CLB 301. It is possible to connect the force lines to any of the tile interconnect wiring lines M0-M23 To The normal input interconnect wiring structure 306 is selected to the output lines Q0-Q3. The return signal is supplied to the CLB 301. Register control interconnection wiring structure 307   Clock line CLK, Clock enable line, Reset line and tri-state line TS , Supply signals (programmable to selected tile interconnect wiring lines M0-M23) (From the routing matrix 201). Also, Low skew system You Clock line CLK to the global horizontal lines GH0 and GH1 for the signal or global It is directly controlled by the signals from the vertical lines GV0 and GV1. No contention   According to this invention, Program one PIP on a given CLB input line If done, No other PIP on that CLB input line should be turned on. example If Program PIP on the intersection of input line QW0 and CLB input line F0 And (ie The signal to the input line QW0 drives the CLB input line F0), tile Interconnection wiring line M6 M7, M8, M9, M14, M15 and input line QN0 The upper PIP remains off, No contention on CLB input line F0 Assure. Normally, To prevent contention, Which PIP on one input line Use a simple decoding method to choose whether to turn on, Or two or more on one input line Memory cell programming software to avoid turning on the PIP above This is achieved by using the rules in. In another embodiment, Alternative means of input selection Is possible. For example, In one embodiment, Specify whether to turn on each PIP To load one memory cell. Programmable routing matrix   FIG. 6 shows the programmable routing matrix 201 of FIG. 2A. In Figure 6 Represents the signal flow to one line for all PIPs in CLB matrix 202. Although it is shown as a triangular shape, In the programmable routing matrix 201 Most PIPs are shown as open circles that represent the signal flow to both lines. An example outside is, Lines TQ4 through TQ7 (output from tri-state buffer block 302 of FIG. 3A) Line) to the long horizontal lines LH0-LH7 and the long vertical lines LV0-LV7. IP, And the global signal line GH0, CH1, GV0, Signal from GV1 is tile phase The PIP is sent to the interconnection wiring lines M0 to M3.   The programmable routing matrix 201 includes Global line, Long line, Double length The line and the 1 × long line extend. Each of these lines Selected tile interconnections It is connected to the lines M0-M23. Programmable routing matrix 20 1 is Connect to programmable routing matrix in proximity tiles, four A double length line extending in the azimuth direction, In other words, 1x Chohoku Line N1-N11, 1x Choto Line E 1-E11, Formed via 1-fold long south line S1-S11 and 1-fold long west line W1-W11 To do. Connection to a programmable routing matrix one tile apart Double Long North Line DN0 and DN6, Double length East Line DE0 and DE6, Double Nannan Line And double length western lines DW0 and DW6 (see FIG. 2A). Across tiles Each of the long vertical lines LV0-LV7 and the long horizontal lines LH0-LH7 that extend in Can be connected to one of the interconnection wiring lines M0-M23.   Although the specific pattern of PIP shown in FIG. 6 is sparse, it has excellent signal transferability. There is. More specifically, Programmable routing matrix 201 In this example, the number of PIPs included is 124, One for each of the lines in Figure 6 It is sparse compared to the approximately 4200 PIPs that result when connected to one line. Shi Scarecrow This PIP pattern is Any line with any intermediate PIP can be Make sure you can connect to the wire. For example, As shown in FIG. West line W1 is east Two PIPs on line E1, That is, the tile interconnection wiring line M1 is connected to these two lines. It is possible to connect by turning on the two PIPs connected to. Contrast to this By the way The connection between the West Line W1 and the East Line E2 requires 8 PIPs and 9 lines . That is, West line W1 to tile interconnection wiring line M1, East line E1, Tiles Continuation wiring line M20, West line W9, Tile interconnection wiring line M9, North line N9, tile Interconnection wiring line M21, And it is necessary to connect through the east line E2. this Length paths are usually undesirable, but In some applications, delay is not an issue. For those By the way, The availability of such a route enables the completion of the design. PIP two Only one simple route, Line N1, S1, E1 and W1 for tile interconnect wiring To line M1, Line N2 S2 E2 and W2 to tile interconnection wiring line M2 and others It can be used to connect to each other via the interconnection wiring line M5. Tile interconnection The wiring line M6 is a double length line DN6. DS6 Connected to DE6 and DW6. Ta Ill interconnection wiring lines M7 to M11 are north, South, Of corresponding numbers that extend east and west It is connected to a 1x long line.   The tile interconnection wiring lines M12-M13 are designed to minimize the decrease in operating speed and The cross connection pattern that enhances the transfer flexibility is put into practice, Sparse PIP distribution is valuable Achieve chip surface area savings. For example, Tile interconnection wiring line M12 is double length North line DN0, South Line S3, East line E5, Connected to the West Line W1, For tile interconnect wiring Line M15 is the north line N3, East line E8, Double Chonan Line DS6, And connected to the west line W4 It In this way The present invention provides a predetermined pattern that minimizes the number of PIPs. , Allows any wire to be connected to any other wire. That is, This invention Ensure that the path is always provided while minimizing the silicon surface area. Routing matrix model   Each of the tile interconnect wiring lines M0-M23 is connected to five or six other lines It is possible. That is, As shown in FIG. 7A, Tile interconnection wiring line M0-M Each of the 23's is represented by an asterisk with five or six tips. For this model And The eight tile interconnection wiring lines M0 to M7 are North line N0-N3, East Line E 0-E3, Programmable on selected one of South Line S0-S3 and West Line W0-W3 Connected in an effective manner. The tile interconnection wiring lines M0 to M3 have the same numerical suffix. North of the cousin South, It is possible to connect to the East and West lines. Tile interconnection wiring line M4 To M7 is north, South, east, Can be connected to one of the West Line staggers. Like this hand, Tile interconnection wiring lines M0-M3 are north of the suffix, east, South and west Provide a means of interconnecting wires, The interconnection wiring lines M4-M7 are lines from four directions. To provide the opportunity for cross-connecting. Also, The tile interconnection wiring lines M0-M7 are The Programmable routing matrix 201 is a logical block with circuit arrangement flexibility Means are provided for connecting to the matrix 202 (FIG. 3A). Routing matrix and logic block connectivity model   FIG. 7B illustrates the "star configuration" of the present invention. In a star configuration, Each CLB is a specific star Features (ie, Programmable routing matrix), Ie other star Radial lines extending from the part 201 to the other CLB 301 via the part 201. It is associated with the star-shaped portion 201 that is open. Double and single length lines are shown in FIG. 7B. I have. In another embodiment, Other lengths of lines are used for the star configuration. this like, The star configuration of this invention provides a good connection between the associated CLB and the rest of the device. Ensure the possibility. Global interconnection wiring structure   FIG. 8 shows a global signal pad P113 arranged near the corner of the chip 100 (FIG. 1). , P114, Normally from P115 and P116 to the four sides of the chip 100. Global signal line GTL to be placed, GTR, Fixed to GBR and CBL respectively Indicates a connection. Each global signal line runs vertically or via each row or column of core tile 101. Programmably connectable to multiple horizontal lines. For example, Global upper left The signal line GTL is connected to the global vertical lines GV1-a to GV1-n by PIP PV1-a to GV1-a. Via PV1-n, One for each row of core tiles 101 PIP can be assigned and connected. The global signal line GTR on the upper right is PIP PH0-a. Through PH0-n, One for each row of core tiles 101 Assign two PIPs, It can be connected to the global horizon GH0-a. Lower right global signal The line GBR can be connected to the global vertical lines GV0-a to GV0-n via GV0-n. . Finally, The lower left global signal line GBL is connected to the global horizontal lines GH1-a to GH1-n. It is possible to continue. Global verticals and globals with reference signs beginning with GV or GH The horizon is 2A, As mentioned in connection with 3 and 7, Through the global connection line Programmable routing matrix 201 and C in core tile 101 It can be connected to the LB matrix 202.   As shown in FIG. Long lines that extend through the edge tiles of chip 100 (FIG. 1) LV0L, LV7L, LH0T, LH7T, LV0R, LV7R, LH0B and And LH7B (not shown in FIG. 8 for simplicity but not shown in FIGS. 10A-10D). Is also connectable to the above global line. More specifically, Lower right global signal The line GBR is a lower horizontal long line LH0B via PIP PGBR0 and PGBR7. And can be driven by a signal to LHTB. The global signal line GBL at the lower left is PIP PG Left vertical long line LV0L via bottom left buffer BBL via BL0 and PGBL7 And can be driven by a signal to LV7L. Equivalent connection on top and right side of chip Is provided. left, Up, The right and lower long lines are PIP traces such as PIP PBR7. They can be connected to each other for any reason. Long line LV0L, LV7L etc. are arbitrary around the chip Is driven by signals from the pads of the pad (discussed below in connection with FIGS. 10A-10D). Via the margin tiles 103-106), Any pad can supply a global signal. Furthermore To any of the core tiles, Global signals can be provided via the margin tiles 103-106 It Selectable long line divider   1-9 illustrate one embodiment of the present invention that includes an elongated line divider that can be partially lined. An example is shown. Each of the upper edge tiles 104, Six core tiles 101, And below Two tile rows consisting of the side edge tiles 106 are shown in FIG. Long vertical line LV0-L V7 crosses all core tiles 101, Marginal tiles 10 in each of the two rows Terminate at 4 and 106. The long vertical lines LV0-LV7 are the margin tiles 104 and Of the tile interconnection wiring lines M0-M15 and TQ0-TQ3 in The exposed one can be connected as is conventional in connection with FIGS. 10A-10D. further , As mentioned above with respect to FIGS. 2A and 6, Long lines LV0-LV7 are progress A selectable line in the ramable routing matrix 201 can be connected. Simple For abbreviation, The horizontal long lines LHO-LH7 are not shown in FIG. It is shown in FIG.   In the embodiment shown in FIG. Vertical long lines L in the three upper core tiles 101 V0-LV7 is a part in three lower core tiles 101 by the long line divider LLS. Is separated from. The enlarged view is Long line splitter LLS in one embodiment Includes an n-type transistor which is turned off by a low voltage applied to the control gate CG, this Shows that the vertical long line is divided into upper and lower segments by It The long line divider LLS is a large chip embodiment, Upper and lower long lines Normally used to allow the two to be driven independently of each other by their position on the chip . As shown in Figure 1, The horizontal long lines LH0 to LH7 are also long lines at the center of the chip 100. It is divided by the divider LLS. In another embodiment, Long wire divider L Is it installed along the same long line as some long line dividers such as LS and LLSA? , The long line divider LLSB has one end of the long line in one edge tile and an adjacent edge tile. Provided between one end of the long wire inside, These long lines are connected to each other in a programmable manner. To continue. Marginal tile for the example of FIG. 2A   10A-10D show the edge tile shown in FIG. 2A in more detail. Stated in more detail Then, 10A-10D show the left edge tile 103, Upper edge tile 104, Right edge tile 105, And the lower edge tile 106, respectively. Edges in these examples Tiles are pad PV, PZ, PY, And usually connected to at least one of the PX, Must It does not mean that it is not connected. In another embodiment, described in more detail below with reference to FIG. , There is at least one border tile that is not connected to any pad.   In FIG. 10A, Four pad PV, PZ, PY, And PX are input / output (I / O) Vice IOBV, IOBZ, IOBY, And connected to the margin tile 103 via IOBX respectively ing. I / O device IOBV, IOBZ, IOBY, And each of I0BX is an edge with three lines Connected to edge tile 103. For example, I / O device IOBV is I / O input line IV, I / O output line OV, And connected to the marginal tile 106 by a tri-state line TSV. Output line OV Note that the output signal supplied to P42 is controlled by the I / O tri-state line TSV. I want to. Similar lines are I / O devices IOBZ, IOBY, It is also equipped with IOBX.   With the PIP full distribution I / O input interconnection wiring structure 1001, I / O input line IV, IZ, IY, Signals on the I / O input lines to and IX can drive the edge tile input lines QIN0-QIN3. next to By the output interconnect wiring structure 1004 of the connection, From core tile 101 to output lines QE0-QE3 Signal pad PV, PZ, PY, And PX can be supplied. I / O output interconnection By the line structure 1002, Signals from adjacent core tiles (north line N0-N7 for edge tile 103) , South Line S0-S7, And east lines E1-E5 and E7-E11), And long wire LH0-LH 7 and LV0-LV7 and double length wire DH0, It is possible to supply the signal to DH6 to the pad . The I / O output interconnect wiring structure 1002 has a nearly complete PIP distribution, Inside the chip The signal coming from the other point to the left edge tile 103, Left side from the rest of the tip Between the line leading to the edge tile 103 and the set of edge tile interconnect wiring lines M0-M15. Despite the loose normal interconnect wiring structure 1006, Pad PV, PX, PY, And PZ Lead to any of.   Intermediate interconnect wiring structure 1003 starts from one of the tile interconnect wiring lines M0-M15M0-M15 Guide the incoming signal to one of the edge tile input lines QIN0-QIN3, For the corresponding output lines Q0 to Q3 Guide through the buffer, Supply to corresponding lines TQ0-TQ3 via tri-state buffer block 302 It next, It is possible to supply signals to horizontal long lines LH0-LH7 and vertical long lines LV0-LV7. Can It In this way, the signals to the edge tile input lines QIN0-QIN3 are directly output lines Q0-Q3, Drive lines TQ0-TQ3 via tri-state buffer block 302.   In the feedback interconnection wiring structure 1005, the signals to the output lines Q0-Q3 are tile interconnection wiring lines. , Ie the north line N0-N7, South Line S0-S7, East Line E1-E11, Double length line DE0, DE6, DH0 and D Interconnect wiring line M selectively connected to H6 and connected to long lines LV0-LV7 Drive 0-M15. In this way The margin tiles 103 are 100 chips And a pad connection with external connection to the adjacent core tile 101 chip, And next to Allows connection to tangential edge tiles (or adjacent corner tiles detailed below). Pa Dead PV, PZ, PY, And PX are the pads P42 shown in FIG. 41, 40 and 39 respectively Show.   Figure 10B, 10C, And 10D is the margin tile 104, 105, And 106 respectively . These tiles have the same structure except for orientation and are the same references as shown in Figure 10A. Because the numbers are attached, Figure 10B, 10C, And interface structure shown in I0D Details of are not described here. I / O interface for optional pad   FIG. 10C shows a combination of connected and unconnected pads, Thereby mask Illustrate the flexibility that can be achieved at the level.   In this example, One unconnected pad PZ and connected pad PV, PY , PX is In FIG. 1, pad P6, P7 and P8 (connected to margin tile 105) ) Put the circuit layout shown in () into operation. As shown in Figure 1, A certain number on each edge tile Pad is connected. For example, Pad P17 is only connected to edge tile 106. It is one pad. Therefore, As shown in Figure 10D, Pad PV, PZ, PY, And And only one of the PXs (pad PV in this example) is connected to the margin tile 106. ing.   Returning to FIG. 10C, Pad PZ and its input / output buffer structure IOBZ are removed. And The entire chip is made smaller by reducing the total number of pads on the chip. Entering The force line IZ and the output line OZ are In an area that is outside the outer tile 105 in some embodiments. It is short-circuited. In this way All tiles 105, Pad PV, PZ, PY, And P Regardless of the number of X Layout in the same way. Returning to FIG. Pad P6, P7 and And P8 are connected to one marginal tile 105. In FIG. 10D, Pad PY and And related structures IOBY and ESDY are not provided. That is, The example of FIG. 10D is 2 represents the pads P26 to P28 of FIG. In another embodiment of the invention, Other pads Is four Are removed until the entire pad is removed. For example, Figure 1 shows all pad connections Includes some margin tiles that are not affected (two of the margin tiles 103, One of the margin tiles 104, And one of the edge tiles 105 has no pad. Not continued). Corner tiles   11A-11D show four corner tiles 113 of chip 100 (FIG. 1), 114, 115 and 116 are shown respectively. FIG. 11A shows IEEE 1149. Conventional boundary scan block BS conforming to 1 Including CAN. The block is located in Logistics, San Jose, California 95124. CK Drive 2100 located at Xilinx Inc. . Published by Luis Morales, Xilinx application note "X" Boundary Scan in C4000 Devices ", which is described here. Are incorporated herein by reference in their entirety. In Figure 11A, the upper left corner tile 113 is a fixed connection from the 1x Cho-East line E0-E7 to the 1x Cho-South line S0-S7 respectively, and Programmable connections from long horizontal lines LH0-LH7 to long vertical lines LV0-LV7 respectively including. In addition, FIG. 11A shows a programmable connection of the boundary scan block BSCAN. An example of an interconnect wiring structure 1101 for supplying a single-length wire and a long wire is shown. . Corner tile 113 is a program to external pin P43 which supplies global clock signal SGCK1. Including connection   The circuit layout of the corner tile 114 shown in FIG. 11B is the same as that of the corner tile 113 (FIG. 11A). Is one. More specifically, tile 114 (Fig. 11B) is 1x longer than the West Line W0-W7. Fixed connections that connect to the south south lines S0-S7 respectively, and long horizontal lines LH0-LH7 to long vertical lines LV 0-includes programmable connections to LV7 respectively. 11A and 11B In both, the long vertical line LV0 is connected to the long horizontal line LH0, but tiles 113 and Due to the layout of the Therefore, the corner tiles 113 and 114 have different appearances in FIGS. 11A and 11B. Corner The tile 114 includes a clock input pin P1 for supplying the clock signal SGCK4. Corner tiles 114 is a conventional oscillator / counter circuit used for bit counting during the circuit arrangement of the chip 100. Phases that provide programmable connections between DIVs and the above-mentioned single and long lines Includes interconnect wiring structure 1102. In one embodiment, the circuit DIV is on-chip Used during chip operation to provide an oscillator or counter divider. circuit DIV originates internally Circuitry is arranged to divide the oscillator signal or the user-supplied signal. Corner part File 114 is a boundary scan update signal, that is, an output of a portion of a standard boundary scan circuit (this Most of the circuitry is located in tile 113) and further includes signal BSUPD. In this embodiment , The signals BSUPD are West lines W2 and W3 (hence West lines S2 and S3) and Programmable on horizontal horizontal lines LH2 and LH3 (hence vertical vertical lines LV2 and LV3) Supplied in various forms.   FIG. 12 shows an embodiment of a circuit for implementing the oscillator / counter circuit DIV of FIG. 11B. Show. Two output taps OSCI and OSC2 are provided, and these oscillators are The circuit can be arranged to produce twelve frequencies which are frequency divided outputs. Internal oscillator OS C supplies the oscillator signal to NAND gate 1231. NAND gate 1231 is a memory cell OSCRU Enabled by N. When enabled, the output signal from the oscillator OSC is Supplied to the Luxplexer 1201.   In the memory cell 1202, the multiplexer 1201 provides the output signal from the internal oscillator OSC. Or signal to one of the 1x long west lines W0-W3 (the signal to the 1x long south line SO-SW and each Equal. (See Fig. 11B), or a signal to one of the long horizontal lines LH0-LH3 (long vertical) Supply equal to the signal on lines LV0-LV3). The multiplexer 1201 is It provides an output signal that is subjected to frequency division by lip flops 1214-1220.   Multiplexers 1225 and 1226 are the data inputs for flip-flops 1227 and 1228. Supply the division ratio selection input to the input terminals. The output of these flip-flops Are provided as signals to taps OSC1 and OSC2. Flip-flop 1227 and And 1228 are clocked from the original input signal and output from multiplexers 1225 and 1226. Reduce the skew of the output signal. The multiplexer 1225 is a memory cell OSC1A And under the control of OSC1B, the switching signal is divided by 4, 16, 64 or 256. A signal that can be an input signal from the multiplexed multiplexer 1201 is supplied. Memories Multiplexer 1204 is the original clock from multiplexer 1201 depending on the settings in module 1203. Can output lock signal output, or frequency division that is output from flip-flop 1213 A signal (the original frequency divided by 512) can be supplied. Multiplexer 1204 The original clock signal when the output signal of the multiplexer 1201 is set to be output. Are supplied from the multiplexer 1226 in the form of being divided by 2, 8, 32 or 128. The multiplexer 1204 is designed to supply the divided signal from the flip-flop 1213. Fixed 1212, the multiplexer 1226 determines the frequency of the original input signal to multiplexer 1201. The output is divided by 1024, 4,096, 16,384 or 65,536. in this way, The signals to the output taps OSC1 and OSC2 are tuned to oscillate at many different selected frequencies. Is programmed.   FIG. 11C shows the lower right corner tile 115. Corner tiles 115 are long horizontal lines LH0-LH7 and And long vertical lines LV0-LV7 are connected in a programmable manner, and the north line N0-N7 is connected to the west line. Connect to W0-W7. Corner tiles 115 are programmable interconnect wiring structures, Wachi start up block STARTUP on the north line N0-N7 (hence the west line W0-W7) and long hanging Programmably connect to straight lines LV0-LV7 (hence long horizontal lines LH0-LH7) Further included is an interconnect wiring structure 1103. Start-up block STARTUP sequentially arranges signals It controls the timing of the startup function that accompanies the start of operation of the chip 100 (FIG. 1).   During the start-up function, there are three things to do from the circuit layout mode to the operation mode. is necessary. That is, the signal is emitted to the global tri-state signal terminal GSR and the global reset Signal to the signal terminal GSR and signal to the load complete terminal DONE (all circuits Placement bit indicates that it was loaded in the proper location in the FPGA) . The start-up block STARTUP determines the sequence of emission of these signals and the timing of these signals. Imming (for example, one, two, or three clock cycles between each signal Allows the user to program (eg, separate).   Fig. 11D is constructed by connecting 1x long lines and long lines in the same way as the other three tiles. The lower left tile 116 is shown. The lower left corner tile 116 also includes a readback unit RDBK. Readback block RDBK allows the user to read the contents of the circuit layout memory to any data line. Read out to any external connection pin via the data line terminal of read-back unit RDBK. It is possible to do. The trigger terminal TRIG in the read-back unit RDBK is The same shift record that loads one row of data from the circuit layout memory into the circuit layout memory. It is for a signal that triggers copying to a register. Clock terminal The signal on CLK controls the shift out of the data on line DATA. Read middle edge The signal to the child RIP is the other from the trigger terminal TRIG during the data shift-out. To prevent the chip from sending the signal. In this circuit, to each part tile 116 The circuit layout data for the entire chip operates according to the initial circuit layout route of Shifted out of the chip to any one of the external pins.   Many other embodiments of this invention will be apparent to those skilled in the art from the foregoing description. Would. For example, the above description relates to an embodiment where the core tile is square or square. However, another embodiment includes a tile having six sides.   As mentioned above, the core tiles need not be identical. Different logical contents A set of tile designs can also be provided. If your tile design complies with common boundary constraints, Chips can be formed by combining various designs in various patterns. Good results To obtain, each tile design must have a good signal distribution within the tile. The tile routing matrix efficiently splits incoming signals to logic block input terminals. Must be spread and the logic block output signal must be directed to the tile perimeter. RAM memo There are tiles that do not include logic but only route, and route without logic and memory Some tiles include means. In addition, a tie that physically contains the input / output pads inside. Can also be designed, and its padded tile design achieves distributed access to logic Can be combined with other tile designs. The other embodiments are also the present invention. Is intended to be included within the scope of. This invention is described in the claims. To do.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, M C, NL, PT, SE), JP (72) Inventor Horen, Victor A.             United States California             95070 Saratoga, Short Hill Co             14000

Claims (1)

[Claims] 1. An FPGA structure with multiple core tiles, where each core tile is   A circuit block flexible logic block matrix,   Programmable routing matrix,   The above-mentioned circuit arrangement flexible logic block is used to accommodate another circuit arrangement in an adjacent core tile. Connection means for connecting to a logical logic block matrix,   The circuit layout flexible logic block is connected to the programmable routing matrix. Inter-matrix connecting line connecting to the   Program the programmable routing matrix in adjacent core tiles With routing lines that connect to possible routing matrices FPGA tile structure containing. 2. The FPGA tile structure according to claim 1, wherein the core tiles are identical to each other. 3. The FP of claim 1, wherein one core tile is different from another core tile. GA tile structure. 4. The adjacent core tiles are located on the north, south, east, and west sides of the core tiles. The FPGA tile structure according to claim 1. 5. Further comprising a plurality of elongated lines extending horizontally through the core tile, At least one of the plurality of long wires is at least one of the inter-matrix connecting wires. The FPGA tile structure of claim 1 coupled to. 6. Further comprising a plurality of elongated lines extending vertically through the core tile, At least one of the plurality of long wires is at least one of the inter-matrix connecting wires. The FPGA tile structure of claim 5 bonded to. 7. The circuit arrangement flexible logic block matrix and the programmable 7. The method of claim 6 further comprising a global horizon coupled to the active routing matrix. FPGA tile structure. 8. The circuit arrangement flexible logic block matrix and the programmable 8. The method of claim 7, further comprising a global vertical line coupled to the active routing matrix. FPGA tile structure. 9. A multi-length line is further included, the multi-length line not being in the adjacent core tile. 9. The FPGA tile structure of claim 8 having a grammable routing matrix associated with it. Build. Ten. The FPGA tile structure according to claim 9, wherein the various long lines are double length lines. 11. The connecting means includes a carry output line and a carry input line, and the carry output line The FPGA tile of claim 1 in which is coupled to a carry input line in an adjacent core tile. Construction. 12. The carry input line is coupled to a carry output line in an adjacent core tile. The FPGA tile structure according to item 11. 13. The connection means is   A plurality of input lines to the circuit layout flexible logic block matrix;   A plurality of output lines from the circuit layout flexible logic block matrix; Wherein at least one of the plurality of input lines is in the plurality of outputs in adjacent core tiles. Coupled to one of the force lines and at least one of the plurality of output lines is in an adjacent core tile Is coupled to one of the plurality of input lines of The FPGA tile structure according to claim 9. 14. The circuit layout flexible logic block matrix   Programmably connect to the plurality of input lines through an input interconnection wiring structure Multiple logic block input lines,   Programmably connect to the plurality of output lines through an output interconnection wiring structure Multiple logic block output lines 14. The FPGA tile structure of claim 13 including. 15． The circuit layout flexible logic block matrix is used for the plurality of logic block matrices. Circuit layout flexibility coupled between the input line and the plurality of logic block output lines. 15. The FPGA tile structure of claim 14, further comprising a logic block that includes: 16. The output interconnection wiring structure has more interconnections than the input interconnection wiring structure. 16. The FPGA tile structure of claim 15 having a sequency distribution. 17． The FP of claim 16, wherein the input interconnect structure has a sparse interconnect distribution. GA tile structure. 18. 18. The FPGA of claim 17, wherein the output interconnection structure has a sufficient distribution of interconnection points. Tile structure. 19. The circuit layout flexible logic block matrix connects the output lines to the logic Additional feedback interconnect wiring structure for programmable connection to block input lines 16. The FPGA tile structure of claim 15 including. 20. The circuit layout flexible logic block matrix is the matrix indirect. Conventional interconnections that connect the connection to the logic block input lines in a programmable manner 20. The FPGA tile structure of claim 19, further comprising a wiring structure. twenty one. 21. At least one of the inter-matrix connection lines includes a buffer. FPGA tile structure. twenty two. The circuit layout flexible logic block includes a plurality of function generators, The number generators are each coupled to a subset of the logic block input lines. 20 FPGA tile structure. twenty three. The circuit layout flexible logic block includes a plurality of multiplexers, At least one of the plurality of function generators includes at least one of the plurality of multiplexers; 23. The FPGA tile structure of claim 22, which provides a signal to one. twenty four. The circuit layout flexible logic block further comprises a plurality of register means, At least one of the plurality of multiplexers is at least one of the plurality of registers. 24. The FPGA tile structure of claim 23, which supplies signals to one. twenty five. At least one function generator is coupled to one logic block output line The FPGA tile structure of claim 24. 26. At least one multiplexer connected to one logic block output line 26. The FPGA tile structure according to claim 25. 27. A contract in which at least one register is coupled to one logic block output line. FPGA tile structure according to claim 26. 28. At least one multiplexer is coupled to the carry output line The FPGA tile structure according to Item 27. 29. At least one multiplexer is coupled to the carry input line. The FPGA tile structure according to Item 28. 30. The circuit layout flexible logic block further includes a group of multiplexers. Each of these multiplexer groups is coupled to one of the plurality of function generators. FPGA tile structure according to claim 22. 31. The circuit layout flexible logic block further comprises a plurality of register means, 30. Each multiplexer group supplies a signal to one of the plurality of register means. The described FPGA tile structure. 32. The method of claim 31, wherein each function generator is coupled to one logic block output line. FPGA tile structure. 33. At least one multiplexer in each multiplexer group is a logic block. 33. The FPGA tile structure of claim 32 coupled to an output line. 34. The FP of claim 33, wherein each register is coupled to one logic block output line. GA tile structure. 35. At least one multiplexer of the circuit layout flexible logic block The FPGA tile structure of claim 34 coupled to the carry output line. 36. At least one multiplexer of the circuit layout flexible logic block 36. The FPGA tile structure of claim 35 coupled to a carry input line. 37. The output interconnection wiring structure includes a first plurality of transistors, each transition 21. The FPGA tile structure according to claim 20, wherein the star is provided for one logic block output line. Build. 38. The output interconnect wiring structure includes a first plurality of memory devices, each memory 36. A device controls the state of a subset of the plurality of transistors. FPGA tile structure. 39. The output interconnection wiring structure includes a second plurality of transistors, the second plurality of transistors Each of the plurality of transistors of the plurality of transistors is associated with a subset of the plurality of logic block output lines. 39. The FPGA tile structure of claim 38 coupled between two output lines. 40. The output interconnect wiring structure controls the state of the second plurality of transistors. 40. The FPGA tile structure of claim 39, further comprising a second plurality of memory devices that include: 41. The input interconnection wiring structure and the normal interconnection wiring structure are a first plurality. Of transistors, the first plurality of transistors being the plurality of matrices. Contracts provided for a subset of inter-connector lines and a subset of the plurality of input lines. FPGA tile structure according to claim 20. 42. The input interconnection wiring structure and the ordinary interconnection wiring structure are the first interconnection wiring structure. A contract including at least one memory device for controlling the states of a plurality of transistors The FPGA tile structure according to claim 41. 43. The input interconnection wiring structure and the normal interconnection wiring structure are a second plurality. Of transistors and each of the second plurality of transistors comprises a plurality of transistors. With a subset of inter-trix connection lines or an additional subset of said plurality of input lines The FPGA tile structure of claim 41 coupled to one logic block input line. Build. 44. The input interconnection wiring structure and the normal interconnection wiring structure are the second interconnection wiring structure. Further comprising a second plurality of memory devices controlling the states of the plurality of transistors of the The FPGA tile structure according to claim 43. 45. The programmable routing matrix routes the routing lines to the matrix. 21. Includes a programmable interconnect wiring structure that couples to inter-ix connection lines. Installed FPGA tile structure. 46. The programmable interconnect wiring structure runs horizontally through the core tile. 45. The plurality of elongated lines extending further coupled to the inter-matrix connecting lines. The described FPGA tile structure. 47. The programmable interconnect wiring structure extends vertically through the core tile. 47. The plurality of elongated lines extending further coupled to the inter-matrix connecting lines. The described FPGA tile structure. 48. The programmable interconnect wiring structure comprises the multi-type long lines in the matrix. 48. The FPGA tile structure of claim 47, further coupled to inter-connect lines. 49. The programmable interconnect wiring structure connects the global horizon to the matrix. 49. The FPGA tile structure of claim 48, further coupled to inter-line connection lines. 50. The programmable interconnect wiring structure connects the global vertical line to the matrix. 50. The FPGA tile structure of claim 49, further coupled to an interline connection line. 51. Before the long lines, ie, extending horizontally or vertically across the core tiles At least one of the long lines includes a long line divider, and the long line divider is The FPGA tile structure of claim 6 including means for blocking the conduction of at least one long line. . 52. 52. The FPGA tile structure of claim 51, wherein the means for blocking conduction comprises a transistor. Build. 53. 53. The FPGA tile structure of claim 52, wherein the transistor is an n-type transistor. . 54. Further including a plurality of edge tiles, each edge tile having at least one other edge edge The FPGA tile structure of claim 20 combined with a tile and a core tile. . 55. The edge tiles are further coupled to input / output (I / O) devices. FPGA tile structure described in 4. 56. The I / O device is connected to a pad that provides an external connection to the chip 56. The FPGA tile structure of claim 55. 57. The FPGA tile of claim 56, wherein an electrostatic discharge device is connected to the pad. Construction. 58. The edge tile connects the I / O device to the routing line, the input line, and the output line. 57. The FPGA tile structure of claim 56 including force lines and means for connecting to said multi-length lines. . 59. The coupling means connects the global horizontal line or the global vertical line to the I / O device. 59. The FPGA tile structure of claim 58, which is bonded. 60. 57. The FPGA tile structure of claim 56, wherein said coupling means comprises a first interconnect wiring structure. Build. 61. It further includes a plurality of corner tiles, each corner tile touching two adjacent edge tiles. 55. The FPGA tile structure of claim 54, which is continued. 62. The plurality of elongated strips in which the corner tiles extend horizontally across the core tiles. Connecting a line to the plurality of elongate lines extending vertically across the core tile. The FPGA tile structure according to Item 61. 63. The corner tiles define a first subset of the plurality of routing lines into the plurality of tracks. 62. The FPGA tile structure of claim 61, further connecting to a second subset of route indicators. 64. The plurality of elongated strips in which the corner tiles extend horizontally across the core tiles. A line and the first subset of the plurality of routing lines to a selected circuit. 62. The FP of claim 61 including a corner tile interconnect wiring structure that connects in a grammable manner. GA tile structure. 65. The FPGA tile structure of claim 64, wherein the selected circuit is a boundary scan block. Build. 66. 66. The FPGA tile of claim 64, wherein the selected circuit is an oscillator / counter circuit. Construction. 67. The FPGA tile structure of claim 64, wherein the selected circuit is a startup block. . 68. 65. The FPGA tile structure of claim 64, wherein the selected circuit is a readback unit. . 69. The margin tiles are smaller than the long lines that extend horizontally across the core tiles. Claims further comprising means for programmable connection of external pins to at least one The FPGA tile structure according to Item 61. 70. Logic block matrix and programmable, each with flexible circuit layout A plurality of paired constructions including different routing matrices,   The circuit layout flexible logic block matrix A plurality of connecting lines that connect to the route matrix,   The programmable routing matrix can be used for other programs in other pair constructions. Ramable routing matrix and FPGA tile structure containing. 71. The circuit arrangement flexible logic block matrix in one pair configuration structure The logic block matrix capable of arranging a plurality of circuits in another pair structure is provided with the program. Further includes means for connecting without using a Gramtable Routing Matrix 71. The FPGA tile structure of claim 70. 72. The means for connecting is   The first programmable routing matrix to the adjacent programmable routes A plurality of single length lines connected to the instruction matrix,   Non-adjacent programmable of the first programmable routing matrix Multiple double-length lines that connect to different routing matrices 71. The FPGA tile structure of claim 70, including. 73. Programmable into multiple contiguous programmable routing matrices, each Multiple long wires that can be connected in any suitable form 71. The FPGA tile structure of claim 70, further comprising: 74. Multiple signal lines,   A first plurality of transistors provided for each signal line;   At least one memory device for controlling the states of the plurality of transistors; ,   A second plurality of transistors each connected to a subset of the first plurality of transistors. A transistor,   The states of the second plurality of transistors are compared with those of the second plurality of transistors. Means to control to determine which provides the signal to the output line Interconnect wiring structure including. 75. A third connected in series to a subset of the first plurality of transistors 75. The interconnect wiring structure of claim 74, further comprising a plurality of transistors of. 76. The at least one memory device includes a plurality of memory devices, each memory device 75. A memory device controls the state of one of the third plurality of transistors. The interconnection wiring structure described. 77. The plurality of memory devices send signals to the first plurality of transistors; 77. The complement of the signal is provided to a third plurality of transistors, respectively. Interconnect wiring structure. 78. Multiple signal lines,   A first plurality of transistors provided for each signal line;   The state of the first plurality of transistors is changed to the first state of the first plurality of transistors. Supplying a signal to a group of one of the second plurality of transistors of the first plurality of transistors. A first memory device controlling the group to provide the complement of that signal;   A second plurality of transistors, each coupled to a subset of the first plurality of transistors. A transistor,   The state of the second plurality of transistors is changed to the state of the second plurality of transistors. Supplying a signal to a group of one of the second plurality of transistors A second memory device controlling the group to provide the complement of that signal;   A third plurality of transistors each connected to a subset of the second plurality of transistors. A transistor,   The state of the third plurality of transistors is changed to the state of the third plurality of transistors. Supplying a signal to one group to the second group of the third plurality of transistors Third memory device controlling to provide the complement of the signal And one of the third plurality of transistors produces a signal on the output line. Continued wiring structure. 79. It has a tiled FPGA structure,   Logic block matrix and associated program, each of which is flexible in circuit layout Multiple core tiles formed in rows and columns containing possible routing matrices When,   A plurality of core tiles formed on the north, east, south and west sides of the core tiles. Margin tiles,   A plurality of corner tiles formed adjacent to the plurality of edge tiles; Tile-type FPGA structure including. 80. The core tile and the marginal ties formed around the north and south sides 80. The tile type of claim 79, further comprising a plurality of horizontal elongated lines extending through each row of FPGA structure. 81. The core tile and the marginal ties formed around the east and west sides 81. The tile type of claim 80, further comprising a plurality of vertical elongated lines extending through each row of FPGA structure. 82. The water extending through the margin tiles formed around the north and south sides Through each row of the margin tiles where a flat long line is formed around the east and west sides The vertical tiles that extend are joined by the plurality of corner tiles. The tiled FPGA structure described in 81. 83. Each core tile, edge tile, or corner tile has at least two lines Contains, one corner tile contains the north line joined to the east line, and another corner tile Includes the south line connected to the east line, and another corner tile is the west line connected to the south line And another corner tile includes a north line joined to the west line, said south side One of the perimeter tiles on the periphery includes the north line joined to the east and west lines, Another edge tile of a side includes an east line joined to a north line and a south line, said north side Another peripheral edge tile includes a south line joined to the east and west lines, said east line Yet another edge tile around the side includes the east line joined to the north and south lines , The core tiles include the north line joined to the east, south, and west lines, The east line of the marginal tile in which the west line is formed around the north side or the south side And the east line of the corner tile is formed around the north side or the south side. Joined to the west line of the edge tiles, and the south line of the corner tiles to the east side. Was Is connected to the north line of the edge tiles formed on the west side, and is in front of the corner tiles. The north line is on the south line of the marginal tiles formed around the east side or the west side. The south line of the edge tiles that are combined and formed around the north side is the core tile. The west line of the marginal tiles formed on the east side is connected to the north line and the west line is the core tile. Is connected to the east line of the, and the north line of the edge tiles formed around the south side is the core The east line of the marginal tile that is joined to the south line of tiles and is formed around the west side 83. The tiled FPGA structure of claim 82, wherein is bonded to the west line of the core tile. 84. Each edge tile includes a normal interconnect wiring structure, and the plurality of horizontal long lines and front Note that at least two wires are programmable in the usual interconnection wiring structure. 84. The tiled FPGA structure of claim 83 connected. 85. Further comprising at least one pad, the at least one pad being bordered 85. Programmably connected to the conventional interconnect wiring structure of tiles. The tiled FPGA structure shown. 86. A plurality of pads are further included, each pad including the conventional interconnect arrangement of the edge tiles. 86. The tiled FPGA structure of claim 85 connected programmably to a line structure. 87. The at least one pad is connected to the normal phase via a pad interconnection wiring structure. 86. The tiled FPGA structure of claim 85, wherein the tiled FPGA structure is programmablely connected to the interconnect wiring structure. Build. 88. Both the regular interconnect wiring structure and the pad interconnect wiring structure are 88. The tiled FPGA structure of claim 87, including programmable interconnect points (PIPs). 89. The pad interconnect wiring structure has more PI than the normal interconnect wiring structure. 89. The tiled FPGA structure of claim 88, comprising P. 90. 89. The pad interconnect wiring structure comprises PIP substantially entirely. Tiled FPGA structure. 91. The tag of claim 90, wherein the conventional interconnect wiring structure sparsely comprises the PIPs. Ill-type FPGA structure. 92. A method of forming a tiled FPGA structure comprising:   A process for forming a flexible logic block matrix in a core tile. When,   Forming a programmable routing matrix within the core tile,   The circuit layout flexible logic block matrix and the programmable The process of combining different routing matrices,   The circuit layout flexible logic block matrix to a circuit in a proximity core tile A process of connecting to a logical block matrix with configuration flexibility,   The programmable routing matrix is added to another core tile The process of binding to a Gram-enabled routing matrix and Including the method. 93. The other core tile is the programmable path within the core tile. 93. The method of forming a tiled FPGA structure of claim 92 adjacent to an instruction matrix. 94. The other core tile is the programmable path within the core tile. 93. A method of forming a tiled FPGA structure according to claim 92, which is not proximate to an instruction matrix .