JPH08502609A - Non-numeric coprocessor - Google Patents

Abstract

(57) [Summary] The non-numerical coprocessor for fuzzy information retrieval and pattern recognition has information processing means and can be connected to a host computer and a data source. Internal processing elements are organized in a number of simultaneously operable window modules (W0, W1, ...) Arranged for examining the data stream from the data source. The processing element compares a byte of the data stream with predetermined upper and lower limits to determine if the byte is within the bounds and, if so, generates a hit signal. Each window module has window matching logic for correlating the hit signals from its different processing elements and produces a window matching signal upon the occurrence of a predetermined match. By configuring the coprocessor in this way, it is possible to transfer a separate data stream to individual window modules or chained window modules that are selectably configured as window groups or super windows, depending on the needs of the application. , The parallel processing capacity available by the data routing means (12) is obtained.

Description

Description: TECHNICAL FIELD The present invention relates to a non-numerical coprocessor for fuzzy information retrieval and pattern recognition using an electronic computer. BACKGROUND ART Conventional computer systems can be used to describe, store, recognize and retrieve information using complex programming and data organization techniques. However, by using such a known method, the system performance often deteriorates remarkably, especially in tasks such as complicated information item search and complex pattern recognition. Through information retrieval, text and database searching, and pattern matching, most computer users have faced well-known problems resulting from the inefficiencies of conventional approaches to non-numerical computation. For example, a huge amount to respond to a query of the type "find all dates and locations where cadmium was measured between 1980 and 1985, where phosphorus concentrations were measured above 15 μg / l". Reading a measurement of or even a much simpler query can cause severe performance problems in conventional systems. Inspired by human behavior that retrieves large amounts of information and recognizes complex items therefrom, the present invention seeks to eliminate the gap between traditional method-based systems and today's performance requirements. . Accordingly, it is an object of the present invention to provide simple non-numerical programming while at the same time scanning large volumes of data substantially faster than conventional non-numerical computing systems and slower to find certain complete sentences. Or to provide the ability to search for complex combinations of many word fragments. Further, the present invention seeks to eliminate the need for extended segmentation, vectorization, and duplicate storage of data to search for complex information items, which is often required when employing conventional techniques. To do. In the present disclosure, a "byte" should be construed as a series of contiguous bits treated as a unit, and the number of bits is not necessarily eight. DISCLOSURE OF THE INVENTION According to the present invention, the problem faced by the prior art is a non-numeric coprocessor for fuzzy information retrieval and pattern recognition, which has information processing means and is connectable to a host computer and a data source, The information processing means comprises a plurality of internal processing elements organized within a predetermined number of simultaneously operable window modules arranged to examine a data stream from said data source, each processing element being within the data stream. 1 byte, for example an 8-bit byte, of the byte is present within the boundary value by comparing the predetermined individually programmable upper and lower limit values assigned to the processing element with each other. If it is within the boundary value, generate a hit signal to be sent to the window matching logic circuit provided in each window module, It is solved by a coprocessor which correlates with hit signals received from different processing elements in the window module and further generates a window match signal by the occurrence of a predetermined match in the window module. This coprocessor configuration provides powerful parallel processing capabilities that can be used to provide coprocessor systems with performance far exceeding that of conventional systems for information retrieval and pattern recognition. . The coprocessor according to the invention preferably further comprises a separate data stream from said data source to said simultaneously operable window module individually in response to configuration data corresponding to the needs of the application. Alternatively, the window module comprises data routing means for transferring in a manner that is chained to different selectable window configurations such as individual super windows or groups of super windows or a single super window containing all window modules. By chaining windows into longer windows, more complex search conditions can be accommodated, and the routing of input data to different windows is required for the window length and data stream of the currently executing application. Depending on the method, it can be done in several ways. In fact, within the limit of the number of available windows, any number of streams of 1 byte each can be processed. For example, a number of individual data inputs, each preferably eight bits long, can be transferred to different windows for parallel processing, and the same data stream needs to be duplicated when processed by different windows. Disappears. Thus, the coprocessor according to the present invention has a flexible and configurable data routing function and also supports the use of the processor in applications of 64 bits or less in length. Preferably, the data routing means comprises a network of multiplexers organized at different levels, each multiplexer being able to select one of two data inputs, each preferably eight bits long, and transfer it to its output. . In particular, in the preferred embodiment of the coprocessor, the multiplexer levels comprise folding, parallel, and serial multiplexer levels, respectively. The coprocessor further comprises a static random access memory (RAM) for internal storage of the window structure which can be loaded into the coprocessor. This eliminates the need to transfer configuration data to the coprocessor for each search operation (necessary to transfer only if the configuration is changed), which is advantageous for developing software that includes a personalized set of downloadable configuration data. In one embodiment of the coprocessor, each processing element comprises a latch cell for temporary storage of a byte to be tested and two comparator cells with the upper and lower limits for the processing element. The cell is configured to generate a hit signal. Further provided in the coprocessor is result control logic configured to receive the window match signal and compare it to a programmable central hit mask, the central hit mask defining a logical combination of window hits, and It is preferable to have the addresses of all detected occurrences reported (hit address mode) or the total number of matches in the examined data volume (hit count mode). The convenience of programming and controlling the coprocessor, and further advantages and features of the coprocessor, will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in detail with reference to the accompanying drawings, on the basis of an example of a preferred embodiment of a coprocessor according to the present invention. FIG. 1 shows a typical application of a coprocessor according to the invention. FIG. 2 is a block diagram of a coprocessor according to the present invention connected to a host computer and a data source. FIG. 3 is a diagram showing a single window within a coprocessor according to the present invention. FIG. 4 is a diagram showing a single processing element of a window in a coprocessor according to the present invention. FIG. 5 shows a data routing network within a coprocessor according to the present invention. 6 to 15 show various preferred configurations of the data routing network within the coprocessor according to the present invention. 16 to 17 detail the flow of data through the routing network in the coprocessor according to the two different configurations shown in each of FIGS. 7 to 16. FIG. 18 shows a typical host / coprocessor configuration. FIG. 19 shows the address map organization within the coprocessor. FIG. 20 shows a portion of the window for a given example application. Description of the Preferred Embodiments As shown in FIG. 1, a coprocessor chip 1 according to the present invention generally comprises a bidirectional data transfer link to a host computer 2 and a unidirectional data transfer link. It is connected to the data source 3. The preferred embodiment of coprocessor chip 1 comprises a series of eight window modules W0-W8, as shown in FIG. These data modules W0-W8 are logically located between the data router module 12 and the result control logic circuit 13 which are interconnected via an 8-bit data bus connected to the host interface module 14. ing. The data source interface module 15 performs one-way 64-bit data transfer from the data source 3 to the data router module 12. Referring now to FIG. 3, each of the eight data window modules W0-W8 has a window matching logic circuit 16 and a 32-byte shift register corresponding to 32 processing elements PE0-PE31. As shown in FIG. 4, each processing element PE is divided into a latch cell 17 and two comparator cells 18, 19 associated with each other to check individually programmable upper and lower limits. As shown in detail in FIG. 5, each window can be chained to a longer window via the data routing network in the data router module 12, allowing more complex data retrieval. The data router is composed of a 3-level multiplexer, and selects and outputs one of two 8-bit length inputs. The first level multiplexer, which is supplied with an 8-bit long data stream from the data source, consists of a folding multiplexer (upper multiplexing row in FIG. 5), i.e. a multiplexer that folds the data stream in a circle. Each window can be independent of the location where the actual data stream enters the coprocessor chip. The folding multiplexer is connected to a parallel multiplexer (the central multiplexing row in FIG. 5) that duplicates the data stream and simultaneously reads the same data stream in different windows. Finally, the serial multiplexer (the lower multiplexing row in FIG. 5) chooses whether or not each window should be chained to the superwindow. These three multiplexer levels allow input combinations and window chains. Hereinafter, a part of the possible configurations will be described with reference to FIGS. 6 to 17. The input data streams are assigned codes 0 to 7, for example, the stream 0 corresponds to D (7,0) and the stream 1 corresponds to D (15,8). a) Each of the eight data streams is supplied to each window arranged in parallel. This is the simplest routing strategy. Each stream is sent to the corresponding window. This configuration is shown in FIG. 6 and the actual configuration is shown in detail in bold in FIG. b) Supply each of the four data streams to two windows arranged in parallel. Each data stream is paired and sent to two windows arranged in parallel. The streams can be every other dataset 0, 2, 4, 6 or datasets 1, 3, 5, 7, eg stream 0 is followed by stream 1. This configuration is shown in FIG. c) Feed each of the four data streams to two windows arranged in series. This configuration is similar to b), except that each pair of windows is concatenated to form one superwindow of double length. This configuration is shown in FIG. d) Each of the two data streams is supplied to four windows arranged in parallel. The streams are combined in groups of four and sent to two sets of four windows arranged in parallel. The streams can alternately be (0, 4), (1, 5), (2, 6) or (3, 7), eg stream 0 followed by streams 1, 2, 3 Next to 4, streams 5, 6, and 7 are arranged. This configuration is shown in FIG. e) Feeding the two data streams respectively into two groups of parallel windows consisting of two windows arranged in series. As in d), the windows are chained, but the parallelism is reduced. This configuration is shown in FIG. 10, and in FIG. 17 the input streams 2 and 6 and the actual configuration are shown in detail in bold type. f) Each of the two data streams is supplied to four windows arranged in series. This configuration is similar to the configuration of d) except that the windows of each group are linked so as to form one super window that is four times the length of each window. This configuration is shown in FIG. g) Supply one data stream to eight windows arranged in parallel. Each data stream is combined to form one stream and sent to eight windows arranged in parallel. Any of the eight streams can be used as input, treating the entire data storage area as one long 8-bit data file. This configuration is shown in FIG. h) Feeding one data stream to four groups of parallel windows consisting of two windows arranged in series. Similar to g), but each window is chained for a more complex search. This configuration is shown in FIG. i) Supply one data stream to two groups of parallel windows consisting of four windows arranged in series. Similar to g) and h), but chaining more windows to increase complexity. This configuration is shown in FIG. j) One data stream is supplied to eight windows arranged in series. Similar to g), but connects all windows to form a single super window, allowing the most complex searches. This configuration is shown in FIG. Alternative filter and data path configurations are determined by the configuration data loaded into the chip. All configurations are capable of 10 gigabytes of single byte comparisons per second with data routing. However, by trading off the number of simultaneous data paths, complex queries are made, which facilitates mapping a large number of applications on a chip. The coprocessor 11 is typically linked to a computer via a host interface 14, as shown in FIG. The illustrated host computer comprises a disk unit 21, a disk controller 22 associated therewith, a central processing unit or CPU 23, a system memory 24 and a system bus 25. The host interface 14 is based on an 8-bit bidirectional port (HD bus) and read / write cycles are executed synchronously and asynchronously. The host interface itself is controlled by the assertion of the IOR and IOW signals in combination with the CS signal and the specific polarity on the SETA DR line (see Figure 2). The configuration data is stored in the configuration RAM and consists of a total of 828 bytes, enabling a complete reconfiguration within about 100 microseconds. In most systems, the configuration time is determined by the transfer rate from the host computer. When the input / output channel of a personal computer is used, assuming that the transfer rate is IMB / sec, it generally takes 1000 microseconds. Minor changes to the configuration data are made by addressing through an internal address register of the coprocessor, which can further reduce the configuration time. Thus, the reconstruction and the search are performed very quickly, making it possible to search for equal amounts of data on different criteria. In counting mode, the coprocessor accumulates the number of matching data items found on the chip. In reporting mode, the coprocessor issues an interrupt signal when it detects a hit. This signal continues to be sent until the host computer issues an ACK signal or an IOW signal. The internal result position counter is housed in a shadow register (not shown). The configuration data determines whether the chip should stop receiving data if a hit occurs. If the chip is configured to stop the data stream, the DWTD signal (see Figure 2) will be inactive until the ACK signal is sent. If the data stream is programmed to flow uninterrupted despite a match, the counter contained in the shadow register will not be overwritten until the ACK signal is sent. This is advantageous for text searching when hits frequently occur on the text portion containing the desired data. Also, if the problem occurs only in the legitimate part of the text (chapter, section), it is not appropriate to seek an exact detection of its occurrence within that part of the text. The 64-bit synchronous data interface 15 (see FIG. 2) is controlled by a simple handshake procedure. When the coprocessor is ready to receive data, the DWTD signal is sent one clock cycle before the actual data is read. This makes it possible to ensure more appropriate timing when designing the interface. When the data source is ready with data, it issues a DVALID signal. If the DWTD signal was inactive at the last rising clock, the sending of the DVALID signal prevents the data from being read by the coprocessor. Therefore, after sending the DWTD signal and detecting the rising clock edge, the data source should not consider the data transfer completed until it detects the data and the DVALID signal during the first rising clock. Corresponding timing schemes can be implemented for such synchronous and asynchronous read / write functions. If the input stream contains data that is to be interpreted as a numeric value that spans more than one byte, the most significant byte must reach the first in the window. Programming of the chip is done by writing configuration data to different addresses in the host interface. The different parts of the configuration are indirectly addressable. As a result, only a part of the configuration can be changed in a very short time if necessary. It is not necessary to stop the data stream during the reconfiguration, but false matches may occur due to the transient condition that occurs when the configuration is partially written. Also, since the record counter is reset by writing to the corresponding window, problems may arise in the case of misaligned records. Therefore, it is desirable to stop the data stream before changing the configuration. The internal configuration address in the coprocessor consists of the 11-bit address ADR (10,0), which is generated in the internal address register. The eight high-order bits of this register can be loaded via the host interface. The three lower bits are cleared when the upper bits are loaded. Loading is done by setting address bits on the HD bus and sending CS, IOW and SETADR signals simultaneously. The organization of the 11-bit address is shown in FIG. The coprocessor comprises twelve internal modules, each with its own address. The module address consists of the four upper bits in the address and is changed only by writing a new value from the HD bus. The module base address is shown in Table 1. The 7 low-order bits are held in the counter and incremented for each access from the host interface. Thus, in-order bytes within a module can be easily accessed. Module address auto-incrementing is not supported due to holes in the address map between modules. In most modules, offset addresses can be used for more detailed addressing. To access a single byte, the absolute address is calculated as: Address = (module address ^* 128 (10)) + Offset Address Next, the address register is loaded with a value via the HD interface and then accessed to autoincrement the address register. Read access is easiest because it requires no knowledge of the previous configuration. Each window module consists of:・ Lower limit 32 bytes ・ Upper limit 32 bytes ・ Field delimiter (separator) mask 32 bytes (all bytes, only the least significant bit is important) ・ Match waiting time value 2 bytes ・ Record length value 1 byte Offset for these registers The addresses are shown in Table 2 below. In the actual search, the limit register is loaded with the appropriate value. The field delimiter mask takes 1 at the least significant byte position of each field. Note that the field delimiter mask uses only the least significant bit of each byte. That is, a 1 is written to the delimiter mask byte that matches the processing element PE, and otherwise the last byte of the field is held at 0. The match latency is the number of clock cycles required for the window to perform a hit. Zero match latency means that the hit is reported from the window to the central match logic during the clock cycle that caused the hit. When the matching waiting time is 4, for example, it means that the matching is reported after 4 more cycles, that is, within a total of 5 cycles. The value written in the matching waiting time register is 65535 (10) -the waiting time. That is, for example, the matching waiting time 4 is specified by writing the value 65531 (10) in the register. The routing of the data streams all take the same amount of time, so if the data streams are input to the chip at the same time, the data streams will occur simultaneously at the input of each window (or the first window of the chain). Sending the stream through the chain window introduces a cumulative delay of 32 cycles, which should be taken into account when calculating the match latency. A clock cycle with no data transfer, that is, an inactive DVALID signal does not affect the number of waiting cycles. Therefore, the match latency is measured for data transfers, not physical clock cycles. The record length is used to suppress hits by occasionally matching patterns that do not match record boundaries. By setting the record length to 1, all hits are reported to the central match logic. When the record length is 6, for example, only the matching performed in the sixth data transfer is reported from the window. The byte counting window is reset by every write operation using the module address corresponding to that window. That is, the first executable match is performed for the sixth data transfer after writing the window configuration. The record length value is programmed into the corresponding register in the coprocessor as 256 (10) -record length. Therefore, a record length of 10 (10) is written as 246 (10). The 256-bit hit mask RAM is organized as 32x8 bits as can be seen from the host interface. This 32 bytes is selected by the 5 low order bits in the internal address register, leaving bits 5 and 6 as "don't care" and bits 7 through 10 as the module address 1000 (2). Writing to byte address 0 affects bits 0 through 7 in the 256-bit addressing scheme, the least significant bit in the byte corresponds to bit position 0. Similarly, writing to byte address 4 affects bits 32-39 of the 256-bit addressing scheme. Each window addresses the RAM as 256 x 1 bit. The match signal from the eight windows is used as the address, and the match signal from window 0 represents the least significant address bits. A hit is detected when a 1 is stored in the real location. The module consisting of mode register, result counter, hit pattern, and version register does not have an internal offset address, but is organized as a serial read shift register chain. All writes to this module occur in the mode register, the only writable register in the chain. This affects how the coprocessor acts on hits. In this case, only the 3 lower bits are made to function, and 0 is always written to the other bits. Table 3 describes the mode bits. These bits result in eight combinations of operations, all described in Table 4. When reading from this module, the values are presented in the following order: 1. Result counter, byte 3 (most significant byte) 2. Result counter, byte 2 3. Result counter, byte 1 4. Result counter, byte 0 (least significant byte) 5. Hit pattern 6. Mode 7. All registers, except the version number mode register, are read-only. Not all values need to be read after the first read has started. Sending an ACK or IOW signal to the coprocessor overwrites the value of the result counter and hit pattern with a new hit and accesses the most significant byte of the result counter to initiate a new read (IOW signal is CS Must be qualified with the signal). This is also valid when the INT signal is not transmitted. The result counter counts the number of hits or data transfers that have occurred since the last write to the mode register. Therefore, writing any value to this module will clear the result counter. The counter is 32 bits long and does not exhibit a counter overflow indicator. The hit pattern is the matching pattern reported from each of the eight windows at the last hit. This can be used when programming the hit mask RAM to generate hits for some matching patterns. The pattern that actually caused the hit is read to provide more information that facilitates post-processing. The version register contains a number indicating the version of the current coprocessor. It will be used in later revisions to allow the software to fit into current hardware. The data router configuration module is organized as a shift register with level depth 3 and length 1 byte. These are the bytes that control the multiplexer previously described with reference to FIGS. Each byte is read and written in the following order. 1) Serial multiplexer 2) Parallel multiplexer 3) Folding multiplexer The read operation is destructive. That is, all multiplexer configuration data must be rewritten after being read. However, this is not very important since the multiplexer configuration is only read during system test. The most significant bit of each byte corresponds to the leftmost multiplexer in FIG. In a serial multiplexer, any combination of values is legal. In the other two multiplexers, configurations with 4 or more consecutive bits in one of the multiplexer control bytes are illegal (due to propagation delay). This also applies to cyclic feedback. That is, the multiplexer configuration of C3 (16) is also illegal. The configuration bytes for each of the configurations a) to j) described above with reference to FIGS. 6 to 17 are guaranteed to work and are shown in Table 5 below. The coprocessor chip according to the present invention includes a data path module dedicated to a manufacturing test and performs a read operation for outputting data from the window 7. A preferred embodiment of a chip containing a non-numeric coprocessor according to the present invention is a highly parallel VLSI chip mounted on an expansion card for a personal computer or workstation. Preferably, the chip is a 100-pin PQFP package manufactured by a CMOS (Complementary MOS) process, having TTL (Transistor Transistor Logic) and CMOS compatible inputs and operating on a + 5V power supply. At an operating frequency of 20 MHz, such a coprocessor chip has a sustainable data processing capacity of 160 MB / s and makes a comparison of 10 Giga single bytes per second. Programming Example The following example shows the settings for searching a person in the phone book. FIG. 20 shows a partial configuration of the window for this example. This window reports a person with a surname starting with the letters A to G and a match for a phone number in the range 142000 to 160000. The telephone number is treated as a 6-byte numeric field by setting the appropriate bits in the field delimiter mask. Although the other two fields are also shown in the illustrated window, the field number. 1 and No. If all bits are 1's for 2, they do not make a difference because they are not included in the comparison of more than 1 byte. Bytes not included in the search criteria are set to a "don't care" state that matches all data patterns within the maximum range of FF (16) through 00 (16). Due to the programmed 16-byte record length, no matching is done for data that does not meet record boundaries in the configuration. Further, when only one window is used, the matching waiting time is unnecessary. If the above is the only search criterion, it may be copied to all windows and the hit mask RAM is set so that all positions except position 0 are 1. This causes a match signal to be issued when at least one of the windows has a hit. In addition, the mode value also needs to be set appropriately, for example, Report = 1, Stop = 1, and Blank = 0. Next, the coprocessor generates an interrupt signal for each match, and further reads the match position relating to the search start for each match. Functional Description As shown in FIG. 3, the preferred embodiment of the coprocessor consists of eight data windows, each containing a 32-byte shift register. As shown in FIG. 4, each register element is associated with two comparators that check the upper and lower bounds. Each boundary is individually programmable, allowing data to match within any contiguous interval in the byte range. The two comparators report the match to the matching logic circuit connected to each window. For items larger than 1 byte, combine matches of different bytes. This allows data records of up to 256 bytes to be processed. The data field can be configured up to 8 bytes for any interval test and up to 256 bytes for the equivalence test. Each window reports an individual hit to the central hit mask on the chip. A match of each of the eight windows is used as the address of the 256-bit user programmable RAM. This RAM stores a 1 for any combination of window hits that should be detected as a hit. Being programmable, the user should, for example, be reported even when only one window is hit, be reported when four of eight windows are hit, or all windows are hit You can choose when it should be reported. In general, any logical combination of 8 window hits is a user-defined hit. The chip reports the address of occurrence of all hits detected, or the total number of matches in the data volume. When set to report mode, the coprocessor stores an internal counter containing the position of the detected data in the shadow register on hit. This accumulated display may be read later by the host computer. The shadow register is not overwritten until the host computer confirms the match by sending an ACK signal. Each window is configurable to store hits for a programmable amount of time. This allows a context sensitive search to be performed if an exact match cannot be detected. It follows the coprocessor principle. That is, instead of one (strict) search key, many weak conditions on the required data are used. This feature is especially important for searches in complex and / or large amounts of data. Application Example Creating and maintaining traditional indexes would be obsolete because of the search speed achieved by the search coprocessor in unstructured text. By combining text fragments with wildcards with controlled relative distances, important information can be uniquely identified. Synonyms may be used simultaneously in the search. Below are two different types of simple queries. Q1: "In Shakespeare's work, how often and where does the sentence'take it in what sence thou wilt 'appear?" Q2: "'Jelts','Mitter','Kohl,not'Gorbat'." Find a newspaper article in which at least three of the five (partial) names'Major 'and'Bush' appear. "Q1 type stylistic research cannot be done well with conventional text search systems. It is also well known that indexes require more space than text. The coprocessor according to the given example achieves a sustainable data rate of 160 MB / sec for Q1 type queries. Also, Q2-type complex queries are processed at a sustainable data rate of 20 MB / sec. Pattern matching Various types of features can be extracted from images such as fingerprints, and many combinations of such features can identify an object. Searching among multiple applicants has much to gain from the robust and fuzzy mechanism of this coprocessor. In general, the coprocessor's capabilities are well suited to problems involving partial matching, such as those done in DNA research. Image Archiving The need to store and process different types of images has facilitated technological development in many areas. Efficient image retrieval systems are rapidly becoming indispensable, for example in hospitals, newspaper companies or real estate agents. The image represents a multi-dimensional object with a considerable amount of guidance and additional properties. Database Search Most database systems rely on hierarchical structures and well-defined identifiers. Fuzzy queries with less selective attributes impose severe performance problems on existing systems, but such queries are ideal for this coprocessor which combines all weak constraints during operation. For example, specific research on environmental measurement and chemical databases has shown that there is an inherent potential need for simplification and improved performance. Signal Processing Potential applications include nonlinear filtering, radar target correlation, and abnormal signal detection. Data Networks Potential applications include parasitic monitoring functions, for example to report illegal address ranges or to snap information. Some of the personal computers and workstations with this coprocessor use all the problems inherent in distributed processing systems by using as a data source a network originating from a central data pump that periodically spreads the full amount of data. Can be removed. Disk Controller The coprocessor according to the present invention is an ideal disk controller component. This greatly reduces the need to transfer data to the host computer via the bus by simply limiting the data to the required items. The function of the coprocessor is to provide more advanced "data characteristic" addressing beyond conventional content addressing.

Claims (1)

[Claims] 1. Host computer (2) and data source (3) having means for information processing A non-numerical coprocessor for fuzzy information retrieval and pattern recognition (1 )   Said information processing means examines the data stream from said data source (3) A predetermined number of window modules (W0, W1 ,. ． ． ), A plurality of internal processing elements (PE0, PE1, ...)   Each processing element stores one byte in the data stream, for example an 8-bit byte, Ratio to predetermined individually programmable upper and lower limits assigned to processing elements To determine whether the byte value present in the processing element is within the boundary value. If it is within the boundary value, within each window module (W0, W1, ...). To generate a hit signal to be sent to the window matching logic circuit (16) provided in , Received from different processing elements (PE0, PE1) in the window module Correlation with the hit signal, Generate a window match signal, A coprocessor characterized by that. 2. Furthermore,   Depending on the configuration data corresponding to the needs of the application, the data source (3 ), A separate data stream from (W0, W1, ...) Individually or individually Super window or super window group or all window modules Linked to different selectable window configurations, such as a single super window containing Data routing means (12) for transferring in a manner described The coprocessor according to claim 1, further comprising: 3. The data routing means (12) may be organized at different levels. A network of chipplexers, each multiplexer preferably One of two 8-bit data inputs can be selected and transferred to its output The coprocessor according to claim 2, characterized in that: 4. The multiplexer levels are folding, parallel, And serial multiplexer level, A coprocessor according to claim 3, characterized in that: 5. Furthermore,   Static for internal storage of the window structure loadable on the coprocessor With random access memory (RAM), A coprocessor according to claim 2, characterized in that: 6. Each processing element (PE0, PE1, ...) Temporarily stores the byte to be inspected And a latch cell (17) for the processing element, and With two comparator cells (18, 19),   The comparator cell is configured to generate the hit signal, The coprocessor according to claim 1, wherein: 7. Furthermore,   A programmable center hit mask for receiving the window match signal; A result control logic circuit (13) configured to compare,   The center hit mask supports the definition of window match logical combinations. And report the addresses of all detected occurrences (hit address mode). Or report the total number of matches in the examined data volume (see Count mode), The coprocessor according to claim 1, wherein: 8. Each window module (W0, W1, ...) The record length value of the data record existing in the Field separator mask that separates fields and A match latency value that can be set for each window to store Designed to, The coprocessor according to claim 1, wherein: 9. The number of said window modules (W0, W1, ...) Is 8, Each is designed to handle 8-bit long byte inputs and each window C) A shift register with a length corresponding to the data stream supplied to the module Prepared Consisting of 32 processing elements (PE0, PE1, ...), The coprocessor according to claim 1, wherein: 10. Furthermore,   An 8-bit interface having an interrupt function is preferable. A host interface designed to allow coprocessors to be used with icroprocessors. Face means (14),   A 64-bit interface is preferred to allow the coprocessor to Data source, RAM bank, disk array, or network Data source interface means (15), Equipped with   Preferably 64, 56, 48, 40, 32, 24, 16 or 8 bit data. Programmable for data transfer, Coprocessor according to any one of the preceding claims, characterized in that: