JPH0845859A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

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Publication number
JPH0845859A
JPH0845859A JP19596294A JP19596294A JPH0845859A JP H0845859 A JPH0845859 A JP H0845859A JP 19596294 A JP19596294 A JP 19596294A JP 19596294 A JP19596294 A JP 19596294A JP H0845859 A JPH0845859 A JP H0845859A
Authority
JP
Japan
Prior art keywords
wafer
furnace
temperature
reactive
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19596294A
Other languages
Japanese (ja)
Inventor
Takahiro Maeda
孝浩 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP19596294A priority Critical patent/JPH0845859A/en
Publication of JPH0845859A publication Critical patent/JPH0845859A/en
Pending legal-status Critical Current

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  • Chemical Vapour Deposition (AREA)

Abstract

PURPOSE:To prevent a crack in a film and a haze caused by particles on the wafer face, by inserting the wafer in a reaction furnace at a given speed or below and keeping the temperature of the furnace below a given level while the wafer is put in the reactive furnace. CONSTITUTION:Wafers 8 are mounted horizontally on a multiple-stage boat 9. The boat 9 with the wafers 8 is inserted in the inner reactive furnace 3 at an inserting speed of 20mm/min or below. At this time, the inner temperature of the furnace 3 is adjusted at 600 deg.C or below by a heater 1. A reactive gas is fed through a reactive gas conduction port 6 at a lower end part of the inner reactive tube 3 to form a film on the wafer 8. The waste reactive gas is discharged from an outer reactive tube 2 to a discharge tube 7 through an inlet flange 4. In this way, a crack in the film on the wafer 8 is prevented and particles on the face of the wafer 8 that cause a haze are prevented at the same time.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体製造方法、特に化
学気相成長によりウェーハ表面に各種薄膜を生成する半
導体製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly to a semiconductor manufacturing method for forming various thin films on a wafer surface by chemical vapor deposition.

【0002】[0002]

【従来の技術】半導体製造方法の1つに化学気相成長に
よりウェーハ表面に各種薄膜を生成するものがある。
2. Description of the Related Art As one of semiconductor manufacturing methods, there is a method of forming various thin films on a wafer surface by chemical vapor deposition.

【0003】先ず図3に於いて化学気相成長により半導
体を製造する縦型CVD装置、特に縦型CVD装置の主
要部である縦型炉を説明する。
First, referring to FIG. 3, a vertical CVD apparatus for manufacturing a semiconductor by chemical vapor deposition, particularly a vertical furnace which is a main part of the vertical CVD apparatus will be described.

【0004】該縦型CVD装置は、ヒータに囲まれた縦
型反応管内にウェーハを水平姿勢で多段に装入し、ヒー
タで所定の温度に加熱した状態でSiH4 −N2 O或は
TEOS等の反応ガスを導入し、ウェーハ表面にSiO
2 等の薄膜を生成するものである。
In the vertical CVD apparatus, wafers are horizontally loaded in multiple stages in a vertical reaction tube surrounded by a heater, and SiH 4 --N 2 O or TEOS is heated with a heater at a predetermined temperature. Is introduced into the wafer surface to introduce SiO
It produces a thin film such as 2 .

【0005】ヒータ1の内部に外部反応管2が設けら
れ、該外部反応管2の下端にインレットフランジ4が気
密に設けられ、該インレットフランジ4に下端を支持さ
れた内部反応管3が前記外部反応管2と同心に設けられ
ている。前記内部反応管3と前記外部反応管2との間に
は下端が閉塞された円筒状の空間5が形成される。前記
インレットフランジ4には反応ガス導入ポート6が前記
内部反応管3の下方に位置して連通すると共に排気管7
が前記空間5の下端に連通する様設けられている。
An outer reaction tube 2 is provided inside the heater 1, an inlet flange 4 is airtightly provided at a lower end of the outer reaction tube 2, and an inner reaction tube 3 whose lower end is supported by the inlet flange 4 is the outside. It is provided concentrically with the reaction tube 2. A cylindrical space 5 having a closed lower end is formed between the inner reaction tube 3 and the outer reaction tube 2. A reaction gas introduction port 6 is located below the inner reaction tube 3 and communicates with the inlet flange 4, and an exhaust tube 7 is provided.
Are provided so as to communicate with the lower end of the space 5.

【0006】ウェーハ8を水平姿勢で多段に保持するボ
ート9はボートキャップ10を介して金属製炉口蓋11
に支持され、前記ボート9は該金属製炉口蓋11を介し
図示しないボートエレベータに昇降可能に支持され、前
記内部反応管3内に装入される様になっている。前記ボ
ート9が内部反応管3内に完全に装入された状態では、
金属製炉口蓋11が前記インレットフランジ4に気密に
当接し、外部反応管2内を気密に閉塞する様になってい
る。
A boat 9 for holding wafers 8 in a horizontal posture in multiple stages is provided with a metal furnace lid 11 via a boat cap 10.
The boat 9 is supported by a boat elevator (not shown) via the metal furnace lid 11 so as to be able to move up and down, and is inserted into the inner reaction tube 3. In a state where the boat 9 is completely loaded in the inner reaction tube 3,
The metallic furnace lid 11 is in airtight contact with the inlet flange 4 to hermetically close the inside of the outer reaction tube 2.

【0007】ウェーハの処理を行う場合は、前記ボート
9にウェーハ8を水平姿勢で多段に装填し、ウェーハが
装填されたボート9が前記内部反応管3内に装入され、
ヒータ1により内部が所定の温度に加熱された状態で、
前記反応ガス導入ポート6より前記内部反応管3の下端
から反応ガスが導入され、ウェーハ8が処理され、更に
反応後のガスは外部反応管2内部からインレットフラン
ジ4を経て前記排気管7、真空配管(図示せず)から排
気される。
When the wafers are processed, the boats 9 are loaded with the wafers 8 in a horizontal posture in multiple stages, and the boats 9 loaded with the wafers are loaded into the internal reaction tubes 3.
With the inside heated to a predetermined temperature by the heater 1,
The reaction gas is introduced from the lower end of the inner reaction tube 3 through the reaction gas introduction port 6, the wafer 8 is processed, and the gas after the reaction is further introduced from the inside of the outer reaction tube 2 through the inlet flange 4 into the exhaust pipe 7 and vacuum. The air is exhausted from a pipe (not shown).

【0008】通常SiO2 成膜時には、SiH4 −N2
O系で800℃、TEOS熱分解では700℃で反応炉
内の温度を保持し、前記ボート9の装入速度を100mm
/minとして処理していた。
Normally, when forming a SiO 2 film, SiH 4 --N 2
The temperature in the reaction furnace is maintained at 800 ° C for O system and 700 ° C for TEOS pyrolysis, and the charging speed of the boat 9 is 100 mm.
It was treated as / min.

【0009】[0009]

【発明が解決しようとする課題】近年、半導体素子の高
密度化が進み更に生産性の向上の為、ウェーハ径は増々
大きくなっている。ウェーハの大径化に伴い、ウェーハ
を反応炉内に挿入する際の熱ストレスの影響が大きくな
り、ウェーハ表面上に生成した膜にクラックが発生し、
薄膜が破損して発塵の原因となっていた。この発塵は成
膜後にパーティクルやヘイズ(HAZE:薄膜の表面荒
れ)となり、半導体素子の品質、歩留まりの低下を招い
ていた。
In recent years, the density of semiconductor devices has been increasing and the productivity has been further improved, so that the wafer diameter has been increasing. With the increase in diameter of the wafer, the effect of thermal stress when inserting the wafer into the reaction furnace increases, and cracks occur in the film formed on the wafer surface,
The thin film was damaged, causing dust generation. This dust generation causes particles and haze (roughness of the surface of the thin film) after film formation, resulting in deterioration of the quality and yield of semiconductor devices.

【0010】本発明は斯かる実情に鑑み、半導体製造過
程に於けるパーティクルやヘイズの発生を低減する半導
体製造方法を提供する。
In view of the above circumstances, the present invention provides a semiconductor manufacturing method for reducing the generation of particles and haze in the semiconductor manufacturing process.

【0011】[0011]

【課題を解決するための手段】本発明は、反応炉内にウ
ェーハを装入して化学気相成長によりウェーハ表面に各
種薄膜を生成する半導体製造方法に於いて、ウェーハの
反応炉内への装入速度を20mm/min以下、装入時の反応
炉内温度を600℃以下とするものである。
The present invention relates to a semiconductor manufacturing method in which a wafer is loaded into a reaction furnace and various thin films are formed on the surface of the wafer by chemical vapor deposition. The charging rate is 20 mm / min or less, and the temperature inside the reaction furnace at the time of charging is 600 ° C. or less.

【0012】[0012]

【作用】ウェーハの反応炉内装入時の反応炉内温度を6
00℃以下とし、反応炉内に装入する時のウェーハに加
わる単位時間当たりの熱量を少なくしてクラックの発生
を抑制し、更に装入速度を20mm/min以下とし装入速度
を低下させることでウェーハ表面に付着した不純物が脱
離するに充分な時間を与え、不純物による反応炉内の汚
染を防止し、ウェーハ表面にパーティクルが付着し、ヘ
イズが発生するのを防止する。
[Function] The temperature inside the reaction furnace when the wafer is placed inside the reaction furnace is set to 6
To prevent cracks from occurring by setting the temperature below 00 ° C and reducing the amount of heat applied to the wafer per unit time during charging into the reaction furnace, and further reduce the charging speed to below 20 mm / min. Provides sufficient time for the impurities adhering to the wafer surface to be desorbed, prevents contamination of the reaction furnace by the impurities, and prevents particles from adhering to the wafer surface and haze.

【0013】[0013]

【実施例】以下、図面を参照しつつ本発明の一実施例を
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0014】本発明者は種々の実験を行った結果、パー
ティクル、ヘイズの発生量は装入時の炉内温度、装入速
度と大きな関係があることを確認した。
As a result of various experiments, the present inventor has confirmed that the amount of particles and haze generated has a great relationship with the temperature in the furnace during charging and the charging speed.

【0015】図1に炉内温度が700℃である場合にウ
ェーハの装入速度を変化させた場合の、ウェーハ装入速
度とパーティクルの発生個数との関係を示す。図1に示
す如くウェーハ装入速度が50mm/min位迄はウェーハ装
入速度の低下と共にパーティクルの発生個数は急激に減
少し、その後はウェーハ装入速度の低下と共に緩やかに
減少する。
FIG. 1 shows the relationship between the wafer loading rate and the number of particles generated when the wafer loading rate is changed when the furnace temperature is 700 ° C. As shown in FIG. 1, when the wafer loading speed is about 50 mm / min, the number of particles generated sharply decreases with a decrease in the wafer loading speed, and thereafter gradually decreases with a decrease in the wafer loading speed.

【0016】又、図2にウェーハ装入速度を20mm/min
として炉内温度を変化させた場合の、炉内温度とパーテ
ィクルの発生個数との関係を示す。図2に示す如く炉内
温度が高温側から600℃迄はパーティクルの発生個数
が顕著に減少し、550℃より温度が低下してもパーテ
ィクルの発生個数については殆ど変化がない。
Further, FIG. 2 shows a wafer loading speed of 20 mm / min.
The relation between the temperature in the furnace and the number of particles generated is shown when the temperature in the furnace is changed. As shown in FIG. 2, the number of generated particles is remarkably reduced when the temperature in the furnace is from the high temperature side to 600 ° C., and the number of generated particles is hardly changed even when the temperature is lowered from 550 ° C.

【0017】以上の関係から、反応炉内に装入する時の
ウェーハに加わる単位時間当たりの熱量が少なくなると
クラックの発生が抑制され、装入速度を低下させること
でウェーハ表面に付着した不純物が脱離するに充分な時
間が与えられるので、不純物による反応炉内の汚染を防
止し、ウェーハ表面にパーティクルが付着し、ヘイズが
発生するのを防止できる。
From the above relationship, when the amount of heat applied to the wafer per unit time during charging into the reaction furnace is reduced, the generation of cracks is suppressed, and the charging speed is reduced, so that impurities adhering to the wafer surface are removed. Since sufficient time is provided for desorption, it is possible to prevent contamination in the reaction furnace due to impurities, and prevent particles from adhering to the wafer surface and generating haze.

【0018】即ち、装入時炉内温度を600℃迄下げ、
装入速度を20mm/min迄遅くすることでパーティクル、
ヘイズの発生量は著しく減少する。表1は、ウェーハ装
入速度と反応炉内温度とパーティクル発生量、ヘイズ発
生量との具体的関係を示すものである。
That is, the temperature inside the furnace during charging is lowered to 600 ° C.,
Particles can be generated by reducing the charging speed to 20 mm / min.
The amount of haze generated is significantly reduced. Table 1 shows a specific relationship between the wafer loading rate, the temperature in the reaction furnace, the amount of particles generated, and the amount of haze generated.

【0019】[0019]

【表1】 [Table 1]

【0020】表1でも分る様に、パーティクルの目標値
を30個とするとウェーハ装入速度20mm/min以下、反
応炉内温度600℃以下の製造条件が得られる。
As can be seen from Table 1, when the target value of the number of particles is 30, the manufacturing conditions are such that the wafer loading speed is 20 mm / min or less and the reaction furnace temperature is 600 ° C. or less.

【0021】尚、本発明はCVD製造方法のSiO2
に効果があるが、勿論他のポリシリコン膜、窒化膜、リ
ンドープトポリシリコン膜、アモルファスシリコン膜、
等にも効果があることは勿論である。
Although the present invention is effective for the SiO 2 film in the CVD manufacturing method, of course, other polysilicon film, nitride film, phosphorus-doped polysilicon film, amorphous silicon film,
It goes without saying that it is also effective for such cases.

【0022】[0022]

【発明の効果】以上述べた如く本発明によれば、成膜時
のパーティクル及びヘイズの発生を抑制するので、半導
体素子製造上の歩留まりが向上し、膜のクラックの発生
を抑制できることにより、ダミーウェーハ、ボートの洗
浄メンテナンスサイクルが長くなり、生産性が向上する
等の優れた効果を発揮する。
As described above, according to the present invention, since the generation of particles and haze during film formation is suppressed, the yield in semiconductor device manufacturing is improved, and the generation of film cracks can be suppressed. The cleaning and maintenance cycle of wafers and boats is lengthened, and excellent effects such as improved productivity are exhibited.

【図面の簡単な説明】[Brief description of drawings]

【図1】炉内温度が700℃である場合にウェーハの装
入速度を変化させた場合の、ウェーハ装入速度とパーテ
ィクルの発生個数との関係を示す線図である。
FIG. 1 is a diagram showing the relationship between the wafer loading rate and the number of particles generated when the wafer loading rate is changed when the furnace temperature is 700 ° C.

【図2】ウェーハ装入速度を20mm/minとして炉内温度
を変化させた場合の、炉内温度とパーティクルの発生個
数との関係を示す線図である。
FIG. 2 is a diagram showing the relationship between the temperature inside the furnace and the number of particles generated when the temperature inside the furnace is changed at a wafer loading rate of 20 mm / min.

【図3】縦型CVD装置の主要部である縦型炉の説明図
である。
FIG. 3 is an explanatory diagram of a vertical furnace which is a main part of the vertical CVD apparatus.

【符号の説明】[Explanation of symbols]

1 ヒータ 2 外部反応管 3 内部反応管 4 インレットフランジ 5 空間 6 反応ガス導入ポート 7 排気管 8 ウェーハ 9 ボート 10 ボートキャップ 11 金属製炉口蓋 1 Heater 2 External Reaction Tube 3 Internal Reaction Tube 4 Inlet Flange 5 Space 6 Reaction Gas Introducing Port 7 Exhaust Pipe 8 Wafer 9 Boat 10 Boat Cap 11 Metal Furnace Lid

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 反応炉内にウェーハを装入して化学気相
成長によりウェーハ表面に各種薄膜を生成する半導体製
造方法に於いて、ウェーハの反応炉内への装入速度を2
0mm/min以下、装入時の反応炉内温度を600℃以下と
することを特徴とする半導体製造方法。
1. A method for manufacturing a semiconductor, wherein a wafer is loaded into a reaction furnace and various thin films are formed on the surface of the wafer by chemical vapor deposition, and a loading speed of the wafer into the reaction furnace is 2
A semiconductor manufacturing method characterized in that the temperature in the reaction furnace at the time of charging is 0 mm / min or less and the temperature in the reaction furnace is 600 ° C. or less.
JP19596294A 1994-07-28 1994-07-28 Manufacture of semiconductor Pending JPH0845859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19596294A JPH0845859A (en) 1994-07-28 1994-07-28 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19596294A JPH0845859A (en) 1994-07-28 1994-07-28 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPH0845859A true JPH0845859A (en) 1996-02-16

Family

ID=16349888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19596294A Pending JPH0845859A (en) 1994-07-28 1994-07-28 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPH0845859A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294228B1 (en) 1998-11-04 2001-09-25 Nec Corporation Method for forming thin films
US9487859B2 (en) 2014-03-24 2016-11-08 Tokyo Electron Limited Operating method of vertical heat treatment apparatus, storage medium, and vertical heat treatment apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294228B1 (en) 1998-11-04 2001-09-25 Nec Corporation Method for forming thin films
US9487859B2 (en) 2014-03-24 2016-11-08 Tokyo Electron Limited Operating method of vertical heat treatment apparatus, storage medium, and vertical heat treatment apparatus

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