JPH0845288A - Nonvolatile random access memory - Google Patents

Abstract

PURPOSE:To improve the reliability for managing the number of accesses and to reduce the burden of a software by counting and storing the number of accesses to an erasable read-only memory by a hardware. CONSTITUTION:In this nonvolatile random access memory, a random access memory 1 and an erasable read-only memory 2 are combined with each other and the storage content of the random access memory 1 is stored in the erasable read-only memory 2 and also the content of the memory 2 is stored in the random access memory 1 by reading out the content of the memory 2. The memory 1 is provided with a counter 3 counting the number of accesses accessed from the random access memory 1 to the erasable read-only memory 2 and an erasable read-only memory for the counter 4 storing the count value of the counter 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can store the memory of a random access memory in an erasable read-only memory and stores a counter for counting the number of times the random access memory accesses an erasable read-only memory and a count value. The present invention relates to a nonvolatile random access memory having a memory.

[0002]

2. Description of the Related Art Random access memory is referred to as RAM and is referred to as dynamic random access memory (DRA).
M) and static random access memory (SRA)
M). DRAM has a memory cell composed of a capacitor made of a semiconductor and one switching transistor, and stores 1 or 0 depending on whether or not electric charge is stored in the capacitor. Is being rewritten (refreshed). The SRAM has a memory cell composed of a flip-flop (FF) made of a semiconductor, and the stored contents are lost when the power is turned off.

For this reason, the stored contents of the random access memory are lost when the power is turned off. Therefore, the random access memory is combined with an erasable read-only memory to store necessary data in the erasable read-only memory and then the power is turned on. Cut it off and read it back to the random access memory as needed for use. Non-volatile random access memory (Non Volatile Ramdam Access Memory:
NVRAM). Erasable read-only memories include an ultraviolet erasable EPROM and an electrically erasable EEPROM, but EEPRO is easy to use
M is often used. The EEPROM can be written many times by erasing it, but the number of times is limited, for example, about 10 ⁶ times.

[0004]

Therefore, the conventional EE
The number of times of writing or reading (access) to the PROM was counted by software, and the number of times of access was managed. However, if the number of accesses is performed by software, there were the following problems. Since the count is done by software, the correct access count becomes unknown if there is a bug in the software or if the hardware or software runs out of control for some reason. The logic that is different from the original purpose of the control software, that is, management of the number of accesses must be executed by a program, which increases the program execution time and the program size.

The present invention has been made in view of the above problems, and improves the reliability of management of the number of accesses by counting and storing the number of accesses to a read-only memory that can be erased by hardware. Also, the purpose is to reduce the burden on the software.

[0006]

In order to achieve the above-mentioned object, a random access memory and an erasable read-only memory are combined to store the stored contents of a random Akmos memory in the erasable read-only memory, and the random In a nonvolatile random access memory that is read and stored in an access memory, a counter that counts the number of times the random access memory accesses the erasable read-only memory, and a counter erasing that stores the count value of the counter And a possible read-only memory.

[0007]

The number of times the erasable read-only memory is accessed from the random access memory is counted by the counter, and the count value is stored in the erasable read-only memory for the counter to manage the number of accesses. The correct number of accesses can be managed without being affected by.
Moreover, since no software is used, there is no fear of bugs or runaway.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment, and shows the case where the whole indicated by the one-dot chain line is integrated into an IC (integrated circuit). 1
In the SRAM array, a large number of component flip-flops are arranged to form a memory. 2 is EE for SRAM
EEP as a read-only memory that can be erased by PROM
ROM is used. 3 is a counter and SRAM 1 is SR
It is counted each time data is written (Store) or read (Recall) in the EEPROM 2 for AM. Reference numeral 4 denotes a counter EEPROM, which stores the count value of the counter 3. Reference numeral 5 is a row select for selecting a row address of the SRAM array 1 and selects a row address according to address data from the address bus. A column select and input / output unit 6 selects a column address of the SRAM array 1 and inputs / outputs data, and is connected to the address bus and the data bus. Reference numeral 7 is a control logic, which causes the SRAM array 1 to write to the SRAM EEPROM 2 by a Store instruction, and the SRAM E by a Recall instruction.
The SRAM array 1 is caused to read from the EPROM 2 and data is output from the SRAM array 1 to the data bus by the Output Enable command.
The data on the data bus is written to the SRAM array 1 by Enable. SRAM array 1, SRAM EEPROM 2, counter 3, counter EEPROM
4, row select 5, column select and input / output unit 6, and control logic 7 constitute a non-volatile random access memory NVRAM.

Next, the operation of the counter 3 will be described. By the Store instruction, the data of the SRAM array 1 is stored in the SRAM EEPROM 2 and the count value of the counter 3 is written in the counter EEPROM 4. R
The data of the EEPROM 2 for SRAM is read to the SRAM array 1 by the ecall instruction and the counter E
Data is transferred from the EPROM 4 to the counter 3. The transferred count value can be read out to the data bus.

The timing of counting by the counter 3 is St
It may be either an ore instruction or a Recall instruction. There are the following two counting methods, each of which has its own characteristics. It is suitable for counting the number of times of writing by the addition type (increment type) 0, 1, 2. Subtraction type (decrement type) 1,000,000, 999999, 99998, and a method of performing subtraction, which is suitable for managing the life (the number of remaining writes).

In the above-described embodiment, the case where the components are integrated into one IC to form the NVRAM has been described.
RAM array 1, SRAM EEPROM 2, counter 3, counter EEPROM 4, row select 5, column select and input / output unit 6, and control logic 7.
Each may be integrated into an IC, mounted on a substrate, and connected in a pattern to form an NVRAM. In addition, ASIC (Applic
ation Specific IC), some components may be integrated into an IC by using an application specific IC, etc., and the remaining components may be integrated into a substrate and incorporated into a substrate to form an NVRAM. Further, although the SRAM is used, it may be a DRAM. When using a DRAM, it is necessary to have the control logic 7 perform refresh control.

[0012]

As is apparent from the above description, according to the present invention, the number of accesses to the erasable read-only memory of the non-volatile random access memory is counted by using hardware. Can be managed properly. Since it does not need to be managed by software as in the past, software can be dedicated to other processing, and its program can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

[Explanation of symbols]

1 SRAM array (random access memory) 2 SRAM EEPROM (erasable read-only memory) 3 Counter 4 counter EEPROM (counter erasable read-only memory) 5 Row select 6 Column select and input / output unit 7 Control logic

Claims (1)

[Claims] 1. A nonvolatile access memory and an erasable read-only memory are combined to store the stored contents of a random Akumos memory in an erasable read-only memory and to read and store the contents in the random access memory. Random access memory includes a counter that counts the number of times the random access memory accesses the erasable read-only memory, and a counter erasable read-only memory that stores the count value of the counter. Characteristic nonvolatile random access memory.