JPH0844697A - Security system for micorocomputer with built-in memory - Google Patents

Abstract

PURPOSE:To partially disable the reading of contents by partially applying security to a memory of a microcomputer with built-in memory by outputting an output inhibiting signal so as not to execute the output to the outside when an address to which security is applied is judged. CONSTITUTION:A NAND circuit provided at a security judging circuit 5 inputs the contents inverting an input terminal 4a by a NOT circuit, the contents of an input terminal 4b, and security signal 1. In this case, if the security is applied when an address is four bits (4a-4d) and high-order two bots 4a and 4b are '01', even when the security signal 1 is inputted, data are normally transferred from a built-in memory 2 to an output terminal 3 in the case other than that the high-order two bits 4a and 4b of the input terminal are '01'. Besides, when the security signal 1 is inputted and the high-order bits 4a and 4b are '01', namely, reading is disabled only at addresses from '0100' to '0111', and security is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a security system for a microcomputer having a built-in memory, and more particularly to a security system for a microcomputer having a built-in memory capable of prohibiting reading (security) at a desired address of the memory. It is about.

[0002]

2. Description of the Related Art Conventionally, since the contents of a memory of a microcomputer with a built-in memory can be read relatively easily, there is a possibility that another person may analyze the contents stored in the memory such as programs and data. . Therefore, the conventional microcomputer with a built-in memory uses a circuit as shown in FIG. 6 in order to make it impossible to read the contents.

This circuit has a security bit 8. If the security signal 1 is not input, the security bit 8 remains "1" (unlocked state) and data is directly transferred from the internal memory 2 to the output terminal 3. , All areas are accessible.

However, when the security signal 1 is input, "0" (lock state) is written in the security bit 8 and the output judging circuit 6 stops outputting the contents of the memory 2, so that it is not transferred to the output terminal 3. . Therefore, the entire area of the built-in memory 2 cannot be accessed, and the contents of the stored program and the like cannot be read again.

[0005]

However, in the above-mentioned conventional method, once security is applied, the entire area of the built-in memory cannot be accessed, and even the program creator cannot read the contents. Therefore, in order to manage the stored programs, it was necessary to take measures such as creating in advance a program for outputting a part of the program to the outside. That is, a program that does not operate in actual operation is required only for program management, resulting in waste of memory capacity and waste of program development time.

The present invention has been made in view of the above circumstances. An object of the present invention is to partially protect the memory of a microcomputer with a built-in memory so that the contents cannot be read. It is to provide a security method for a microcomputer with a built-in memory, which is capable.

[0007]

In order to achieve the above object, the features of the system according to the first invention are that a built-in memory for outputting contents stored at an input address and a security for the input address. It is determined whether or not a security check is applied, and a security determination unit that outputs an output prohibition signal when it is determined that the address is security-protected in the determination, and the security determination unit that outputs the output prohibition signal And an output determination unit that does not output the output content to an external terminal.

The first method according to the second aspect of the present invention is characterized in that a built-in memory for outputting the content stored at the input address, the input content, and an output inhibit signal are input. In the security method of the microcomputer with a built-in memory, which has an output determination unit that stops the output of the output content in the case of a failure, security is applied to the input address by the input address and the security signal. It is to be provided with a security judging section for outputting the output prohibition signal to the output judging section when it is judged that the inputted address is protected.

A feature of the second method according to the second invention is that the security judgment unit includes a security area setting register that holds information as to whether or not the area is a security area.

[0010]

With the configuration of the system according to the first and second aspects of the invention, since the security judging section inputs the address, the security can be set by the inputted address. In addition, even if security is applied, the preset area or arbitrary area on the memory can be read, and if you write information convenient for management there, the program creator etc. can read the contents. It was made possible.

Further, since the security area setting register is provided by the configuration of the second method according to the second aspect of the present invention, it is possible to more flexibly set the address area for security.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment A first embodiment of the present invention will be described with reference to FIG. The same parts as those in FIG. 4 of the conventional example are designated by the same reference numerals.

In the present embodiment, security is not applied to the area on the preset memory,
Here, if the address is 4 bits (4a to 4d) and the upper 2 bits 4a and 4b are "01", that is, security is applied to addresses 0100 to 0111 of the built-in memory.

In this case, the security judgment circuit 5 as shown in FIG. 1 may be added. This security judgment circuit 5
Has a NAND circuit, and the NAND circuit is
The contents obtained by inverting the input terminal 4a by the NOT circuit, the contents of the input terminal 4b, and the security signal 1 are input. That is, when all of these three inputs become "1", the output of the NAND circuit becomes "0" (lock state), and the output judgment circuit 6 does not transfer to the output terminal 3.

Therefore, even if the security signal 1 is input, if the upper 2 bits 4a and 4b of the input terminal 4 are other than "01", the data is transferred from the built-in memory 2 to the output terminal 3 as usual. Further, when the security signal 1 is input and the upper 2 bits 4a and 4b of the input terminal 4 are "01", that is, only addresses 0100 to 0111 cannot be read, security is applied.

In this way, the set area (in this case, addresses other than 0100 to 0111) can be read even after security is applied.

Second Embodiment A second embodiment of the present invention will be described with reference to FIG. The same parts as those in FIG. 1 of the first embodiment are designated by the same reference numerals.

In this embodiment, as in the first embodiment, the address is 4 bits (4a-4d) and the upper 2 bits 4a, 4 are included.
When b is “01”, that is, 0100 to
Security will be applied to address 0111.

In the case of this embodiment, a security judgment circuit 5 as shown in FIG. 2 is added. This security judgment circuit 5
Has a NAND circuit, and the NAND circuit is
The contents obtained by inverting the input terminal 4a by the NOT circuit, the contents of the input terminal 4b, and the security signal 1 are input. That is, when all of these three inputs become "1", the output of the NAND circuit becomes "0" (lock state), and the output judging circuit 6 sends the read signal or the chip select signal 9 to the memory 2. Is no longer entered,
No data is transferred to the output terminal 3.

Therefore, even if the security signal 1 is input, if the upper 2 bits 4a and 4b of the input terminal 4 are other than "01", the data is transferred from the built-in memory 2 to the output terminal 3 as usual. When the security signal 1 is input and the upper 2 bits 4a and 4b of the input terminal 4 are "01", that is, only the addresses 0100 to 0111,
It becomes impossible to read, and security is applied.

In this way, the set area (in this case, addresses other than 0100 to 0111) can be read even after security is applied.

Third Embodiment A third embodiment of the present invention will be described with reference to FIG. The same parts as those in FIG. 1 of the first embodiment are designated by the same reference numerals.

Also in the present embodiment, as in the first embodiment, when the address is 4 bits (4a to 4d) and the upper 2 bits 4a and 4b are "01", that is, 0 in the built-in memory.
Security is applied to addresses 100 to 0111.

In the case of this embodiment, a security judgment circuit 5 as shown in FIG. 3 is added. This security judgment circuit 5
Has a NAND circuit, and the NAND circuit is
The contents obtained by inverting the input terminal 4a by the NOT circuit, the contents of the input terminal 4b, and the security signal 1 are input. That is, when all of these three inputs become "1", the output of the NAND circuit becomes "0" (lock state), and the output judging circuit 6 transfers the data of the address buses 4a-4d to the memory 2. Therefore, normal data cannot be output to the output terminal 3.

Therefore, even if the security signal 1 is input, if the upper 2 bits 4a and 4b of the input terminal 4 are other than "01", the data is transferred from the built-in memory 2 to the output terminal 3 as usual. When the security signal 1 is input and the upper 2 bits 4a and 4b of the input terminal 4 are "01", that is, only the addresses 0100 to 0111,
It becomes impossible to read, and security is applied.

In this way, the set area (in this case, other than addresses 0100 to 0111) can be read even after security is applied.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to FIGS. 4 and 5. The same parts as those in FIG. 1 of the first embodiment are designated by the same reference numerals. Again, the address is 4 bits (4
Cases a to 4d) will be described.

First, the structure of this embodiment will be described.
The present embodiment is characterized in that the security judgment circuit 5 is provided with a register 7 capable of arbitrarily setting a security application area. This register 7
Has a mask register (M in the figure) and a start address register (S in the figure). This mask register has 4 bits. For convenience of explanation, the most significant bit is Ma, hereinafter Mb and Mc, and the least significant bit is Md.

Similarly, the start address register also has 4 bits, and the most significant bit is Sa.
Hereinafter, Sb and Sc will be referred to, and the least significant bit will be referred to as Sd.

Here, the register 7 is preferably a non-volatile memory in that stored contents do not disappear even when the power is turned off, and more preferably an EPROM.

The security judgment circuit 5 has a 5-input NAND circuit, and the 5-input NAND circuit receives the security signal 1 and four 2-input NAND circuits. Also, these four 2-input NAND
The circuit uses an exclusive OR of the input terminals 4a and Sa and Ma.
And a two-input NAND circuit having inputs as inputs, an exclusive OR of the input terminals 4b and Sb, and a two-input NAND circuit having Mb as inputs, an exclusive OR of the input terminals 4c and Sc, and Mc And a two-input NAND circuit having inputs, and a two-input NAND circuit having Md and an exclusive OR of the input terminals 4d and Sd.

Therefore, even if the security signal 1 is input, if at least one of the four 2-input NAND circuits is "0", the data is transferred from the built-in memory 2 to the output terminal 3 as usual.

Further, the security signal 1 and this 4
5 if all NAND circuit outputs become "1"
The output of the input NAND circuit becomes "0" (lock state),
The output judgment circuit 6 does not transfer to the output terminal 3.

That is, when "0" is set in the mask registers Ma to Md, the address (bit) becomes irrelevant, and when "1" is set, the value of the start address register corresponding to the address (bit) becomes valid. The address space set by the mask register and the start address register becomes the security area.

Next, a setting example of the register 7 and a security area set by the setting will be described with reference to FIG. (A) is a mask register Ma, Mb, M
This is a case where c and Md are set to 1000, and Sa, Sb, Sc, and Sd of the start address register are set to 0000.

In this case, since Ma is "1", 4
Only the address (bit) of a is valid, 4b, 4c, 4d
Is invalid (irrelevant). Next, Sa, Sb, Sc, Sd
Is set to 0000, but 4b, 4c, and 4d are invalid (irrelevant), so only the value of 4a is valid.
Therefore, only Sa of the start address register is valid, and Sa is "0", so the security area is 0.
The area from 000 to 0111, that is, the area of 0 *** (where “*” is arbitrary, the same applies below) is the security area.

(B) shows mask registers Ma, Mb, and M.
This is a case where c and Md are set to 1100 and Sa, Sb, Sc, and Sd of the start address register are set to 1010.

In this case, since Ma and Mb are "1", the addresses (bits) 4a and 4b are valid and 4
c and 4d are invalid (irrelevant). Next, Sa, Sb, S
c and Sd are set to 1010, but 4c and 4d
Is invalid (irrelevant), only the values of Sa and Sb are valid. Therefore, the security area is 1000 to 10
It will be 11. That is, the area of 10 ** is the security area.

(C) is a mask register Ma, Mb, M
This is a case where c and Md are set to 1010 and Sa, Sb, Sc and Sd of the start address register are set to 1100.

In this case, since Ma and Mc are "1", the addresses (bits) of Sa and Sc are valid, and S
b and Sd are invalid (irrelevant). Next, Sa, Sb, S
c and Sd are set to 1100, but Sb and Sd
Is invalid (irrelevant), only the values of Sa and Sc are valid. Therefore, the security area is 1000 to 10
01 and 1100 to 1101. That is, 1 * 0 *
Area is the security area.

In this embodiment, the case of 4 bits has been described for simplification of description. Therefore, it is obvious that the present invention is not limited to this, and can be applied to, for example, a memory of 16 bits or 32 bits.

Further, the security judgment circuit 5 and the output judgment circuit 6 are not limited to this, and may be appropriately changed without departing from the gist of the invention.

As described above, the method of this embodiment has the effect that the program creator can set a secure area on the memory, as compared with the above embodiments. If it is desired to omit this work, it seems to be a good idea to select the above-mentioned embodiment.

[0045]

As described above, in the security methods according to the first and second aspects of the present invention, since a partial area on the memory can be read even after security is applied, necessary information is written there. The content can be determined by Therefore, it is not necessary to previously create a program for outputting the contents of the memory to the outside as in the conventional case.

Further, in the second method according to the second aspect of the invention, since the security area setting register is provided, the address area to which security is applied can be freely set.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a security system according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a security system according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a security system according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a security system according to a fourth embodiment of the present invention.

FIG. 5 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a conventional security system.

[Explanation of symbols]

 1 Security signal 2 Internal memory 3 External terminal (data) 4a Input terminal (address 3, most significant bit) 4b Input terminal (address 2) 4c Input terminal (address 1) 4d Input terminal (address 0, least significant bit) 5 Security Judgment circuit 6 Output judgment circuit 7 Security area setting register 8 Security bit 9 Read signal or chip select signal

Claims (3)

[Claims] 1. A built-in memory that outputs the contents stored at an input address; a judgment is made as to whether or not the input address is security-protected; A security determination unit that outputs an output prohibition signal when a determination is made, and an output determination unit that does not output the output content to an external terminal when the output prohibition signal is input. A security method for microcomputers with a built-in memory. 2. A built-in memory for outputting the contents stored at the input address, and the input contents,
In a security system of a microcomputer with a built-in memory, which includes an output determination unit that stops outputting the output content when an output prohibition signal is input, the input address and the security signal are used for the input. A security determination unit that determines whether or not the address is protected, and outputs the output prohibition signal to the output determination unit when it is determined that the input address is protected A security method for a microcomputer with a built-in memory. 3. The security system for a microcomputer with a built-in memory according to claim 2, wherein the security judgment unit includes a security area setting register that holds information as to whether or not the area is to be protected.