JPH0844591A - Simulator - Google Patents

Abstract

PURPOSE:To shorten the time required for simulation without simulating the part describing the output operation of a message in a program when no simulation for the part is required and by outputting the message required for a simulator. CONSTITUTION:The leading address of a message processing part in the program is registered by an address registering means 3. An address comparison means 5 compares a registered leading address with the address of a machine language instruction read in by a program read-in control means 6a, and reports the machine language instruction on the leading address to a simulation control means 2a when it is detected. At this time, the simulation is interrupted. and the message stored in a message storage means 8 in advance is outputted. After that, the simulation is sampled by an instruction analysis executing means 7a, and an operation is restarted from the address next to the last address of a message part set on a simulation address register 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulator, and more particularly to a simulator for simulating a program to be debugged.

[0002]

2. Description of the Related Art In a conventional simulator, a machine language instruction of a program to be debugged is read and simulated for one instruction, and the next one instruction is read for simulation. The machine language instructions of the program were also read one by one and simulated sequentially for the part of the program that describes the output operation of messages such as branch trace information and interruption information.

[0003]

The above-described conventional simulator reads the machine language instructions of the entire program to be debugged one by one and then simulates them. Therefore, the output operation of the message included in the program is described. The part to be simulated was simulated as in the other parts. However, if this part does not need to be debugged, it has a drawback that the simulation time will be longer than that.

The object of the present invention is to reduce the simulation time by shortening the simulation time without simulating the part describing the output operation of the message in the program to be debugged. It is to provide a simulator that can raise the cost.

[0005]

The simulator of the first invention comprises: (A) a program under test storage means for storing a program under test to be debugged; (B) an address comparison instruction signal; and a first machine language. First simulation control means for controlling the simulation of the program under test by outputting an instruction read instruction signal, an instruction execution prohibition signal and a second machine language instruction read instruction signal, (C) a message output processing portion of the program under test An address registration means for registering the leading address of (1), (D) a read address storage means for receiving and storing the address at which the simulation is performed from the first simulation control means,
(E) receives the address comparison instruction signal, compares the address value read from the read address storage means with the head address value received from the address registration means and preset internally as a registered address,
(F) One word of the machine language instruction of the program under test stored in the program under test storage means by the address comparing means for outputting a head address detection signal when they match (F) the first machine language instruction read instruction signal When the simulation control means receives the head address detection signal, the second machine language instruction read instruction signal is used as the address of the machine language instruction to be read first from the tested program storage means after the head address is detected. First program read control means for reading an address from the instructed address storage means and for reading a machine language instruction stored in the tested program storage means based on the address, (G) first program read control Machine language instructions of the program under test read by the means Analyze and report that the analysis is completed to the first simulation control means, execute the analyzed machine language instruction, output message information obtained as a result of analysis and execution of the machine language instruction, and start the When the machine language instruction of the address is analyzed, the address next to the last address of the message output portion is extracted and output as simulator restart address information, and the instruction is executed from the first simulation control means that has received the head address detection signal. First instruction analysis executing means that does not execute the machine language instruction that has been analyzed when a prohibition signal is sent, (H) message storing means for storing the message information, (I) message information in the message storing means Is stored and the address value received from the first instruction analysis executing means. An address information register for holding the address value next to the last address value of the message output processing part of the program under test obtained from the emulator restart address information, and (J) the message storage means when the leading address detection signal is received. Information reading means for reading from the address information register the address value in which the message is stored and the address value next to the last address value of the message output processing part of the program under test, (K) reading the register information Message reading means for receiving the address value in which the message of the message storing means is stored from the means, and reading the message from the message storing means; (L) message outputting means for outputting the read message to the message reading means; M) the second
A simulation address register for setting the address value next to the last address value of the message output processing part of the program under test read from the address information register, as the address storing means indicated by the machine language instruction read instruction signal , And are configured.

The simulator of the second invention is
(A) Test program storage means for storing a test program to be debugged, (B) address comparison instruction signal, first machine language instruction read instruction signal, instruction execution prohibition signal, second machine language instruction read instruction Second simulation control means for controlling the simulation of the program under test by outputting a signal and a third machine language instruction read instruction signal, and (C) address registration for registering the top address of the message output processing portion of the program under test. Means, (D) special instruction code setting means for embedding a special instruction code in the instruction at the start address, and (E) the second
Read address storing means for receiving and storing an address to be simulated from the simulation controlling means, and (F) receiving the address comparison instruction signal, receiving the address value read from the read address storing means and the address registering means, and preliminarily internally Address comparison means for comparing the start address value set as a registration address and outputting a start address detection signal when they match, (G) registering the address by the third machine language instruction read instruction signal control signal The machine language instruction stored in the head address registered in the means is read and sent to the special instruction code setting means, and is stored in the tested program storage means by the first machine language instruction read instruction signal. Read the machine language instructions of the program under test word by word , When the second simulation control means receives said first address detection signal,
After the head address is detected, the address is read from the address storage means designated by the second machine language instruction read instruction signal as the address of the machine language instruction to be read first from the test program storage means, and the test subject is tested based on the address. Second program read control means for reading a machine language instruction stored in the program storage means,
(H) A machine language instruction of the program under test read by the second program read control means is analyzed and the fact that the analysis is completed is reported to the second simulation control means, and the machine language after the analysis is completed. Execute the instruction,
Message information obtained as a result of analysis and execution of the machine language instruction is output, and when the machine language instruction at the start address is analyzed, the address next to the last address of the message output portion is extracted and output as simulator restart address information. However, as a result of the analysis, when it is detected that the special instruction code is embedded in the read machine language instruction of the program under test, the address comparison instruction signal for operating the address comparison means is detected. When the instruction execution prohibition signal is output from the second simulation control means which is output from the second simulation control means and receives the head address detection signal, the machine language instruction whose analysis has been completed is not executed. Instruction analysis and execution means of (I) message storage for storing the message information (J) The last address of the message output processing part of the program under test obtained from the address value in which the message of the message storage means is stored and the simulator restart address information received from the second instruction analysis execution means. An address information register for holding an address value next to the value, (K) when the head address detection signal is received, the address value at which the message of the message storage means is stored and the message output processing portion of the program under test Register information reading means for reading the address value next to the last address value of the message from the address information register, and (L) receiving the address value in which the message of the message storing means is stored from the register information reading means. Read message from storage Message reading means, (M) a message output means for outputting a message read in the message reading means, (N) and the second
A simulation address register for setting the address value next to the last address value of the message output processing part of the program under test read from the address information register, as the address storing means indicated by the machine language instruction read instruction signal , And are configured.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the simulator of the present invention.

The simulator of the embodiment shown in FIG. 1 includes a test program storage means 1 for storing a test program to be debugged, a simulation control means 2a for controlling a simulation of the test program, and a message output process of the test program. Address registration means 3 for registering the value of the top address of the part (hereinafter referred to as the top address), read address storage means 4 for storing the address value indicating the address where the simulation is being performed, and address value read from the read address storage means 4. And the start address value registered in the address registration means 3 are compared, and when they match, an address comparison means 5 which outputs a start address detection signal and a machine language instruction of the program under test stored in the program under test storage means 1 Read program Control means 6a, instruction analysis execution means 7a for analyzing and executing the machine language instructions of the loaded test program, message storage means 8 for storing messages, address values for storing messages in the message storage means 8 and The address information register 9 that holds the address value next to the last address value of the message output processing portion of the test program, the address value at which the message of the message storage means 8 is stored, and the last of the message output processing portion of the program under test. A register information reading means 10 for reading the address value next to the address value from the address information register 9, a message reading means 11 for reading a message from the message storing means 8, and a message output for outputting the read message to the message reading means 11. Means 12, address information And a simulation address register 13 to set the next address value of the last address value of the message output processing portion of the test program read from the register 9.

Next, the operation will be described.

In FIG. 1, before starting a simulation of a test program to be debugged, which is stored in the test program storage means 1, an operator (not shown) sends an address from a simulation console (not shown). In the registration means 3, the portion describing the message output operation in the program under test, that is, the head address value of the message output processing portion of the program under test is registered. The address registration means 3 sends an address registration end signal to the simulation control means 2. The registered start address value is sent from the address registration means 2 to the address comparison means 5 and is set inside the address comparison means 5 in advance as a registered address.

Next, when the simulation is started,
A machine language instruction read instruction signal 101 is sent from the simulation control means 2a to the program read control means 6a,
Upon receiving the machine language instruction read instruction signal 101, the program read control means 6a causes the one word read instruction analysis execution means 7a to read the machine language instruction of the test program to be debugged, which is stored in the test program storage means 1. Send out. The instruction analysis execution means 7a analyzes one word of the machine language instruction of the program under test received from the program read control means 6a, and when the analysis of the machine language instruction is completed, the instruction analysis end signal 102 is sent to the simulation control means 2a.
To report that the analysis of the machine language instruction is completed. Next, the instruction analysis executing means 7a executes the analyzed machine language instruction. When the execution of the machine language instruction is completed, the instruction analysis execution means 7a sends an instruction execution end signal 103 to the simulation control means 2a to report that the execution of the machine language instruction is completed. On the other hand, the instruction analysis executing means 7a outputs the message information obtained as a result of the analysis and execution of the machine language instruction and stores it in the message storing means 8 and the address information of the message storing means 8 storing the message information in the address information register 9 Output to. Further, the instruction analysis executing means 7a extracts the address next to the last address of the message output portion and outputs it to the address information register 9 as simulator restart address information when the machine language instruction of the first address is analyzed.

Upon receiving the instruction execution end signal 103, the simulation control means 2a sends the next machine language instruction read instruction signal 101 to the program read control means 6a.
Every time the machine language instruction read instruction signal 101 is received from the simulation control means 2a, the program reading control means 6a reads one machine language instruction next to the program under test in accordance with the address indicated by the machine language instruction read instruction signal 101. It is sent to the analysis executing means 7a. The instruction analysis executing means 7a analyzes and executes the machine language instruction every time it receives the machine language instruction from the program read control means 6a, and sends the instruction analysis end signal 102 and the instruction execution end signal 103 to the simulation control means 2a. To do. In this way, the simulation operation proceeds.

When the simulation control means 2a receives the instruction analysis end signal 102 while the above-mentioned simulation operation proceeds, it sends the address value of the machine language instruction to be executed next to the read address storage means 4. The address value previously stored in the read address storage means 4 is replaced with the latest address newly received from the simulation control means 2a. The simulation control means 2a sends the address value of the machine language instruction to be executed next to the read address storage means 4 and at the same time.
An address comparison instruction signal 104 is sent to the address comparison means 5 in order to compare the already registered head address value with the address value of the machine language instruction to be executed next, which is stored in the read address storage means 4. To do. When the address comparison means 5 receives the address comparison instruction signal 104, the address comparison means 5 compares the head address value with the address value of the machine language instruction to be executed next, which is stored in the read address storage means 4, and when they match, that is, at the head. When an address is detected, the leading address detection signals 105 and 106 are sent to the simulation control means 2a and the register information reading means 10.
Is sent. The simulation control means 2a sends an instruction execution prohibition signal 107 to the instruction analysis execution means 7a, and instructs the instruction analysis execution means 7a not to execute the machine language instruction previously analyzed. Further, the register information reading means 10
From the address information register 9 to the message storage means 8
And the address next to the last address of the message output processing part of the program under test are read. Register information reading means 10
Sends the address in which the message of the message storing means 8 read from the address information register 9 is stored to the message reading means 11. The message reading means 11 reads the message from the message storage means 8 and outputs it to the message output means 12. A message is output by the message output means 12. After outputting the message, the message output means 12 sends a message output completion signal 108 to the simulation control means 2a.

Further, the register information reading means 10 sets the address next to the last address of the message output processing part of the program under test read from the address information register 9 in the simulation address register 13. Upon receiving the message output completion signal 108 from the message output means 12, the simulation control means 2a first reads the address set in the simulation address register 13 from the program read control means 6 and reads the address in the program under test storage means 1. From the machine language instruction read instruction signal 109 for restarting the reading of the machine language instruction. Upon receiving the machine language instruction read instruction signal 109, the program read control means 6 reads the address set in the simulation address register 13 and reads the machine language instruction from that address of the program under test storage means 1 to the instruction analysis execution means 7a. Send out. The instruction analysis executing means 7a resumes the simulation by analyzing and executing the machine language instruction.

In this way, without simulating the message output processing part of the program under test,
A message can be output.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a second embodiment of the simulator of the present invention.

The simulator of the embodiment shown in FIG. 2 includes a test program storage means 1 for storing a test program to be debugged, a simulation control means 2b for controlling a simulation of the test program, and a message output portion of the test program. Address registering means 3 for registering the value of the start address of the above, special instruction code setting means 14 for embedding a special instruction code in the instruction of the start address, read address storing means for storing the address value indicating the address where the simulation is being performed 4, the address value read from the read address storage means 4 and the start address value registered in the address registration means 3 are compared, and when they match, an address comparison means 5 which outputs a start address detection signal, and the test program storage means 1 Tested stored in Message storing means 8 programmed read control means 6b to read machine instructions programs, instruction analyzing execution means 7b which analyzes and executes machine language instructions of the test program is loaded, the message is stored,
An address information register 9 for holding the address value in which the message of the message storage means 8 is stored and the address value next to the last address value of the message output processing part of the program under test, the message of the message storage means 8 is stored. The register information reading means 10 for reading the address value present and the address value next to the last address value of the message output processing portion of the program under test from the address information register 9, the message reading means 11 for reading the message from the message storing means 8, A message output means 12 for outputting the read message to the message reading means 11, a simulation address for setting the address value next to the last address value of the message output processing portion of the program under test read from the address information register 9. And a register 13.

Next, the operation will be described.

In FIG. 2, the head address value of the message output portion of the program under test is set to the address registration means 3
The operation of registering by the above and presetting in the address comparing means 5 is the same as in the case of the first embodiment shown in FIG. In the case of the present embodiment, a special instruction code setting operation is performed as an operation before the start of the simulation operation.

First, when the registration of the leading address by the address registration means 3 is completed, the address registration means 3 sends an address registration end signal to the simulation control means 2b. The simulation control means 2b instructs the program read control means 6b to read the machine language instruction read instruction signal 101.
Is sent. The program read control means 6b reads the machine language instruction stored at the head address of the message output portion of the program under test indicated by the address registration end signal and sends it to the special instruction code setting means 14. The special instruction code setting means 14 embeds a special instruction code not used in the program under test into the machine language instruction at the above-mentioned start address. The machine language instruction of the head address in which the special instruction code is embedded is stored from the special instruction code setting means 14 to the original address of the tested program storage means 1, and the special instruction code setting completion signal is sent from the special instruction code setting means 14. Simulation control means 2b
To the special command code setting operation is completed.

Next, even in the operation after the simulation is started, the program read control means 6b is operated by the machine language instruction read signal from the simulation control means 2b.
Reads the machine language instruction of the program under test stored in the program under test storage means 1 to be debugged and sends it to the instruction analysis execution means 7b, and the instruction analysis execution means 7b analyzes the machine language instruction. The operation in the process of execution is the same as in the first embodiment. Further, as the above-mentioned simulation operation proceeds, the operation in which the address value of the machine language instruction to be executed next is sent from the simulation control means 2b to the read address storage means 4 and stored is the same.

However, in the case of this embodiment, when the simulation control means 2b sends the address value of the machine language instruction to be executed next to the read address storage means 4, the start address is sent to the address comparison means 5. The address comparison instruction signal is not sent in order to compare the value with the address value stored in the read address storage means 4. The address comparison means 5 performs the comparison operation by the instruction analysis execution means 7.
This is when the post-machine instruction is analyzed in b and the special instruction code embedded in the machine language instruction is detected. At this time, the instruction analysis execution means 7b sends the start address detection signal 110 to the simulation control means 2b. The simulation control means 2b receiving the head address detection signal 110 sends the address comparison instruction signal 104 to the address comparison means 5. The address comparing means 5 compares the head address value with the address value of the machine language instruction to be executed next, which is stored in the read address storing means 4,
When they match, that is, when the leading address is detected, the leading address detection signals 105 and 106 are sent to the simulation control means 2b and the register information reading means 10. The subsequent operation is the same as the operation of the first embodiment.

The difference between the operation of the first embodiment and the operation of the second embodiment is that, in the case of the first embodiment, the addresses of the machine language instructions are compared one by one from the beginning until the start address is detected. On the other hand, in the case of the second embodiment, the address considered to be the start address is first detected by using the special instruction code, and then the address comparison means 5 is operated, The point is that the address is compared and detected with the head address registered in advance. In the case of the second embodiment, the number of comparisons made by the address comparing means is reduced, so that the simulation can be made faster than in the case of the first embodiment.

[0026]

As described above, when the simulator of the present invention does not need to simulate the part describing the message output operation in the program, that part is not simulated, and the simulator replaces the program. By outputting the necessary message, the simulation time can be shortened and the debugging efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a simulator of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the simulator of the present invention.

[Explanation of symbols]

 1 test program storage means 2a, b simulation control means 3 address registration means 4 read address storage means 5 address comparison means 6a, b program read control means 7a, b instruction analysis execution means 8 message storage means 9 address information register 10 register information Reading means 11 Message reading means 12 Message output means 13 Simulation address register 14 Special instruction code setting means

Claims (2)

[Claims] 1. A test program storage means for storing a test program to be debugged, (B)
First simulation control means for outputting an address comparison instruction signal, a first machine language instruction read instruction signal, an instruction execution prohibition signal, and a second machine language instruction read instruction signal to control the simulation of the program under test; )
Address registration means for registering the start address of the message output processing portion of the program under test, (D) Read address storage means for receiving and storing the address at which the simulation is performed from the first simulation control means, (E) Address comparison When an instruction signal is received, the address value read from the read address storage means is compared with the leading address value received from the address registering means and preset as a registered address internally, and a leading address detection signal is output when they match. Address comparing means, (F) the machine language instructions of the program under test stored in the program under test storage means are read word by word in response to the first machine language instruction read instruction signal, and the simulation control means is operable to read the machine language instructions. Receives the start address detection signal When the address is taken, the address is read from the address storage means designated by the second machine language instruction read instruction signal as the address of the machine language instruction to be read first from the test program storage means after detection of the head address, First program read control means for reading a machine language instruction stored in the tested program storage means based on the following: (G) a machine language instruction of the tested program read by the first program read control means Analyze and report that the analysis is completed to the first simulation control means, execute the analyzed machine language instruction, output message information obtained as a result of analysis and execution of the machine language instruction, and start the When the machine language instruction of the address is analyzed, next to the last address of the message output The address is extracted and output as simulator restart address information, and when the instruction execution prohibition signal is sent from the first simulation control means that has received the head address detection signal, the analysis-completed machine language instruction is not executed. First instruction analysis and execution means, (H) message storage means for storing the message information, (I) address value at which the message information of the message storage means is stored, and received from the first instruction analysis and execution means An address information register for holding the last address value and the next address value of the message output processing part of the program under test obtained from the simulator restart address information, (J) storing the message when the leading address detection signal is received The address value where the means message is stored and before Register information reading means for reading the address value next to the last address value of the message output processing portion of the test program from the address information register, (K) the message of the message storing means is stored from the register information reading means A message reading means for receiving a read address value from the message storing means, (L) message outputting means for outputting the read message to the message reading means, (M) reading the second machine language instruction A simulation address register for setting an address value next to the last address value of the message output processing part of the program under test read from the address information register, as the address storage means instructed by the instruction signal. Simule characterized by Data. 2. A test program storage means for storing a test program to be debugged, (B) an address comparison instruction signal, a first machine language instruction read instruction signal,
Second simulation control means for controlling the simulation of the program under test by outputting an instruction execution prohibition signal, a second machine language instruction read instruction signal and a third machine language instruction read instruction signal, (C) the program under test Address registration means for registering the start address of the message output processing part of (1), special command code setting means for embedding a special command code in the command of the start address,
(E) Read address storage means for receiving and storing an address to be simulated from the second simulation control means, (F) Address value read from the read address storage means and the address registration read from the read address storage means Address comparison means for receiving from the means and comparing the start address value which is preset inside as a registered address, and outputs a start address detection signal when they match, (G) the third machine language instruction read instruction signal control A signal reads the machine language instruction stored in the head address registered in the address registration means and sends it to the special instruction code setting means, and stores the program under test in response to the first machine language instruction read instruction signal. The machine language instructions of the program under test stored in the means When the second simulation control means reads the word by word and receives the head address detection signal, the second machine language instruction is used as the address of the machine language instruction that is first read from the program under test storage means after the head address is detected. Second program read control means for reading an address from the address storage means designated by the read instruction signal and reading a machine language instruction stored in the tested program storage means based on the address, (H) the second Analyzing the machine language instruction of the program under test read by the program reading control means, reporting to the second simulation control means that the analysis is finished, executing the machine language instruction after the analysis, Outputs message information obtained as a result of analysis and execution of machine language instructions, When the machine language instruction at the start address is analyzed, the address next to the last address of the message output portion is extracted and output as simulator restart address information. As a result of analysis, the machine language instruction of the program under test read in is read. When it is detected that the special instruction code is embedded therein, the address comparison instruction signal for operating the address comparison means is output from the second simulation control means, and the start address detection signal is received. Second instruction analysis executing means for not executing the analyzed machine language instruction when the instruction execution prohibition signal is sent from the second simulation control means, (I) message storing means for storing the message information , (J) Address where the message of the message storage means is stored An address information register for holding a value and an address value next to the last address value of the message output processing part of the program under test, which is obtained from the simulator restart address information received from the second instruction analysis execution means,
(K) When the head address detection signal is received, the address value in which the message of the message storage means is stored and the address value next to the last address value of the message output processing portion of the program under test are set to the address. Register information reading means for reading from the information register,
(L) a message reading means for receiving an address value in which the message of the message storing means is stored from the register information reading means, and reading the message from the message storing means, and (M) a message read to the message reading means. Message output means for outputting, (N) the last address of the message output processing portion of the program under test read from the address information register as the address storage means instructed by the second machine language instruction read instruction signal A simulator comprising a simulation address register for setting an address value next to a value.