JPH084131B2 - Photoelectric conversion device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a photoelectric conversion device of a type that accumulates carriers generated by photoexcitation.

[Prior Art] FIG. 6 (A) is disclosed in JP-A-60-12759.
FIG. 6 (B) is a schematic cross-sectional view of a photoelectric conversion device described in Japanese Unexamined Patent Publication No. 12765, which is an equivalent circuit diagram of one photoelectric conversion cell.

In both figures, photoelectric conversion cells are formed and arranged on an n-silicon substrate 1, and each photoelectric conversion cell is composed of SiO ₂ , Si ₃ N.
₄ , or an element isolation region 2 made of polysilicon or the like, is electrically insulated from an adjacent photoelectric conversion cell.

 Each photoelectric conversion cell has the following configuration.

Low impurity concentration formed by epitaxial technology
A p region 4 is formed on the n ⁻ region 3 by doping a p-type impurity, and an n ⁺ region 5 is formed in the p region 4 by an impurity diffusion technique or an ion implantation technique. P region 4 and n ⁺ region 5 are the base and emitter of the bipolar transistor, respectively.

An oxide film 6 is formed on the n ⁻ region 3 in which each region is formed in this manner, and a capacitor electrode 7 having a predetermined area is formed on the oxide film 6. The capacitor electrode 7 faces the p base region 4 with the oxide film 6 interposed therebetween, and a pulse voltage is applied to the capacitor electrode 7 to control the potential of the p base region 4 in a floating state.

In addition, an emitter electrode 8 connected to the n ⁺ emitter region 5, an n ⁺ region 11 having a high impurity concentration on the back surface of the substrate 1, and a collector electrode 12 for applying a potential to the collector of the bipolar transistor are formed. .

Next, the basic operation will be described. First, it is assumed that the p base region 4 of the bipolar transistor is in a negative potential initial state. Light 13 is incident from the p base region 4 side, holes of the electron-hole pairs generated by the incident light are accumulated in the p base region 4, and the accumulated holes cause the potential of the p base region 4 to change. Rise in the positive direction (accumulation operation).

Then, a positive voltage pulse for reading is applied to the capacitor electrode 7, and a reading signal corresponding to the change in the base potential during the storage operation is output from the emitter electrode 8 in the floating state (reading operation). However, since the accumulated charge amount of the p base region 4 is hardly reduced, the read operation can be repeated.

To remove the holes accumulated in the p base region 4, the emitter electrode 8 is grounded and a positive voltage refresh pulse is applied to the capacitor electrode 7. By applying this pulse, the p region 4 is biased in the forward direction with respect to the n ⁺ emitter region 5, and the accumulated holes are removed. Then, when the refresh pulse falls, the p base region 4 returns to the initial state (refresh operation). Thereafter, the operations of accumulating, reading, and refreshing are similarly repeated.

In short, the method proposed here accumulates the carriers generated by light incidence in the p base region 4, and controls the current flowing between the emitter electrode 8 and the collector electrode 12 by the amount of accumulated charges. is there. Therefore, the accumulated carriers are read after being amplified by the amplification function of each cell, and high output, high sensitivity, and low noise can be achieved.

In addition, the potential Vp generated in the base by carriers (here, holes) accumulated in the base by photoexcitation is
Given by Q / C. Here, Q is the charge amount of holes accumulated in the base, and C is the capacitance connected to the base.
As is clear from this formula, when highly integrated, the cell
As the size is reduced, Q and C are also reduced, and it can be seen that the potential Vp generated by photoexcitation is kept substantially constant. Therefore, the method proposed here is
It can be said that it is also advantageous for high resolution in the future.

[Problems to be Solved by the Invention] However, in the above conventional photoelectric conversion device, the refresh operation for extinguishing the carriers accumulated in the base depends on the forward current between the emitter and the base.
In a short-time refresh pulse, the base potential after refreshing depends on the base potential before refreshing, which causes the problem of afterimage and non-linearity of photoelectric conversion characteristics.

[Means for Solving the Problems] In the photoelectric conversion device according to the present invention, a plurality of photoelectric conversion cells having semiconductor regions for accumulating carriers generated by photoexcitation are arranged, and the semiconductor regions of adjacent photoelectric conversion cells are arranged. Of the plurality of photoelectric conversion cells are turned on by applying a first potential to the gate of the insulated gate transistor so that the insulated gate transistor is turned on. Resetting a signal in a region and applying a gate second potential of the insulated gate transistor to turn off the insulated gate transistor to control so as to separate the semiconductor regions of the plurality of photoelectric conversion cells. Characterize.

[Operation] When the insulated gate transistor is turned on, the potential of the semiconductor region of each cell can be set to a constant potential regardless of the amount of accumulated carriers. Further, when the insulated gate type transistor is turned off, the photoelectric conversion cells can be electrically isolated from each other.

EXAMPLES Examples of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic sectional view of an embodiment of a photoelectric conversion device according to the present invention. However, parts having the same functions as those in FIG. 6 are given the same numbers.

In the figure, p base regions 4 of photoelectric conversion cells are formed at regular intervals in an n ⁻ region 3 which is a collector region. An n ⁺ emitter region 5 is formed in each p base region 4.

Furthermore, the electrode 10 is formed so as to straddle each p base region 4 and each adjacent p base region 4 with the oxide film 6 interposed therebetween.
1 is formed. The electrode 101 on the p base region 4 is p
The capacitor Cox for controlling the base potential is formed facing the base region 4, and the electrode 101 between the adjacent bases is
The adjacent p base region 4 serves as a gate electrode of a MOS transistor Tr having source / drain regions. In this embodiment, the capacitor electrode and the MOS transistor T
The gate electrode of r is connected.

The MOS transistor Tr is a p-channel type and normally-off type in this embodiment, and is in an OFF state if the potential of the electrode 101 is the ground potential or a positive potential. Therefore, the p base region 4 between adjacent cells is electrically isolated,
It is not necessary to form the element isolation region as in the conventional case. That is advantageous for miniaturization of the device.

On the contrary, when the electrode 101 has a negative potential exceeding the threshold potential Vth, the MOS transistor Tr is turned on, and the p-value of each cell is reduced.
The base regions 4 are electrically connected to each other.

FIG. 2 is a partial equivalent circuit diagram of this embodiment. The part surrounded by the broken line in the figure corresponds to the equivalent circuit of one photoelectric conversion cell.

In the figure, the photoelectric conversion cells S _{1 to} Sn are arranged and connected in a line.

The electrode 101 of each cell is commonly connected to the terminal 102,
A pulse φd is input to.

Further, the MOS transistors Tr of the respective cells are connected in series, and p regions (not shown) are formed in the p base regions 4 of the terminal cells S ₁ and Sn at a further fixed distance, respectively. A p-channel type normally-off type MOS transistor Qx is formed on the side of.

A pulse φd similar to the electrode 101 is input to the gate electrode of the MOS transistor Qx, and the p region (not shown) is fixed at a constant potential Vc. The p region (not shown) of the MOS transistor Tr of the cell S ₁ is also fixed to the constant potential Vc.

Therefore, all MOS transistors Tr and Qx are
With the N state, the potential of the p base region 4 of each cell can be set to a constant potential Vc. Further, in the OFF state, each cell is in an electrically separated state.

The emitter electrode 8 of each cell is a reset transistor Qb
_The pulse φr is commonly input to the gate electrodes of the transistors Qb ₁ to Qbn which are grounded via _{1 to} Qbn.

A positive voltage Vcc is applied to the collector electrode 12.

 Next, the operation of this embodiment will be described.

FIGS. 3A to 3C are timing charts showing driving examples of the present embodiment.

 The drive example shown in FIG. 3 (A) will be described.

In the figure, it is assumed that the constant potential Vc is set to the ground potential and carriers are accumulated in the p base region 4 of each cell by the accumulation operation.

First, the pulse φd rises and a positive voltage is applied to the electrode 101 of each cell (period T ₁ ). At this time, since the pulse φr is at the low level, the transistors Qb _{1 to} Qbn are OFF and the emitter electrode 8 of each cell is in a floating state. Also electrode 101
Is a positive potential, the MOS transistor Tr is OFF. Therefore, the potential of the p base region 4 rises via the capacitor Cox, and the read operation already described is performed.

Next, the pulse φr is set to the high level and the transistor Qb
_{1 to} Qbn are turned on, and the emitter electrode 8 of each cell is grounded.

Then, when the pulse φd falls to a negative potential, the MOS transistors Tr and Qx of each cell are turned on, and all p base regions 4 are turned on. As a result, the base potential is uniformly set to the ground potential Vc in the period T ₂ regardless of the accumulated potential.

When the pulse φd rises to the ground potential after the period T ₂ has elapsed, the base potential rises by the capacitance-divided potential and becomes a positive potential.

For this reason, the carriers accumulated in the p base region 4 disappear in the period T ₃ , but in this refresh operation, the base potential is not in the initial state of a negative potential (reverse bias state between the base and the emitter). Then, pulse φ
The refresh operation is performed when d rises to a positive potential. Then, when the pulse φd falls after the lapse of the period T ₄ , the base potential returns to the initial state of negative potential.
Thereafter, the accumulation operation is started and the above operations are repeated.

Thus, the pulse φd causes the MOS transistor Tr
In order to perform the refresh operation in the periods T ₃ and T ₄ after setting the base potential to the constant potential Vc with the ON state,
The base potential after refreshing can be reliably kept at a constant level regardless of the potential before refreshing.

Besides the period T ₂ , the MOS transistor Tr of each cell is
Is in the OFF state, the electrical isolation of each cell is realized. That is, it is possible to achieve electrical isolation of cells without forming an element isolation region as in the conventional case, and to promote miniaturization of cells.

The driving example shown in FIG. 3B shows a driving method in which Vc is fixed to a negative voltage and a refresh pulse is not applied.
That is, by setting the pulse φd to a negative potential in the period T ₂ , the MOS transistor Tr is made conductive and the base potential is set to the initial state of the negative potential Vc. Therefore, the storage operation can be started without applying the refresh pulse.

The driving example shown in FIG. 3 (C) is a method of obtaining an output by a phototransistor operation and is suitable for a line sensor.

First, Vc is fixed to the ground potential, and the pulse φd is set to the negative potential to make the MOS transistor Tr conductive and set the base potential to the ground potential. When the pulse φd rises to the ground potential, the base potential rises to the positive potential. Then, a refresh operation is performed while the emitter electrode 8 is grounded by the pulse φr, and the emitter electrode 8 is brought into a floating state by the fall of the pulse φr, and at the same time, the storage and read operations are started.

FIG. 4 is a schematic circuit diagram of the second embodiment of the present invention.

The present embodiment is an m × n area sensor having a structure in which the line sensors shown in FIG. 2 are overlapped by m lines. However,
Each line has the structure shown in FIG. 1, but a normal element isolation region is formed between the lines to electrically isolate the lines.

The electrodes 101 of the cells in each line are commonly connected and connected to the terminal 102 via the switches SW _{1 to} SWm, respectively. The pulse φd is input to the terminal 102.

The switches SW _{1 to} SWm are analog switches, the control terminals of which are connected to the output terminals of the vertical scanning circuit 103, and the outputs φv _{1 to} φvm control ON / OFF.

The emitter electrode 8 of each cell has vertical lines L _{1 to} Ln for each column.
It is connected to the. The vertical lines L _{1 to} Ln are grounded through the reset transistors Qb _{1 to} Qbn, and the transistor Qb ₁
A pulse φr is input to the gate electrodes of Qbn.

The vertical lines L _{1 to} Ln are connected to the storage capacitors C _{1 to} Cn via the transistors Qa _{1 to} Qan, respectively, and the capacitors C _{1 to} Cn are output lines via the transistors Q _{1 to} Qn.
Connected to 104.

A pulse φt is commonly input to the gate electrodes of the transistors Qa _{1 to} Qan, and pulses φh _{1 to} φhn from the horizontal scanning circuit 105 are input to the gate electrodes of the transistors Q _{1 to} Qn, respectively.

The output line 104 is grounded via the transistor Qrh and connected to the input terminal of the amplifier 106. A pulse φrh is input to the gate electrode of the transistor Qrh.

 The above-mentioned pulses φ are supplied from the control unit 107.

In addition, a constant potential for setting the base potential of each cell
Vc is the main potential Vc is the ground potential in this embodiment.

 Next, the operation of this embodiment will be briefly described.

FIG. 5 is a partial timing chart showing a driving example of the present embodiment. However, the drive method shown in FIG. 3 (A) is used here.

First, only the pulse φv ₁ of the vertical scanning circuit 103 is set to a high level and the switch SW ₁ is turned on. Also, the pulse φ
Then, t is set to the high level to turn on the transistors Qa _{1 to} Qan.

Next, when the pulse φd is set to a positive potential for the period T ₁ , a positive voltage is applied to the electrodes 101 of the cells S _{11 to} S ₁ n on the first line through the switch SW ₁ . As a result, the read operation of the first line is performed, and the read signal of the first line is changed to the vertical lines L _{1 to} Ln.
And the capacitors C _{1 to} Cn are respectively stored through the transistors Qa _{1 to} Qan.

Next, the pulse φt goes low and the transistor Qa
_{1 to} Qan are turned off. Then, the pulses φh _{1 to} φhn are sequentially output from the horizontal scanning circuit 105, and the read signals accumulated in the capacitors C _{1 to} Cn are sequentially output line 10 according to the pulses.
The output signal Vout is output to the outside through the amplifier 106 and is serially output as an output signal Vout. Note that the pulse φrh rises each time each read signal is output,
The carrier of the output line 104 is removed by turning on Qrh.

In parallel with this signal output operation, the pulse φr is set to the high level to turn on the transistors Qb _{1 to} Qbn, and the vertical line L ₁
Ground ~ Ln. Further, the pulse φd is set to a negative potential in the period T ₂ , and the MOS transistor Tr on the first line is turned on.

As a result, the potentials of the p base regions 4 of the cells S _{11 to} S _1n are uniformly set to the ground potential Vc, and as described above, the refresh operation in the periods T ₃ and T ₄ restores the initial negative potential. , Start the accumulation operation.

When the operation of the first line is completed in this way, the pulse φv ₁
Goes down, and the switch SW ₁ is turned off. Then, the pulse φt rises to turn on the transistors Qa _{1 to} Qan. As a result, carriers remaining in the capacitors C _{1 to} Cn are transferred to the vertical lines L _{1 to} Ln and the transistors Qa _{1 to} Qan.
Remove through.

Thereafter, the same operation is performed for each line, and the read signals of the 2nd to mth lines are sequentially output.

Also in this embodiment, the base potential of the cells on each line is set to a constant potential in the period T ₂ , and then the refresh operation is performed in the periods T ₃ and T ₄ , so that the afterimage characteristics are favorable and the photoelectric conversion characteristics are good. It is possible to obtain an image pickup device having good linearity. In addition, since no element isolation region is required in the line direction here, it is suitable for miniaturization of cells and can easily cope with high resolution.

[Effects of the Invention] As described in detail above, the photoelectric conversion device according to the present invention has an insulated gate transistor in which semiconductor regions of adjacent photoelectric conversion cells are used as main electrode regions. In the ON state, the potential of the semiconductor region of each cell can be easily set to a constant potential regardless of the amount of accumulated carriers. Therefore, the afterimage problem is solved and the linearity of the photoelectric conversion characteristic is improved.

Furthermore, if the insulated gate transistor is turned off, the photoelectric conversion cells can be electrically isolated from each other, and it is not necessary to form an element isolation region as in the conventional case.
The manufacturing process is simplified, and the device is suitable for miniaturization.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of a photoelectric conversion device according to the present invention, FIG. 2 is a partial equivalent circuit diagram of this embodiment, and FIGS. 3 (A) to (C) are respectively Timing chart showing a driving example of the present embodiment, FIG. 4 is a schematic circuit diagram of a second embodiment of the present invention, FIG. 5 is a partial timing chart showing a driving example of the present embodiment, and FIG. FIG. 1A is a diagram of JP-A-60-12759 to JP-A-60-1.
A schematic cross-sectional view of the photoelectric conversion device described in Japanese Patent No. 2765, FIG. 6 (B), is an equivalent circuit diagram of the one photoelectric conversion cell. 1 ... n type substrate 3 ... n ^- epitaxial layer (collector region) 4 ... p base region 5 ... n ⁺ emitter region 6 ... oxide film 7 ... capacitor electrode 8 ... emitter electrode 12 ... collector electrode 101 ... Electrode

Claims (1)

[Claims] 1. A plurality of photoelectric conversion cells having a semiconductor region for accumulating carriers generated by photoexcitation are arranged, and an insulated gate transistor is formed by using the semiconductor regions of adjacent photoelectric conversion cells as main electrode regions. By applying a first potential to the gate of the insulated gate transistor, the insulated gate transistor is turned on to reset the signals in the semiconductor regions of the plurality of photoelectric conversion cells. A photoelectric conversion device, wherein the insulated gate transistor is turned off by applying a second potential to the gate to control so as to separate the semiconductor regions of the plurality of photoelectric conversion cells.