JPH0837547A - Digital processing circuit for radio equipment - Google Patents

Abstract

PURPOSE:To decrease power consumption by lowering the clock frequency of a linear feedback shift register by operating this circuit at the clock frequency of lower speed than the clock frequency of a multilevel modulator or demodulator. CONSTITUTION:Either a multilevel modulated input side circuit connected to the input side of the multilevel modulator of a transmitter or a multilevel demodulated output side circuit connected to the output side of the multilevel demodulator of a receiver is composed of a linear feedback shift register 10 combining and connecting plural register circuits (S0 to S9) and plural exclusive OR 40A and 40B so as to be parallelly operated corresponding to the bit width of an input to the multilevel modulator or an output from the multilevel demodulator at least. A parallelly processed two-bit output 8 of the linear feedback shift register 10 is respectively inputted to the exclusive OR 4A and 4B and consists of a descrambler circuit 11. In this case, the circuit is operated at the clock frequency of lower speed than the frequency of a clock at a bit rate provided for the multilevel modulator or demodulator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear return ring shift register for processing transmission / reception digital data of a radio, and particularly, this linear return ring register is effective when an interface circuit has a plurality of bit widths. The present invention relates to a digital processing circuit of a wireless device.

[0002]

2. Description of the Related Art It is well known that a scrambler is generally used in a conventional wireless device such as a second generation cordless telephone system. That is, the scrambler converts the transmission data sequence into a random sequence irrelevant to the input by adding the input data sequence with the pseudo random data sequence. On the receiving side, the original sequence is restored by a descrambler that performs inverse scrambler conversion. The scrambler makes the changes in the amplitude, polarity, and phase of the transmitted signal appear even on average even if the input data has periodicity or a fixed pattern, and facilitates the timing extraction of the signal change point on the receiving side. Used to At the same time, there is an effect that the spectrum distribution of the transmission signal is spread over the entire band. This is well known, for example, it becomes suitable for correcting the characteristics of the entire band when the adaptive equalizer is used on the receiving side.

6 and 7 show a second-generation cordless telephone system standard (draft) RCR STD-28 (hereinafter RC).
Called R STD-28. ) Is a diagram showing an execution procedure of the scrambling method and the descrambling method defined in (1). In each process, a register initial value S is set for each frame, and a pattern corresponding to a predetermined pattern number N set in advance is set. It is executed by adding P and the transmission data or the reception data by an exclusive OR Ex _x OR.

FIG. 8 is a block diagram of a receiving system of a conventional radio device related to the descramble of FIG. 7 described above. Since the transmitting system has a configuration symmetrical to this as shown in FIG. 6, its description is omitted. . In FIG. 8, reference numeral 1 is a 4-value demodulator that demodulates a 4-level modulated reception signal on the transmitter side and outputs a 2-bit demodulation signal 1A. Reference numeral 2 denotes a parallel-serial conversion circuit which converts a 2-bit parallel signal into serial data 2A. Reference numeral 3 denotes a linear return shift register, which will be described later, and 4 denotes an exclusive OR, which is similar to the exclusive OR Ex OR of FIG. 6 is a descrambler circuit, which is composed of the linear return shift register 3 and the exclusive OR 4;
Reference numeral 7 is output data of the descrambler circuit 6.

FIG. 9 is a detailed view of the linear return ring shift register 6 shown in FIG. 8, in which the same reference numerals as those in FIG. 8 indicate the same or corresponding portions. In the figure, 40 is an exclusive OR ExOR, and 5 is register circuits S0 to S9, respectively, and the linear return register 3 connects the exclusive OR ExOR and register circuits S0 to S9 in a ring shape as shown in the figure. And is operated sequentially according to a clock pulse (not shown). The details of the linear return ring shift register are well known in "Modern Cryptography" edited by the Institute of Electronics and Communication Engineers, and the detailed description thereof is omitted below.

Next, the operation of the descrambler on the receiver side shown in FIGS. 8 and 9 will be described. The 4-valued demodulator 1 shown in FIG. 8 inputs a receiver signal and outputs a 2-bit demodulated signal 1A per symbol clock. The parallel-serial conversion circuit 2 converts the 2-bit demodulated signal 1A into the symbol rate 2
It is converted into 1-bit serial data 2A with a clock having a bit rate of double the frequency. The descramble circuit 6 uses a bit rate clock to generate an M series (maximum length
Sequence) is generated and the scramble applied by the transmitting side is released. In this way, the linear return ring shift register 3 of the descramble circuit 6 operates with a clock having a bit rate twice the frequency of the clock of the quaternary demodulator 1.

The linear return shift register on the transmitter side (not shown) is also the linear return shift register 3 on the receiver side.
Similarly, it will operate faster with twice the clock.

FIG. 10 shows an RCR STD-28 as a digital processing circuit on the receiver side, which receives the output data 7 of the descramble circuit 6 of FIG. 8 or the serial data 2A.
FIG. 6 is a block diagram of a confidentiality cancellation circuit 8 defined by 1. In the figure, the same reference numerals as those in FIGS. 8 to 9 indicate the same or corresponding parts, 81 is a concealment canceling circuit input, 82 is a concealment canceling circuit output, 84 is an exclusive OR Ex OR, and the input 81 is the same as in FIG. The output data 7 or the serial data 2A is input. The cipher release circuit 8 includes a plurality of shift register circuits 5 and exclusive OR 41A to 41C and shift register circuits S0 to S15 and exclusive OR Ex O as shown in FIG.
R is connected, and is composed of a linear return shift register similar to FIG. Like the descramble circuit 6 of FIG. 9, such a linear return shift register also operates with a clock having a bit rate of twice the frequency of the clock of the quaternary demodulator 1.

FIG. 11 is a block diagram of a CRC (cyclic code) detection circuit 9 defined by RCR STD-28 as a digital processing circuit on the receiver side. In the figure, the same reference numerals as those in FIGS. 8 to 10 indicate the same or corresponding portions, 91 is a CRC detection circuit input, and the CRC detection circuit 9 shows a plurality of register circuits 5 and exclusive ORs 42A to 42C. As shown in, the register circuits S0 to S15 and the exclusive OR E
It is a return return connection of x OR, and is composed of a linear return return shift register similar to FIG. Such a linear return ring shift register has the same structure as the descrambling circuit 6 of FIG.
It operates with a clock having a bit rate of twice the frequency of the clock of the value demodulator 1. Although the above-described example has been described with respect to the receiver side, the same applies to the transmitter-side concealment circuit and the CRC encoding circuit paired with these.

[0010]

Since the linear return shift register on the transmitter side or the receiver side of the conventional radio device is constructed as described above, the modulator or demodulator adopts four-value modulation. In this case, a clock frequency having a bit rate twice as fast as the symbol rate clock of the modulator / demodulator is required. On the other hand, it is known that when the clock frequency of the linear return ring shift register becomes higher, the power consumption of the linear return ring shift register composed of C-MOS increases in proportion to this, and therefore when the clock frequency becomes higher. Power consumption will also increase proportionately. On the other hand, with regard to wireless devices, especially mobile phones, attention has recently been paid to downsizing in size, high-performance rechargeable batteries capable of operating for a long time with one charge, and power saving of operating circuits. LS
Saving power consumption of the I semiconductor circuit was also an issue.

The present invention has been made in view of the above problems, and at least one of linear return ring shift registers used in various circuits of a transmitter or a receiver of a multilevel modulation radio device. Another object of the present invention is to provide a digital processing circuit of a radio device, which operates at a clock frequency lower than the clock frequency of the modulator or the bit rate of the receiver.

[0012]

A digital processing circuit of a radio device according to the present invention is a multi-level modulation input side circuit connected to an input side of a multi-level modulator of a transmitter or a multi-level demodulator of a receiver. At least one of the multilevel demodulation output side circuits connected to the output side of the plurality of register circuits and a plurality of register circuits so as to operate in parallel corresponding to the bit width of the input of the multilevel modulator and the output of the multilevel demodulator. It is composed of a linear return-shift register which is connected in combination with the exclusive OR of and is operated at a clock frequency lower than the clock frequency of the bit rate possessed by the multilevel modulator or demodulator.

Further, in the digital processing circuit of the radio device according to the present invention, the multi-level modulator / demodulator is composed of a four-level modulator / demodulator, and 2-bit parallel or parallel signals corresponding to the input of the 4-level modulator or the output of the demodulator are provided. This is a linear return ring shift register that operates in parallel with a 2-bit integer multiple bit.

Further, in the digital processing circuit of the radio device according to the present invention, the linear return ring shift register in which a plurality of register circuits and a plurality of exclusive ORs are connected in combination is a scramble circuit, a descrambler circuit, a secret circuit, It functions as at least one circuit function of the confidentiality cancellation circuit, the CRC encoding circuit, and the CRC detection circuit.

Furthermore, the digital processing circuit of the radio device according to the present invention is a serial / parallel conversion circuit or a parallel / serial conversion circuit that absorbs the difference in bit width between circuits when the bit widths processed in parallel are different. A conversion circuit is provided.

[0016]

The digital processing circuit of the radio device according to the present invention is
A linear return shift register in which a plurality of register circuits and a plurality of exclusive ORs are connected in combination so as to operate in parallel corresponding to the bit width of the input of the multilevel modulator or the output of the multilevel demodulator, Since the clock frequency is lower than the clock frequency of the multi-level modulator or demodulator, the clock frequency of the linear return shift register is lower than that of the conventional one.

Further, the digital processing circuit of the radio device according to the present invention is a linear return ring shift register which operates in 2-bit parallel to 2-bit integer multiple bit parallel corresponding to the input of the quaternary modulator or the output of the demodulator. In the case of 2-bit parallel, the input of the 4-value modulator or the output of the demodulator and the digital processing circuit having the linear return ring shift register can be directly connected, and in the case of 2-bit integer multiple bit parallel, The clock frequency of the linear return shift register becomes slow.

Further, in the digital processing circuit of the radio device according to the present invention, a linear return shift register in which a plurality of register circuits and a plurality of exclusive ORs are connected in combination is a scramble circuit, a descrambler circuit, a secret circuit, Since it is made to function as at least one circuit function of the confidentiality cancellation circuit, the CRC encoding circuit, and the CRC detection circuit, the clock frequency of at least one circuit of these digital processing circuits operates at a slower clock frequency. .

Furthermore, the digital processing circuit of the radio device according to the present invention is a serial-parallel conversion circuit or parallel-serial conversion circuit that absorbs the difference in bit width between circuits when the bit widths processed in parallel are different. Since the conversion circuit is provided, the digital processing circuit on the parallel side operates at a slower clock frequency.

[0020]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to FIGS.
Will be explained. FIG. 1 is a block diagram of a main part including a descrambler circuit 11 as a digital processing circuit of a wireless device provided on the receiver side corresponding to FIG. 8, and the same reference numerals as those in FIG. 8 denote the same or corresponding parts. In FIG. 1, reference numeral 10 denotes a parallel-processed linear return shift register, the 2-bit outputs of which are input to exclusive ORs 4A and 4B, respectively.
It constitutes the descrambler circuit 11. 8 is
This is a 2-bit width descrambler circuit output. Figure 2
2 is a detailed circuit diagram of the descrambler circuit 11 of FIG.
In the figure, the same reference numerals as those in FIG. 9 denote the same or corresponding parts. In the figure, 40A and 40B are exclusive ORs, and 5 is register circuits S0 to S9. The linearly-returned shift register 10 that has been processed in parallel constitutes a linearly-returned shift register that operates in parallel for 2 bits by the exclusive ORs 40A and 40B and a plurality of register circuits S0 to S9.

Next, the operation of what is shown in FIGS. 1 and 2 will be described. In order to describe the operation of the linear return shift register 10 according to the embodiment of the present invention, the operation of the conventional example will be described first. FIG. 9 is a circuit diagram including the conventional linear return ring shift register 3, and the operation of the linear return ring shift register 3 in FIG. 9 is expressed as follows using an equation. That is, dFF (*) _t (* = 0 to 9) is set as the current value of the register circuits S0 to S9, and dFF (*) _{t + 1} (*
= 0 to 9) to the next timing register circuits S0 to S9
Then, the values of the register circuits S0 to S9 in FIG. Here, + is an exclusive OR. dFF (0) _{t + 1} = dFF (1) _t dFF (1) _{t + 1} = dFF (2) _t dFF (2) _{t + 1} = dFF (3) _t dFF (3) _{t + 1} = dFF (4 ) _T dFF (4) _{t + 1} = dFF (5) _t dFF (5) _{t + 1} = dFF (6) _t dFF (6) _{t + 1} = dFF (7) _t dFF (7) _{t + 1} = dFF (8) _t dFF (8) _{t + 1} = dFF (9) _t dFF (9) _{t + 1} = dFF (0) _t + dFF (5) _t Therefore, the above formula outputs 1-bit data every 1 clock. The linear return ring shift register 3 is configured, and the descrambler circuit 6 of FIG.
There XOR is taken by E _x OR @ 4 in the value of the register circuit S0, will be descrambled. The above is the operation of the conventional example, but by applying this expression twice, the following expression according to the embodiment of the present invention can be obtained. That is,
Here, dFF (*) _{t + 2} (* = 0 to 9) is dFF _{t + 1}
If the values of the register circuits S0 to S9 at the timing next to (*) are assumed, the values of the register circuits S0 to S9 at this time satisfy the following equation. Here, + is also an exclusive OR. dFF (0) _{t + 2} = dFF (2) _t dFF (1) _{t + 2} = dFF (3) _t dFF (2) _{t + 2} = dFF (4) _t dFF (3) _{t + 2} = dFF (5 ) _T dFF (4) _{t + 2} = dFF (6) _t dFF (5) _{t + 2} = dFF (7) _t dFF (6) _{t + 2} = dFF (8) _t dFF (7) _{t + 2} = dFF (9) _t dFF (8) _{t + 2} = dFF (0) _t + dFF (7) _t dFF (9) _{t + 2} = dFF (1) _t + dFF (8) _{t The} above expression is expanded to hardware. Is the linearly-returned shift register 10 processed in parallel in FIG.
2-bit parallel data 1A from the 4-valued demodulator 1
Is a register circuit S that operates in parallel every time one clock is input to the linear return shift register 10 shown in FIG.
The values of 0 and S1 are simultaneously exclusive-ORed by the EX ORs 4A and 4B, and the data for 2 clocks of the conventional linear return shift register 3 of FIG. The width descrambler circuit output 8 is output.

As described above, according to the first embodiment of the present invention, the operating frequency of the descrambler circuit 11 becomes low because the clock frequency of the linear return-shift register 10 becomes 1/2, and normally this type of circuit is used. Thus, the operating speed of the C-MOS semiconductor circuit that constitutes the device becomes low, and low power consumption can be realized. As described above, in the portable telephone as a radio device, the power saving of the descrambler circuit 11 is achieved by increasing the performance of the rechargeable battery and increasing the operating time for one charge or one battery exchange. This makes it possible to reduce the size of a portable wireless device.

Further, according to the first embodiment of the present invention, since the 2-bit descrambler output data 8 is given to the 2-bit output 1A of the 4-level demodulator 1, the matching is good, and the conventional one shown in FIG. The parallel-serial conversion circuit 2 can be made unnecessary as compared with the output side circuit of the four-valued demodulator 1.

In the first embodiment of the present invention, the descrambler circuit on the receiver side of the wireless device has been described. However, as is clear from FIGS. 6 and 7, the scrambler circuit on the transmitter side of the wireless device is also used in the above embodiment. It has the same effect as 1. In addition,
When configured as this scrambler circuit, the configuration of the linear return ring shift register to be processed in parallel is similar to that of the circuit shown in FIG. 2, and is connected to the input side of the four-value modulator (not shown) of the transmitter. The multi-valued modulation input side circuit is a scramble circuit.

Example 2. Next, as a second embodiment of the present invention, in the case where the input side of the four-level demodulator on the receiver side of the radio device or the multi-level demodulation output side circuit connected via the descramble circuit is the concealment canceling circuit. explain. This circuit is also the RCR ST, as described as the conventional example in FIG.
D-28 deciphering circuit shown in the same manner as in Example 1 a plurality of shift register circuit 5 and a plurality of exclusive OR E _x O
The descrambling circuit is shown in FIG. 3 and will be described below. 3, the same reference numerals as those in FIG. 2 indicate the same or corresponding portions, and 41A to 41I are exclusive OR Ex _x OR. Reference numeral 14 denotes a 2-bit parallel processed deciphering circuit input, which is connected to the output signal 1A to the descrambler circuit output of the 4-valued demodulator 1 shown in FIG. 2, and the output of the linear return ring shift register of FIG. For each shift clock, an exclusive OR is taken with the anonymity canceling circuit input 14 to output an anonymized 2-bit anonymity canceling circuit output 12. Thus, the one shown in FIG. 3 has the same function as that of the conventional example shown in FIG. 10, and the conventional two clocks of data can be deciphered in one clock of one time. It has the same effect as 1. In the above description of the second embodiment, the cipher release circuit on the receiver side of the wireless device has been shown and described in FIG. 3, but the same effect can be obtained by the cipher circuit on the transmitter side. That is, when configured as the secret circuit, the linear return shift register to be processed in parallel is the same as the circuit shown in FIG. 3, and the input side of the four-value modulator (not shown) of the transmitter or the scrambler is used. The multilevel modulation input side circuit connected via a circuit (not shown) serves as a secret circuit.

Example 3. Next, as a third embodiment of the present invention, a case where a multi-level demodulation output side circuit connected via an input side of a four-level demodulator on the receiver side of a radio device or a descrambler circuit is a CRC detection circuit will be described. . This CR
As described in the conventional example of FIG.
The CRC detection circuit shown in CR STD-28 is composed of a linear return ring shift register in which a plurality of register circuits 5 and a plurality of exclusive ORs Ex OR are connected in combination as in the first embodiment. The circuit is shown in FIG. 4 and described. In FIG. 4, reference numerals 43A to 43F denote exclusive OR ExOR, which constitute a linear return-shift register operating in 2-bit parallel as in the first embodiment described with reference to FIG. The CRC detection circuit input 16 is sequentially added to the linear return loop feedback shift register in units of 2 bits, and the linear feedback shift register operates as a divider and performs a CRC check by obtaining a residue. In addition,
CRC detection is processed in units of a predetermined data block, and the data in each of the registers S0 to S15 is converted into C at a predetermined timing.
A microcomputer control program (not shown) or the like for RC inspection reads and makes a determination, and the details of its operation are omitted. As described above, the third embodiment of the present invention shown in FIG. 4 has the same function as that of the conventional example shown in FIG. 11, and the conventional two blocks of data are CRC'd in one clock for one time.
The operation for detection can be performed, and the same effect as that of the first embodiment can be obtained. In the description of the third embodiment, the CRC detection circuit on the receiver side of the radio device is shown and described in FIG. 4, but it can be used as the CRC encoding circuit on the transmitter side. Has the same effect.

Example 4. Next, as a fourth embodiment of the present invention, an anonymity canceling circuit that performs 8-bit parallel processing will be described with reference to FIG. In each of the first to third embodiments described above, the linear return ring shift register processed in parallel with 2 bits has been described as an example, but in the fourth embodiment, a plurality of bits that are an integral multiple of 2 bits, for example, 8 bits are parallel. The linear return ring shift register operates at a slower speed. FIG. 9 shows a circuit block after the four-level demodulator on the receiver side of the wireless device, and the same reference numerals in FIG. 1 to FIG. 4 indicate the same or corresponding parts. In the figure, reference numeral 21 denotes a received signal, which is input to the 4-level demodulator as in FIG. 1 and outputs a 2-bit demodulated signal 1A. Reference numeral 20 denotes a data processing circuit, which handles, for example, digitally coded received data as 8-bit data and performs predetermined digital signal processing. Reference numeral 19 denotes a parallel processing concealment canceling circuit, which is configured by a linear return ring shift register (not shown) operating in 8-bit parallel to the linear return ring shift register operating in 2-bit parallel in FIG. Minute data is deciphered in one clock. In the configuration as shown in FIG. 5, the 2-bit data of the output 1A of the quaternary demodulator 1 is processed in parallel. After being processed by the descrambler circuit 11 in FIG. 2 and the CRC detection circuit 17 in FIG. Data 1 every 8 bits in the parallel conversion circuit 18
8A. The 8-bit data 18A is processed in 8-bit units in the deciphering circuit 19 which is processed in parallel.
The deciphered output data 19A is input to the data processing circuit 20.

As described above, according to the fourth embodiment of the present invention, the 2-bit demodulated signal 1A of the 4-valued demodulator 1 is converted by the serial-parallel conversion circuit 18 into 4 times as many as 8 bits. Since the anonymity canceling circuit 19 operates, the linear return shift register in the circuit operates with a clock of 1/8 of that in the conventional case, and operates at a lower speed, which further reduces the power consumption of the circuit used. I can.

In the description of the fourth embodiment, the cipher release circuit on the receiver side has been described, but it is obvious that the cipher circuit on the transmitter side can be combined with the parallel-serial conversion circuit. Further, as an embodiment of the present invention, a scrambler / descrambler circuit, a concealment / deconcealment circuit, and a C
Although the RC encoding / CRC detecting circuit has been described, the present invention is also applicable to digital processing circuits of other wireless devices.

[0030]

The digital processing circuit of the radio device according to the present invention has a plurality of register circuits and a plurality of exclusive circuits so as to operate in parallel corresponding to the bit width of the input of the multilevel modulator or the output of the multilevel demodulator. Since it is composed of a linear return ring shift register that is connected in combination with OR, and operated at a clock frequency lower than the clock frequency of the multilevel modulator or demodulator,
The clock frequency of the linear return shift register is lower than that of the conventional one, and the power consumed by this shift register can be reduced.

Further, the digital processing circuit of the wireless device according to the present invention is a linear return shift register operating in 2-bit parallel to 2-bit integer multiple bit parallel corresponding to the input of the 4-value modulator or the output of the demodulator. In the case of 2-bit parallel, the input of the 4-value modulator or the output of the demodulator and the digital processing circuit having the linear return ring shift register are directly connected to each other, and the serial-parallel to parallel-serial conversion circuit which has been conventionally required. In the case of 2-bit integer multiple bit parallelization, the clock frequency of the linear return shift register becomes slower and the power consumption can be reduced.

Further, in the digital processing circuit of the radio device according to the present invention, the linear return ring shift register in which a plurality of register circuits and a plurality of exclusive ORs are combined and connected includes a scramble circuit, a descrambler circuit, a secret circuit, Since it is made to function as at least one circuit function of the confidentiality cancellation circuit, the CRC encoding circuit, and the CRC detection circuit, the clock frequency of at least one circuit of these digital processing circuits operates at a slower clock frequency. ,
This can reduce the power consumption.

Furthermore, the digital processing circuit of the radio device according to the present invention is a serial / parallel conversion circuit or a parallel / serial conversion circuit that absorbs the difference in bit width between circuits when the parallel processed bit widths of the circuits are different. Since the conversion circuit is provided, the digital processing circuit on the parallel side operates at a slower clock frequency, which can further reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part including a receiver-side descrambler circuit as a digital processing circuit of a wireless device according to a first embodiment of the present invention.

FIG. 2 is a descrambler circuit diagram according to the first embodiment of the present invention.

FIG. 3 is a concealment canceling circuit as a digital processing circuit of a wireless device according to a second embodiment of the present invention.

FIG. 4 is a descrambler circuit as a digital processing circuit of a wireless device according to a third embodiment of the present invention.

FIG. 5 is a circuit block diagram on a receiver side of a wireless device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram for explaining an execution procedure of a scramble method of a wireless device.

FIG. 7 is a diagram illustrating an execution procedure of a descrambling method of a wireless device.

FIG. 8 is a block diagram of a main part including a descrambler circuit of a conventional wireless device.

FIG. 9 is a conventional descrambler circuit diagram.

FIG. 10 is a conventional cipher release circuit diagram.

FIG. 11 is a conventional CRC detection circuit diagram.

[Explanation of symbols]

1 4-value demodulator, 2 parallel-serial converter, 3 linear return shift register, 4 exclusive OR, 5 register circuit,
6 descrambler circuit, 7 descrambler circuit output, 8 2 bit width descrambler circuit output, 9 concealment cancellation circuit output, 10 parallel linear return shift register, 11 parallel processed descrambler circuit,
12 Parallel processing anonymization circuit output, 14 Parallel processing anonymization circuit input, 16 Parallel processing CR
C detection circuit input, 17 CRC processing circuit processed in parallel, 18 serial-parallel conversion circuit, 19 concealment removal circuit processed in parallel, 20 data processing circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04L 9/00 B

Claims (4)

[Claims] 1. In a digital processing circuit of a multilevel modulation wireless device, a multilevel modulation input side circuit connected to an input side of a multilevel modulator of a transmitter or an output side of a multilevel demodulator of a receiver. At least one of the multilevel demodulation output side circuits connected to
It is configured by a linear return shift register in which a plurality of register circuits and a plurality of exclusive ORs are connected in combination so as to operate in parallel corresponding to the bit width of the input of the multilevel modulator or the output of the multilevel demodulator. A digital processing circuit for a wireless device, wherein the linear return-shift register is operated at a clock frequency lower than the clock frequency of the bit rate of the multilevel modulator or the multilevel demodulator. 2. A multi-level modulation or demodulator is a four-level modulator or 4
It is characterized in that it is constituted by a value demodulator and a linear return ring shift register which operates in 2-bit parallel or 2-bit integer multiple bit parallel corresponding to the input of the 4-value modulator or the output of the demodulator. The digital processing circuit of the wireless device according to claim 1. 3. A linear return-shift register, which is connected in combination with a plurality of register circuits and a plurality of exclusive ORs, comprises a scrambler circuit, a descrambler circuit, a concealment circuit, a concealment circuit, a CRC encoding circuit, or a CRC. 2. The digital processing circuit for a wireless device according to claim 1, wherein at least one circuit function of the detection circuit is made to function. 4. The multi-level modulator input side circuit is any one of a scramble circuit, a concealment circuit, and a CRC encoding circuit, and the multi-level demodulator output side circuit is any of a descramble circuit, a concealment cancellation circuit, and a CRC detection circuit. Consists of
One or more of a scrambler circuit or descrambler circuit, a concealment circuit or a concealment circuit, or a CRC encoding circuit or a CRC detection circuit having a linear return ring shift register operating in parallel is provided, and each circuit is processed in parallel. If the bit widths differ from each other, the serial-parallel conversion circuit provided in the multi-value modulator input side circuit or the parallel series provided in the multi-value demodulator output side circuit that absorbs the difference in bit width between the circuits 2. The digital processing circuit for a wireless device according to claim 1, further comprising one or both of the conversion circuits.