JP2000261423A - Encryption device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an encryption processing rate by about twice without the need for using a memory with a large scale. SOLUTION: A block division means 13 of this encryption device divides an input packet into blocks and alternately output them to a 1st encryption means 11 and a 2nd encryption means 12. The 1st encryption means 11 uses 2nd intermediate data to encrypt the blocks and outputs the 1st intermediate data and the encrypted 1st block. The 2nd encryption means 12 starts its processing with a delay required for the 1st encryption means 11 to process the 1st intermediate data, uses the 1st intermediate data to encrypt the block and outputs 2nd intermediate data and the encrypted 2nd block. A block coupling means 14 couples the encrypted 1st block with the encrypted 2nd block to output the encrypted packet.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video recorder and a set top box.
The present invention relates to an encryption device used for encrypting content in a personal computer or the like for preventing unauthorized copying.

[0002]

2. Description of the Related Art Conventionally, Japanese Patent Laid-Open No. 9-2
The thing described in 30788 gazette is known.

FIG. 6 shows a block diagram of a conventional encryption device. In FIG. 6, reference numeral 61 denotes a seventh encryption means, 62 denotes an eighth encryption means, 63 denotes a ninth encryption means, and 641-
646 is an encryption circuit, 65 is a register, 66 is an exclusive OR operator, 67 is an encryption key, 68 is a plaintext input terminal, 69
Is a ciphertext output terminal. Hereinafter, a conventional encryption device will be described with reference to FIG.

[0004] The encryption circuits 641 to 646 encrypt unencrypted data (hereinafter, referred to as plaintext) based on the encryption key 67 and output encrypted data (hereinafter, referred to as encrypted text). . Generally, in order to increase the strength of encryption, many encryption circuits having the same configuration are connected in series. In FIG. 6, ma encryption circuits of the same configuration from X1 to Xma (ma is a natural number) and mb encryption circuits of the same configuration from Y1 to Ymb (mb are natural numbers) are connected in series. ing. In FIG. 6, X1 (encryption circuit 641), X2 (encryption circuit 642), Xma (encryption circuit 643), Y1 (encryption circuit 644), Y2 (encryption circuit 645), and Ymb (encryption circuit) Six circuits 646) are shown as examples. As an example of increasing the strength by connecting a large number of encryption circuits in this way, D.
ES (Data Encryption Standard) is known.

[0005] For example, 64-bit plaintext is input from a terminal 68, and block encryption is performed by encryption circuits 641 to 646. For example, MPEG2 (Moving Picture E
xperts Group 2) TSP (Transport Stream Packe)
t) (hereinafter simply referred to as TSP)
Since the SP has an 8-bit length, eight TSPs are collectively converted by a conversion circuit (not shown) into a 64-bit plaintext, and then input from a terminal 68.

In FIG. 6, the output of an eighth encrypting means 62 composed of encrypting circuits 641 to 643 is temporarily stored in a register 65, and when the next plaintext is inputted, an operator 66
To take the exclusive OR of the register 65 and the next plaintext. This is CBC (Cipher Block Chaining)
It is called a mode and is one method for making it difficult to decrypt cipher text.

For example, in the case of the TSP, the data is divided into sub-blocks every 64 bits from the beginning and input from a terminal 68. This sub-block is divided into a first sub-block, a second
If we call them sub-blocks and third sub-blocks,
First, block encryption of the first sub-block is performed by the eighth encryption unit 62, and the result is output to the ninth encryption unit 63 and stored in the register 65. Encryption circuit 644-
The ninth encryption means 63 constituted by 646 continuously performs block encryption of the first sub-block, and outputs the encrypted first sub-block from the terminal 69.

Next, the second sub-block input from the terminal 68 is subjected to an exclusive OR operation by the register 65 and the operator 66, and thereafter, is subjected to block encryption by the encryption circuits 641 to 643. This result is stored in the register 65 and used for block encryption of the next third sub-block. The ninth encryption unit 63 continues to perform block encryption, and outputs the encrypted second sub-block from the terminal 69.

By repeating the above processing until the end of the TSP, encryption for one packet can be performed. Since the ciphertext divided into sub-blocks is output from the terminal 69, the sub-block is inversely transformed into a TSP by an inverse transformation circuit (not shown), thereby obtaining an encrypted TSP.

[0010] As the CBC mode, a configuration as shown in FIG. 7 is also known. In FIG. 7, the register 65 and the encryption key 67
The result of exclusive ORing with the following is used as the next plaintext encryption key. In either of FIGS. 6 and 7, the next encryption is performed from the output of the eighth encryption means 62 and the input plaintext, and the result is further encrypted by the ninth encryption means. The ciphertext is output from 69.

FIG. 8 is a timing chart showing the operation of FIG. 6 or FIG. Input plaintext P10, P2
0, the ciphertexts C10 and C20 are output with a delay of the processing delay T0 of the seventh encryption unit 61. In the case of TSP, since one packet is 188 bytes, it is divided into 24 sub-blocks. Therefore, the processing delay TX for one packet is TX = 24 × T0.

The processing delay T0 of the seventh encryption means 61 is:
It is determined by the processing delay of each of the encryption circuits 641 to 646 and the total number of stages (ma + mb). These are both related to the strength of the encryption, and in order to keep the strength of the encryption above a certain level, the processing delay T0 cannot be made smaller than a certain delay. That is, the processing delay TX for one packet cannot be made shorter than a certain delay. Therefore, for a TSP with a high bit rate, it is necessary to prepare a plurality of seventh encryption means 61 and process them in parallel to reduce the apparent processing delay.

FIG. 9 shows a configuration in the case where processing is performed up to a TSP of about twice the bit rate. In FIG.
Is a tenth encryption means, 92 to 95 are buffers, 96 is a packet dividing means, and 97 is a packet combining means. Hereinafter, referring to FIG. 9, a TSP having an approximately double bit rate will be described.
The case of encryption will be described.

The tenth encryption means 91 has exactly the same configuration as the seventh encryption means 61 as shown in FIG. 10, and the CBC by the eleventh encryption means 92 and the twelfth encryption means 93. Mode, and performs block encryption of one packet. Note that when the seventh encryption means 61 has the CBC mode of FIG. 7, it also has the CBC mode of FIG.

The TSP input from the terminal 68 is divided by the packet dividing means 96 for each packet, and is alternately written to the buffer 92 and the buffer 93 for each packet. Here, the buffers 92 and 93 are, for example, FIFOs (First In First Out memory).

The TSP written in the buffer 92 is encrypted by the seventh encryption means 61 and written in the buffer 94. TSP similarly written in buffer 93
Is encrypted by the tenth encryption means 91 and the buffer 9
5 is written. Here, the buffer 94 and the buffer 9
5 is, for example, a FIFO.

FIG. 12 shows a timing chart at this time. Hereinafter, the operation of FIG. 9 will be described with reference to FIG.

The TSP P1 input from the terminal 68
00, P200, P300 and P400 are divided by the packet dividing means 96, and P100 and P300 are stored in the buffer 9
2, P200 and P400 are written to the buffer 93. The seventh encryption means 61 sequentially encrypts P100 and P300, and writes the resulting ciphertexts C100 and C300 in the buffer 94. Similarly, the tenth encryption means 91 sets P
200 and P400 are sequentially encrypted, and the resulting ciphertext C20
0 and C400 are written to the buffer 95.

The packet combining means 97 includes a buffer 94,
The ciphertext is alternately read from the buffer 95. Thereby, P100, P200, P3 input from the terminal 68
00, the result of encrypting P400 is C100, C200,
C300 and C400 are sequentially output from the terminal 69. Also, at this time, since the seventh encrypting means 61 and the tenth encrypting means 91 operate in parallel, the processing in FIG. 12 is performed up to a TSP having a bit rate about twice that of FIG. .

[0020]

However, in the above-mentioned conventional configuration, it is necessary to add a new FIFO in order to process a TSP of about twice the bit rate, which increases the circuit scale and the cost. There was a problem of inviting.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an encryption device capable of processing a TSP having a bit rate twice as high without adding a FIFO.

[0022]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a block dividing means for dividing input data into a first block and a second block and outputting the divided data, First encrypting means for encrypting the first block using second intermediate data and outputting first encrypted data and first intermediate data; and a second encrypting means for encrypting the first block and the first intermediate data. Second encryption means for encrypting the second block using data and outputting second encrypted data and the second intermediate data; and the first encrypted data and the second encrypted data. Block combining means for combining data and outputting encrypted data obtained by encrypting the input data.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a block dividing means,
The input data is divided into a first block and a second block. The first encrypting means uses the second intermediate data,
The first block is encrypted, and first encrypted data, which is a result of encrypting the first intermediate data and the first block, is output. The second encryption means encrypts the second block using the first intermediate data, and outputs second encrypted data which is a result of encrypting the second intermediate data and the second block. . The block combining unit combines the first encrypted data and the second encrypted data, and outputs encrypted data obtained by encrypting the input data.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an encryption apparatus according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 11 denotes a first encrypting unit, 12 denotes a second encrypting unit, 13 denotes a block dividing unit, 14 denotes a block combining unit, 15 denotes a plaintext input terminal, and 16 denotes a ciphertext output terminal. Hereinafter, the encryption device according to the present embodiment will be described with reference to FIG.

The block dividing means 13 divides the plain text input from the terminal 15 into two blocks. For example, when TSP is input from the terminal 15, first 64
.., And the first, third, fifth,..., Ie, odd-numbered sub-blocks are output to the first encryption unit 11 as the first blocks. . Similarly, the even-numbered sub-block from the head is output to the second encryption unit 12 as a second block. Block dividing means 13 performing such an operation
For example, a demultiplexer is used.

FIG. 2 shows a configuration example of the first encryption means 11 and the second encryption means 12. In FIG. 2, reference numeral 21 denotes third encryption means, 22 denotes fourth encryption means, and 23 denotes fifth encryption means.
24 is a sixth encryption means, 251-25
6 and 261 to 266 are encryption circuits; 27 and 28 are registers; 29 and 210 are exclusive OR operators;
212 is an encryption key. Hereinafter, the encryption operation of the first encryption unit 11 and the second encryption unit 12 will be described with reference to FIG.

The first encrypting means 11 encrypts the first block using the encryption key 211. First, when the first sub-block is input, the encryption circuits 251 to 25
In step 3, block encryption is performed, and the first intermediate data is output. As described in the section of the prior art, in order to increase the strength of encryption, encryption circuits 251 to 25 having the same configuration are used.
3 are connected in series in ma stages.

Each of the first encryption means 11 and the second encryption means 12 has a CBC mode, and calculates the exclusive OR of the input sub-block and the registers 27 and 28 with an operator 29, The configuration performed at 210 is adopted. In the CBC mode, as shown in FIG. 3, an exclusive OR of the registers 27 and 28 and the encryption keys 211 and 212 may be obtained.

The first first intermediate data is subsequently block-encrypted by the encryption circuits 254 to 256, output as an encrypted first sub-block, and output from the register of the second encryption means 12. 28. The encryption circuits 254 to 256 are composed of mb stages,
Ma + m as a whole together with the encryption circuits 251 to 253
An encryption circuit of b = m stages (m is a natural number) is configured.

Since the encryption of the second block is performed by the second encryption means 12, when the second sub-block is input, first, the first first intermediate data stored in the register 28 is stored. The exclusive OR of the second sub-block and the second sub-block is calculated by an operator 210. Next, the na stage (na
Are natural numbers) in the encryption circuits 261 to 263.
2 is performed, and the first second intermediate data is output.

The first second intermediate data continues to be n
Block encryption is performed by encryption circuits 264 to 266 of b stages (nb is a natural number), output as an encrypted second sub-block, and temporarily stored in the register 27 of the first encryption unit 11. Encryption circuits 254 to 25
6 and the encryption circuits 251 to 253 together constitute an encryption circuit of na + nb = n stages (n is a natural number).

Next, when the third sub-block is input, the exclusive OR with the first second intermediate data stored in the register 27 is obtained by the operator 29, and the encryption circuits 251 to 253 are obtained. , And the second first intermediate data is output. This is temporarily stored in the register 28, and is block-encrypted by the encryption circuits 254 to 256, and is output as an encrypted third sub-block.

By repeating the same operation, encrypted sub-blocks are output one after another. FIG. 4 shows a timing chart at this time. In FIG. 4, the processing delay of the third encryption unit is T3, and the processing delay of the fourth encryption unit is T3.
4. The processing delay of the fifth encryption unit is T5, the processing delay of the sixth encryption unit is T6, the processing delay of the first encryption unit is T1 (= T3 + T4), and the processing of the second encryption unit is The case where the delay is T2 (= T5 + T6) and T3 = T4 = T5 = T6 is shown. At this time, ma = mb = na = n
b, that is, m = n.

After the processing delay T3 of the third encryption means, the first first intermediate data is output. After the processing delay T4 of the fourth encryption means, the encrypted first sub-block is output. Is output. The encryption unit 12 starts the process with a delay of the processing delay T3 of the third encryption unit. That is, the processing is started after the first first intermediate data is output. After the processing delay T5 of the fifth encryption unit, the first second intermediate data is output, and after the processing delay T6 of the sixth encryption unit, the second encrypted sub-block is output. Is done.

Similarly, the first encryption means 11 and the second
And the encryption means 12 operate alternately for each sub-block,
The plaintext input from the terminal 15 is encrypted. The block combining unit 14 alternately outputs the ciphertext for each sub-block output by the first encrypting unit 11 and the second encrypting unit 12, thereby converting the plaintext ciphertext input from the terminal 15. , Terminal 16. For example, a multiplexer is used as the block combining unit 14 that performs such an operation.

FIG. 5 shows a timing chart when TSP is used as plain text. In FIG. 5, P1 to P4 are input TSPs, and C1 to C4 are encrypted TSPs. The encrypted TSPs C1 to C4 are input TSPs.
Is output with a delay of the encryption processing delay from P1 to P4. This processing delay is, as shown in FIGS. 4 and 5, T3 +
It becomes T5.

In the case of TSP, one packet is 188
Since it is a byte, one packet is divided into 24 sub-blocks. Therefore, the processing delay TA of the first encryption unit 11 is 12 × T1, and the processing delay T of the second encryption unit 12 is
B becomes 12 × T2. The processing delays TA and TB are equal to T
1 = T2, T3 = T4 = T5 = T6, the minimum, and the processing delay 24 when encrypted by the first encryption means 11 alone
It is possible to process up to T1 of × T1, or a bit rate that is about twice the processing delay of 24 × T2 when the encryption is performed by the second encryption means 12 alone.

In this embodiment, the case where the plaintext is TSP has been described as an example.
Encryption can be performed at a maximum processing speed of about twice.
T1 = T2, T3 = T4 =
Although the case where T5 = T6 has been described, even if this condition is not met, the processing speed can be improved, and this is effective for plaintext with a high bit rate.

[0040]

As described above, according to the present invention, the block dividing means for dividing the input data into the first block and the second block and outputting the divided data, and the first intermediate data using the second intermediate data.
A first encrypting means for encrypting the first block and outputting the first encrypted data and the first intermediate data; and encrypting the second block using the first intermediate data and the second encrypted data and the second encrypted data. A large-capacity memory by providing second encryption means for outputting intermediate data of No. 2 and block combining means for combining the first encrypted data and the second encrypted data and outputting the encrypted data. The processing speed of encryption can be easily improved without using, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encryption device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a first encryption unit and a second encryption unit according to the first embodiment;

FIG. 3 is a block diagram showing a configuration example of another CBC mode according to the first embodiment;

FIG. 4 is a signal waveform diagram illustrating operations of a first encryption unit and a second encryption unit according to the first embodiment.

FIG. 5 is a signal waveform diagram illustrating an operation of the encryption device according to the first embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional encryption device.

FIG. 7 is a block diagram showing a configuration example in another CBC mode in a conventional encryption device.

FIG. 8 is a signal waveform diagram for explaining the operation of a conventional encryption device.

FIG. 9 is a block diagram showing a configuration example when a conventional encryption device is operated at about twice the processing speed.

FIG. 10 is a block diagram showing a specific configuration example of a tenth encryption unit in a conventional encryption device.

FIG. 11 is a block diagram showing a specific configuration example in another CBC mode of a tenth encryption unit in a conventional encryption device.

FIG. 12 is a signal waveform diagram for explaining the operation when the conventional encryption device is operated at about twice the processing speed.

[Explanation of symbols]

 11 first encryption means 12 second encryption means 13 block dividing means 14 block combining means

Claims (5)

[Claims] 1. A block dividing means for dividing input data into a first block and a second block and outputting the divided data, and the first block using the first block and second intermediate data.
A first encryption unit for encrypting the first block and outputting first encrypted data and first intermediate data; and encrypting the second block using the second block and the first intermediate data. And second encryption means for outputting the second encrypted data and the second intermediate data, combining the first encrypted data and the second encrypted data, and encrypting the input data. And a block combining means for outputting encrypted data. 2. The first encryption unit encrypts a first block and outputs first intermediate data. The third encryption unit encrypts the first intermediate data and encrypts the first intermediate data. Fourth encryption means for outputting encrypted data, wherein the second encryption means encrypts the second block and outputs second intermediate data; 6. A sixth encrypting means for encrypting data and outputting the second encrypted data.
An encryption device as described. 3. The block dividing means converts input data into (m
+ N) (m and n are natural numbers) sub-blocks,
The odd-numbered m sub-blocks from the beginning are output as the first block, and the even-numbered n
Output the sub-blocks as a second block, the first encryption unit performs block encryption on the first block for each of the m sub-blocks, and the second encryption unit outputs the 3. The encryption apparatus according to claim 1, wherein two blocks are block-encrypted for each of the n sub-blocks. 4. The first encryption means outputs a j-th (j = 1, 2, 3,..., N) second j-th output from the second encryption means.
Ith of the first block (i = 1, i = 1
2, 3,..., M) block encryption of the sub-block and outputs the i-th first intermediate data and the i-th first encrypted data. The block encryption of the j-th sub-block of the second block is performed using the i-th first intermediate data, and the j-th second intermediate data and j
4. The encryption device according to claim 3, wherein the second encrypted data is output. 5. The first encrypting means outputs the i-th first intermediate data with a delay T, and outputs the i-th first encrypted data with a delay twice as long as the delay T. Outputs the j-th second intermediate data with the delay T and the j-th second encrypted data with a delay twice as long as the delay T, and outputs the first encryption means 5. The encryption device according to claim 4, wherein the encryption is performed with a delay of the delay T.