JPH0836892A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a non-volatile semiconductor memory capable of performing a test in which reliability for defective erasing or defective writing is high. CONSTITUTION:When a function of a status register 18 is tested, a test mode signal is outputted from a test mode circuit 8, and an erasing pulse counter 7 is operated. The erasing pulse counter 7 counts an erasing pulse outputted from a program/erasing voltage generating circuit 5 only one time, a counted value is outputted to the program/erasing voltage generating circuit 5. The program/erasing voltage generating circuit 5 outputs an erasing pulse to a memory cell in a memory cell array 15 only one time in accordance with a counted value of the erasing pulse counter 7, and a state of erasing error is caused. The status register 18 is tested by reading out data of the status register 18 in this state, a test for an erasing error is performed using the status register 18 operating normally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a test mode for testing an erase error or a write error.

[0002]

2. Description of the Related Art A flash memory, which is a conventional nonvolatile semiconductor memory device, will be described below. FIG. 10 is a block diagram showing a configuration of an erasing unit of a conventional nonvolatile semiconductor memory device.

Referring to FIG. 10, the erase unit includes an erase pulse generating circuit 101 and an erase pulse counter 102. When the erase command 103 is input to the erase pulse generation circuit 101, the erase pulse generation circuit 101 outputs an erase pulse to the memory cell 104. At this time, the erase pulse counter 1
02 counts the number of times the erase pulse is generated. The erase pulse generation circuit 101 generates an erase pulse until the count number of the erase pulse counter 102 reaches 5000 times.
The memory cell 104 performs an erase operation according to the input erase pulse.

Next, the writing section of the conventional nonvolatile semiconductor memory device will be described. FIG. 11 is a block diagram showing a configuration of a writing unit of a conventional nonvolatile semiconductor memory device.

Referring to FIG. 11, the writing unit includes a write pulse generating circuit 111 and a write pulse counter 112. Write pulse generation circuit 111 outputs a write pulse to memory cell 104 when write command 113 is input. At this time, the write pulse counter 112 simultaneously counts the number of write pulse outputs. Write pulse generation circuit 111
Generates a write pulse until the count value of the write pulse counter 112 reaches 25 times. The memory cell 104 performs a write operation by the input write pulse.

Next, the structure of the memory cell portion of the conventional nonvolatile semiconductor memory device will be described. FIG. 12 is a diagram showing a configuration of a memory cell portion of a conventional nonvolatile semiconductor memory device.

Referring to FIG. 12, the memory cell portion includes a sense amplifier 110 and NMOS transistors Q11 and Q1.
2, Q14, and a memory transistor Q13 serving as a memory cell of the flash memory. A high voltage V _PP higher than the power supply voltage is supplied to one end of the transistor Q14. The other end of transistor Q14 is connected to sense amplifier 110 and transistor Q11. Write signal WE is input to the gate of transistor Q14. Transistor Q1
1 and Q12 are connected in series, and select gate signals SG1 and SG2 are input to their respective gates. One end of the transistor Q12 is connected to the memory transistor Q13. The gate of memory transistor Q13 is connected to word line WL.

With the above structure, when the write signal WE is input at "H" and the transistor Q14 is turned on, the high voltage V _pp is applied to the memory cell portion as the high voltage V _PP.
2 to the memory transistor Q13. As a result, the data writing operation to the memory transistor Q13 is executed.

The nonvolatile semiconductor memory device configured as described above has a status register inside, and by reading the contents of the register, the internal operating state of the device or the occurrence of an erase error / write error occurs. Etc. can be known. This function is unique to the flash memory. Regarding the erase error / write error, for example, in an 8-input / output device, an erase error can be detected from the D5 pin (status register 5) and a write error can be detected from the D4 pin (status register 4). For example, when the data read from each pin is “0”, erasing or writing has succeeded,
When it is "1", an error has occurred, and there is a write failure or erase failure.

Next, an erase test method for the nonvolatile semiconductor memory device configured as described above will be described. FIG. 13 is a flowchart for explaining a conventional erase test method for a nonvolatile semiconductor memory device.

First, in step S101, an erase command "30H" is input. Next, step S10
In 2, the erase command “30H” is input again. Erasing is performed by inputting the command twice, and the erasing operation is automatically performed inside the device. The data of the above command may differ depending on the product.

Next, in step S103, it is confirmed whether or not the internal operation is in the ready state. If the internal operation is not in the ready state, step S103 is repeated, and if it is in the ready state, the process proceeds to step S104.

After the internal operation becomes ready, the data in the status register 5 is read in step S104. Next, in step S104, it is confirmed whether or not the data in the status register 5 is "0". When it is "0", the erase operation is successful, and "1"
At this time, it can be seen that the erasing has not been completely performed and an erasing failure has occurred.

Next, the operation inside the device corresponding to the above erase test method will be described. FIG. 14 is a flowchart for explaining the internal operation of the conventional nonvolatile semiconductor memory device during the erase test.

First, in step S111, data "0" is written in all memory cells. Next, in step S112, the address is set to address 0. Next, in step S113, the count value X is set to "0".

Next, in step S114, the count value X is incremented. Next, step S11
At 5, an erase pulse is applied to the memory cell. Next, in step S116, the count value X is 500.
Check if it is 0 times. Count value X is 5
If it is 000 times, the process proceeds to step S121, and if it is not 5,000 times, step S117.
Move to.

Next, in step S117, a verify operation is executed. If the verify result is fail, the process proceeds to step S114, and if the verify result is pass, the process proceeds to step S114.
Transition to 118. If the verification result is "pass", in step S118, it is confirmed whether or not the address has reached the final address. If it has not reached the final address, the process proceeds to step S121, and if it has reached the final address, the process proceeds to step S119.

If the final address has not been reached, the address is incremented in step S121 and the process proceeds to step S117 to continue the subsequent processing. On the other hand, if the final address has been reached, the path latch is performed in step S119, and the data of "0" is stored in the status register 5. Next, step S120.
In, the internal operation becomes ready.

On the other hand, in step S116, if the count value X has reached 5000 times, step S122
At, the verify operation is performed. If the verify result is pass, the process proceeds to step S118, and if the verify result is fail, the process proceeds to step S123. If the verify result is fail, fail latch is performed in step S123, and "1" data is stored in the status register 5. Next, in step S124,
Makes internal operation ready.

By the above operation, the erase operation from the address 0 to the final address is executed, and the internal operation becomes ready. Next, read the contents of the status register,
If the data in the status register 5 is "0", the erasing operation has succeeded, and if the data is "1", the erasing operation has not been performed completely, which indicates that the erasing is defective.

Next, the method of the conventional nonvolatile semiconductor memory device write test will be described. FIG. 15 is a flowchart for explaining a conventional write test method for a nonvolatile semiconductor memory device.

Referring to FIG. 15, first, step S13
In 1, the command “10H” is input. next,
In step S132, the write address and data are input. By the above operation, the write operation is automatically performed inside the device.

Next, in step S133, it is confirmed whether or not the internal operation is in the ready state. If it is not in the ready state, step S133 is repeated, and if it is in the ready state, the process proceeds to step S134. Next, in step S134, the data in the status register 4 is read. Next, step S
At 135, it is confirmed whether the data in the status register 4 is "0". Status register 4
If the data is "0", the programming (writing) is completed, and if it is not "0", the program is defective.

Next, the operation inside the nonvolatile semiconductor memory device according to the above write test method will be described. FIG.
FIG. 6 is a flow chart for explaining the internal operation of the conventional nonvolatile semiconductor memory device during the write test.

Referring to FIG. 16, first, step S141
At, the count value X is set to "0". Next, in step 142, the count value X is incremented. Next, in step S143, a write pulse is applied to the memory cell. Next, step S1
At 44, it is confirmed whether or not the count value X is 25 times. If not 25 times, step S
If it is 25 times, go to step 145 and step S
Transition to 148.

If the count value X is not 25, the verify operation is performed in step S145. If the verify result is fail, step S14
2, the process proceeds to step S146 if it is a pass. Next, if the verify result is pass, step S14
In 6, the status register 4 is pass-latched and the status register 4 stores "0" data. Next, in step S147, the internal operation is set to the ready state.

On the other hand, if the count value X is 25 times in step S144, the verify operation is performed in step S148. If the verify result is pass, the process proceeds to step S146, and if the verify result is fail, the process proceeds to step S149. If the verify result is fail, fail latch is performed in the status register 4 in step S149, and "1" data is stored in the status register 4. Next, in step S150, the internal operation is set to the ready state.

By the above operation, after the internal operation becomes the ready state, the status register is read, and when the data of the status register 4 is "0", the writing operation is successful, and when it is "1", the writing operation is successful. It can be seen that the operation has failed and writing has failed.

[0029]

As described above, in the conventional nonvolatile semiconductor memory device, during the erase or write operation,
The status register 2 is fail latched (data “1”) only when the device really becomes defective, and it is not possible to inspect whether or not the function of the status register is operating properly in a non-defective device. It was In other words, you can check for errors in the erase or write operation, but you cannot check the status register itself. If the status register itself is defective, you can check whether each test result is really correct. However, there was a problem that reliability was poor.

An object of the present invention is to solve the above problems, and an object thereof is to provide a non-volatile semiconductor memory device capable of performing a highly reliable test for an erase failure or a write failure.

[0031]

A non-volatile semiconductor memory device according to claim 1 is a non-volatile semiconductor memory device having a test mode for testing an erase error, wherein the non-volatile semiconductor memory device responds to a control signal input from the outside. An erasing error occurrence signal output means for outputting an erasing error occurrence signal and an erasing error occurrence means for producing an erasing error state according to the erasing error occurrence signal are included.

According to a second aspect of the present invention, in addition to the configuration of the non-volatile semiconductor memory device according to the first aspect, the non-volatile semiconductor memory device includes a plurality of non-volatile memory cells, and the erasing error occurs. The generating means includes an erase pulse output means for outputting an erase pulse only once to the plurality of memory cells in response to the erase error generating signal.

According to a third aspect of the present invention, in addition to the configuration of the non-volatile semiconductor memory device according to the second aspect, the erase pulse generating means operates in response to an erase error generation signal to generate an erase pulse. It includes a counting unit that counts only once and an output unit that outputs an erase pulse according to the count number of the counting unit.

A nonvolatile semiconductor memory device according to a fourth aspect is a semiconductor memory device having a test mode for testing a write error, and outputs a write error occurrence signal according to a control signal input from the outside. It includes an output means and a write error generating means for generating a write error state according to the write error generating signal.

According to a fifth aspect of the present invention, in addition to the configuration of the non-volatile semiconductor memory device according to the fourth aspect, the non-volatile semiconductor memory device includes a plurality of non-volatile memory cells. The write error generating means includes stop means for stopping the application of the write pulse to the plurality of memory cells according to the write error generating signal.

[0036]

In the nonvolatile semiconductor memory device according to any one of claims 1 to 3, since the erase error state can be created by the erase error generating means, the erase error state is intentionally generated, and the status register at that time is generated. The function of the status register can be inspected by checking the data of.

In the non-volatile semiconductor memory device according to the fourth and fifth aspects, since the write error state can be created by the write error generating means, the write error state is intentionally generated. The status register can be inspected by checking the data in the status register.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flash memory which is a nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, the nonvolatile semiconductor memory device includes a control circuit 1, a command register 2, a command decoder 3, a verify voltage generating circuit 4, a program / erase voltage generating circuit 5, erase pulse counters 6, 7, Test mode circuit 8, write circuit 9, sense amplifier 10, address register 11, Y decoder 12, X decoder 13, Y gate 14, memory cell array 15, source line switch 1
6, an input / output buffer 17 and a status register 18.

The control circuit 1 has a write enable signal /
WE, chip enable signal / CE, and output enable signal / OE are input to control the operation of the entire device. The command register 2 latches the data input from the input / output buffer 17. The command decoder 3 sets the internal operation according to the data stored in the command register 2. The verify voltage generating circuit 4 and the program / erase voltage generating circuit 5 have a verify voltage different from the power supply voltage V _CC during writing or erasing,
Generates program voltage and erase voltage. The erase pulse counter 6 counts the count value of the erase pulse applied to the memory cell during normal operation and sets a limit value (for example, 3000 times). The test mode circuit 8 receives a test mode command signal from the command decoder 3 and outputs a test mode signal, which is an erase error generation signal for generating an erase error, to the erase pulse counter 7. The erase pulse counter 7 operates according to the test mode signal and counts the erase pulse during erase only once. The writing circuit 9 supplies a predetermined voltage to the memory cell array 15 during writing. The sense amplifier 10 amplifies the data of a predetermined memory cell in the memory cell array 15 and outputs it to the input / output buffer 17.

The address signal A is sent to the address register 11.
Is input, the address signal A is latched, the Y address signal is output to the Y decoder 12, and the X address signal is output to the X decoder 13. The Y decoder 12 is a decoder for selecting a select gate, and selects a predetermined gate in the Y gate 14 according to the input Y address signal. The X decoder 13 activates a predetermined word line in the memory cell array 15 according to the input X address signal. A plurality of memory cells are arranged in the memory cell array 15, and a predetermined memory cell is selected by the X decoder 13 and the Y decoder 14. Source line switch 16
Applies a predetermined voltage to a predetermined memory cell in the memory cell array 15 at the time of erasing. Input / output data DQ is input or output to / from the input / output buffer 17, and external data is taken in or internal data is output. The power supply voltage V _CC and the ground voltage V _SS are supplied to each circuit,
Further, the command decoder 3, the verify voltage generation circuit 4, the program / erase voltage generation circuit 5, the write circuit 9, and the source line switch 16 are supplied with a high voltage V _PP obtained by further boosting the power supply voltage V _CC .

Next, the erase section of the nonvolatile semiconductor memory device shown in FIG. 1 will be described. FIG. 2 is a block diagram showing the configuration of the erasing unit of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 2, the erase portion of the nonvolatile semiconductor memory device includes an erase pulse generating circuit 5a, erase pulse counters 6a and 7a, and a test mode circuit 8. The erase pulse generating circuit 5a is provided inside the program / erase voltage generating circuit 5 shown in FIG. 1 and outputs an erase pulse to the memory cells in the memory cell array 15a in response to the input erase command 20. The erase pulse counter 6a is provided in the erase pulse counter 6 shown in FIG. 1, counts the number of times the erase pulse is generated during normal operation, and the count value X is 300.
It counts up to 0 times and outputs the count result to the erase pulse generating circuit 5a. The erase pulse counter 7a is
The erase pulse counter 7 shown in FIG. 1 is provided, operates according to a test mode signal output from the test mode circuit 8, and counts the number of erase pulses only once when the function of the status register 18 is checked. To the erase pulse generation circuit 5a.

With the above configuration, the erase pulse generating circuit 5
In the case of normal erase failure check, the erase pulse is counted by the erase pulse counter 6a, and the erase pulse is generated from the erase pulse generating circuit 5a until the count value X reaches 3000 times. On the other hand, when checking the function of the status register 18, the erase pulse counter 7a operates in response to the test mode signal which is the erase error occurrence signal, and the erase pulse counter 7a outputs 1 erase pulse.
Only once, the erase pulse generation circuit 5a outputs the erase pulse to the memory cell only once.

Next, a method of inspecting the function of the status register at the time of an erase test using the nonvolatile semiconductor memory device configured as described above will be described. FIG. 3 is a flow chart for explaining a method of inspecting the status register during the erase test of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 3, first, in step S1, the test mode is set. The function check of the status register should be performed in this test mode. The test mode is set by, for example, setting a predetermined pin to a high voltage or inputting a command out of product specifications. Next, in steps S2 and S3, the erase command "30H" is input twice. next,
In step S4, it is confirmed whether or not the internal operation is in the ready state. If it is not ready, step S4 is repeated, and if it is ready, the process proceeds to step S5. Next, in step S5, the contents of the status register 5 are read. Next, in step S6, it is confirmed whether or not the data in the status register 5 is "1". When the data in the status register 5 is "1", the device is non-defective, and when the data is "0", the function of the status register is not functioning normally and the device is defective.

Next, the internal operation at the time of checking the status register in the erase test will be described. FIG.
3 is a flowchart for explaining an internal operation at the time of checking a status register in an erase test of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 4, first, in step S11, "0" is written in all memory cells. Next, in step S12, the address is set to address 0. Next, in step S13, an erase pulse is applied to the memory cell. Next, in step S14, the verify operation of the memory cell to which the erase pulse is applied is performed. Next, in step S15, fail latch is performed in the status register 5 and the data of "1" is stored. Next, in step S16, the internal operation becomes ready. In the above-mentioned operation, the erase pulse counter 7a operates by setting the test mode, that is, by externally setting a predetermined pin to a high voltage and outputting the test mode signal from the test mode circuit 8,
The erase pulse is counted only once, and the erase pulse is applied only once from the erase pulse generating circuit 5a to the memory cell. Normally, one erase pulse does not completely erase, and the erase verify result always fails. Therefore, it can be seen that when the data in the status register 5 is "1", the device is a good product, and when the data is "0", the function of the status register is not operating normally and the device is defective.

As described above, in the first embodiment, the function of the status register is checked by applying the erase pulse only once during the erase test, so that an erase error state can be intentionally created. , It becomes possible to check the function of the status register. As a result, a highly reliable test for erasing defects can be performed.

Next, the writing section of the non-volatile semiconductor memory device shown in FIG. 1 will be described. FIG. 5 is a block diagram showing a configuration of a writing unit of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 5, the writing unit includes a write pulse generating circuit 5b, write pulse counters 6b and 7b, and a test mode circuit 8. The write pulse generating circuit 5b is provided inside the program / erase voltage generating circuit 5 shown in FIG.
A write pulse is output to memory cell 15b in response to write command 21. The write pulse counter 6b is used in normal operation, counts the number of write pulses output from the write pulse generation circuit 5b up to 25 times, and outputs the count result to the write pulse generation circuit 5b. The write pulse counter 7b operates according to the test mode signal output from the test mode circuit 8, and when checking the function of the status register, counts the write pulse only once and generates the count result as the write pulse. Output to the circuit 5b.

With the above configuration, the write pulse counter 6b counts the write pulse up to 25 times in the normal write test, and the write pulse counter 7b outputs 1 when the function of the status register is checked.
The write pulse is counted only once, and the write pulse is output only once.

Next, a method of inspecting the status register during the write test of the nonvolatile semiconductor memory device shown in FIG. 1 will be described. FIG. 6 is a flow chart for explaining a method of inspecting the status register during the write test of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 6, first, in step S21, a test mode is set. The function check of the status register is performed in the test mode. The test mode is set in the same way as the function check of the status register during the erase test.

Next, in step S22, the write command "10H" is input. Next, in step S23, the address is set to the address 0 and "0" is set as the data.
Enter Next, in step S24, if the internal operation is not in the ready state, step S24 is repeated, and if it is in the ready state, step S25.
Move to. Next, in step S25, the data in the status register 4 is read. Next, step S
26, the data of the status register 4 is “1”
Check whether or not. If the status register is 1, the status register is operating normally, and the device is a good product. If the status register is 0, the status register is not operating normally and the device is defective. I know there is.

Next, the internal operation during the above inspection will be described. FIG. 7 is a flow chart for explaining the internal operation at the time of checking the status register in the write test of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 7, first, in step S31, since the test mode is set, write pulse counter 7b operates and the write pulse is applied to the memory cell only once. Then, in step S32, a verify operation is performed. Next, in step S33, fail latch is performed in the status register 4 and "1" is stored as the data in the status register 4. Next, in step S34, the internal operation is set to the ready state.

By the above operation, the write pulse generating circuit 5
Since b outputs a write pulse to the memory cell only once, if writing cannot be performed sufficiently by writing once, a write error occurs and the status register 4 stores "1" data. Therefore, when the data in the status register 4 is "0", it is understood that the status register is not operating normally, and the function of the status register can be inspected. As a result, it is possible to carry out a highly reliable test for writing defects.

In the above embodiment, the write error state was intentionally created by applying the write pulse only once, but the normal write operation can be performed by only one write pulse. There is. Therefore, when writing is completed by applying the write pulse only once, the function of the status register may not be checked. Therefore, a non-volatile semiconductor memory device that can more completely create a defective write state will be described below. FIG. 8 is a block diagram showing the configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

The nonvolatile semiconductor memory device shown in FIG. 8 and FIG.
The non-volatile semiconductor memory device shown in FIG. 6 is different in that write circuit 9 performs a write operation according to test mode signal TE output from test mode circuit 8 and write signal WE output from control circuit 1. Is. Since the other points are similar to those of the nonvolatile semiconductor memory device shown in FIG. 1, the same parts are designated by the same reference numerals, and the description thereof will be omitted below.

Next, the memory cell portion of the second embodiment will be described in more detail. FIG. 9 is a diagram showing a configuration of a memory cell portion of the nonvolatile semiconductor memory device shown in FIG.

Referring to FIG. 9, the memory cell portion includes a sense amplifier 10, NMOS transistors Q4, Q1, Q2,
It includes a NOR gate 1, an inverter G2, and a memory transistor Q3.

Inverter G2, NOR gate G1 and transistor Q4 are provided inside write circuit 9 shown in FIG. The write signal WE is input to the inverter G2, and its output is input to the NOR gate G1. A test mode signal TE is further input to the NOR gate G1. The NOR gate G1 outputs the NOR of the two input signals to the gate of the transistor Q4. Transistor Q4 has one end connected to high voltage V _PP and the other end connected to sense amplifier 10 and transistor Q1. The transistors Q1 and Q2 are provided inside the Y gate 14 and are connected in series. Select gate signals SG1 and SG are applied to the gates of the transistors Q1 and Q2, respectively.
2 is input. Transistor Q2 is connected to memory transistor Q3, and the gate of memory transistor Q3 is connected to word line WL.

Next, the operation of the writing section configured as described above will be described. During normal operation, test mode signal T
E is "L", and when the write signal WE becomes "H", the transistor Q4 turns on and the memory transistor Q
Writing to 3 is performed. Since the test mode signal TE becomes "H" during the inspection of the status register of the second embodiment, the transistor Q4 is not turned on even when the write signal WE becomes "H" or "L". Therefore, the transistor Q4 is not always turned on even when the data of "0" is input from the outside, so that the memory transistor Q3
Is not written to. As described above, since the test mode signal TE is input as the write error generation signal for generating the write error and the write operation to the memory transistor Q3 is controlled by the level of the test mode signal TE, the pseudo operation is performed. It is possible to cause defective writing.

As described above, it is possible to check the function of the status register by creating a pseudo write error state and reading the data of the status register 4 according to the flow charts shown in FIGS. That is, in the above write error state, the data in the status register 4 is the fail latch (data “1”).
If the data in the status register 4 is “1”, it means that the status register is operating normally and the device is a good product.
When it is "0", the status register is not operating normally, and it can be seen that the device is a defective device.

As described above, in the second embodiment, since the write error state can be surely generated, the function of the status register can be completely confirmed, and the reliability against the write failure is higher. It becomes possible to carry out a test.

In each of the above embodiments, the flash memory has been described, but the present invention can be similarly applied to other nonvolatile semiconductor memory devices.

[0068]

In the non-volatile semiconductor memory device according to the first to third aspects, since the erase error state can be created by the erase error generating means, it becomes possible to perform a function test of the status register and erase. It becomes possible to perform a reliable test for an error.

In the non-volatile semiconductor memory device according to the fourth and fifth aspects, since the write error state can be created by the write error generating means, the function check of the status register can be performed and the write operation can be performed. It becomes possible to perform a reliable test for an error.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an erasing section of the nonvolatile semiconductor memory device shown in FIG.

FIG. 3 is a flowchart for explaining a method of checking a status register during an erase test of the nonvolatile semiconductor memory device shown in FIG.

4 is a flow chart for explaining an internal operation at the time of checking a status register in an erase test of the nonvolatile semiconductor memory device shown in FIG.

5 is a block diagram showing a configuration of a writing unit of the nonvolatile semiconductor memory device shown in FIG.

6 is a flowchart for explaining a method of checking a status register during a write test of the nonvolatile semiconductor memory device shown in FIG.

7 is a flowchart for explaining an internal operation at the time of checking the status register in the write test of the nonvolatile semiconductor memory device shown in FIG.

FIG. 8 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

9 is a diagram showing a configuration of a memory cell portion of the nonvolatile semiconductor memory device shown in FIG.

FIG. 10 is a block diagram showing a configuration of an erasing section of a conventional nonvolatile semiconductor memory device.

FIG. 11 is a block diagram showing a configuration of a writing unit of a conventional nonvolatile semiconductor memory device.

FIG. 12 is a diagram showing a configuration of a memory cell portion of a conventional nonvolatile semiconductor memory device.

FIG. 13 is a flowchart for explaining a conventional erase test method for a nonvolatile semiconductor memory device.

FIG. 14 is a flowchart for explaining an internal operation during an erase test of a conventional nonvolatile semiconductor memory device.

FIG. 15 is a flow chart for explaining a conventional write test method for a nonvolatile semiconductor memory device.

FIG. 16 is a flowchart illustrating an internal operation of a conventional nonvolatile semiconductor memory device during a write test.

[Explanation of symbols]

1 control circuit, 2 command register, 3 command decoder, 4 verify voltage generation circuit, 5 program / erase voltage generation circuit, 6, 7 erase pulse counter, 8
Test mode circuit, 9 write circuit, 10 sense amplifier, 11 address register, 12 Y decoder, 13
X decoder, 14 Y gate, 15 memory cell array, 16 source line switch, 17 input / output buffer,
18 Status register.

Claims (5)

[Claims] 1. A non-volatile semiconductor memory device having a test mode for testing an erase error, comprising: output means for outputting an erase error occurrence signal in response to a control signal input from the outside; and the erase error occurrence signal. A non-volatile semiconductor memory device including an erasing error generating means for generating an erasing error state according to the above. 2. The non-volatile semiconductor memory device includes a plurality of non-volatile memory cells, and the erase error generating means applies an erase pulse only once to the plurality of memory cells in response to the erase error generating signal. The nonvolatile semiconductor memory device according to claim 1, further comprising an erase pulse output means for outputting. 3. The erasing pulse generating means operates in response to the erasing error generating signal and counts the erasing pulse only once, and the erasing pulse is generated in accordance with the count number of the counting means. The non-volatile semiconductor memory device according to claim 2, further comprising output means for outputting. 4. A semiconductor memory device having a test mode for testing a write error, comprising: output means for outputting a write error occurrence signal in response to a control signal input from the outside; and the write error occurrence. A non-volatile semiconductor memory device including a write error generating means for generating a write error state according to a signal. 5. The non-volatile semiconductor memory device includes a plurality of non-volatile memory cells, and the write error generation means generates a write pulse for a plurality of memory cells according to the write error generation signal. The non-volatile semiconductor memory device according to claim 4, further comprising stop means for stopping the application.