JPH0836553A - Multiprocessor system and task scheduling method therein - Google Patents

Abstract

PURPOSE:To perform an optimum task scheduling in the case where a task that is being executed by a CPU on the multiprocessor system, changes the states of other tasks. CONSTITUTION:When the task 11A that is being executed by the CPU 10-0 changes the states of the tasks indicated by task control blocks 61E and 61F in a 'wait' task group 60 and a connection with a task ready queue 50 is made, a CPU, which should perform task switching has its order determined in the increasing order of the execution priority of the task being executed by the CPU on the basis of CPU numbers and the priority of the in-execution task recorded in blocks 42 to 44 connected to the queue 40, and a specific interruption is generated to the determined CPU at each time to switch the task to be executed by the interrupted CPU to the task indicated by the head task control block connected to the queue 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system and a task scheduling method in the system.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system in which a plurality of CPUs (processors) operate in parallel, when task scheduling becomes necessary due to the operation of a task being executed by a certain CPU in the system, the CPU is interrupted. Occurred, and only the task to be executed on its own CPU was determined.

For example, when a task being executed on the CPU changes another task from the "waiting" state to the "executable" state, it is necessary to perform task scheduling. At this time, an interrupt is generated in the own CPU, and the task to be executed next on the own CPU as interrupt processing is determined as follows. That is, the priority (execution priority) of the task being executed (self task) and the queue in which the executable tasks (including the task that has been placed in the “executable” state immediately before) are connected in order of priority (hereinafter, task ready queue). (Referred to as), the one with the highest priority is compared, and the one with the higher priority is determined as the task to be executed next. Then, the determined task is executed by the own CPU.

[0004]

As described above, in conventional task scheduling in a multiprocessor system, when task scheduling processing is required during task execution in a certain CPU, an interrupt is generated in the own CPU, The CPU itself determines the next task to be executed based on the task being executed and the task group (the highest priority task among them) connected to the task ready queue.

As described above, conventionally, a task being executed on a certain CPU is "executable" from the "waiting" state for another task.
Only the CPU itself, the executing task (invoking task), and the task group in the task ready queue can be handled by the task scheduling processing required when the state is set.

However, in a multiprocessor system, there are also other CPU groups and tasks being executed there. Therefore, the present inventor has come to recognize that the optimum CPU allocation cannot be performed without considering these in the task scheduling.

For example, a task with a priority of 1 being executed on a certain CPU (the smaller the numerical value, the higher the priority).
However, it is assumed that another task having a priority of 2 is changed from the “waiting” state to the “executable” state.

In the task scheduling process following this process, the currently executing task has a higher priority.
The newly executable task whose priority is 2 remains in the CPU allocation wait state.

Further, even if the priority of a task being executed by another CPU is extremely low, such as 100, the task to be executed next is determined only by the priority relationship with the task being executed by the own CPU. Therefore, the task with the priority of 2 remains in the CPU allocation wait state.

Further, when the task being executed by the own CPU (assuming that the priority is 2) changes, for example, three tasks having the priority 1 to the "executable" state, the CPU is assigned by the task scheduling. Only one of them is executed, and the remaining tasks wait for CPU allocation even if they have a higher priority than tasks running on other CPUs.

As described above, conventionally, when a task scheduling process is required during execution of a task by a certain CPU on a multiprocessor system, that CPU (own CP
In U), since the task to be executed next is determined only by the priority (execution priority) relationship between the task being executed and the task group in the task ready queue, there is a problem that optimal scheduling cannot be performed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a CPU on a multiprocessor system.
If task scheduling processing is required during task execution in C, in addition to the priority of the task under execution and the priority of the task group in the CPU allocation waiting state, other C
In a multiprocessor system and in the same system, optimal task scheduling that makes use of a multiprocessor configuration can be performed by determining all CPUs that should execute task switching in consideration of the priority of tasks being executed in PU. It is to provide a task scheduling method.

[0013]

The configuration according to the first aspect of the present invention is a result task in which a task being executed by a certain CPU on a multiprocessor system changes the state of at least one other task. When the scheduling process becomes necessary, the tasks in the CPU allocation waiting state at that time are displayed in the order of the priority of the task in the multiprocessor system which is executing the tasks of the execution priority lower than the task. It is characterized in that tasks having lower execution priorities are assigned to CPUs in order from the CPU being executed.

In the above configuration, when a task being executed by a certain CPU changes the state of at least one other task from, for example, "waiting" to "executable", the priority of the task being executed is In addition to the priority of the task group that is in the CPU allocation waiting state at that time, the priority of the task that is being executed by another CPU is also considered. The highest priority task is CP on the system
The lowest priority task of U is assigned to the executing CPU. However, this is limited to the case where the priority of the task to be assigned is higher than the priority of the task being executed (in the CPU that is the assignment destination). Next, the task with the second highest priority in the task group in the CPU allocation waiting state at the time of changing the task state is C on the system.
CP that is executing the task with the second lowest priority among PUs
Assigned to U.

Similarly, in the above-mentioned task allocation, the priority of the task being executed by the CPU to which the task is scheduled to be assigned is higher than the priority of the task to be assigned, or the task is assigned. The process is repeated until at least one of the target task and the CPU of the allocation destination is exhausted.

In this way, when a task being executed by a certain CPU changes the state of another task, all the CPUs in the multiprocessor system including that CPU are
If there is a CPU that is executing a task with a lower priority than the task in the CPU allocation wait state, those CPUs are in the CPU allocation wait state in order from the CPU that is executing the task with a lower execution priority. Since each task is assigned in descending order of priority of the task, optimal task scheduling that makes the most of the multiprocessor configuration is possible.

In the configuration according to the second aspect of the present invention, for the above-mentioned task allocation, a specific interrupt which is a signal for performing the task switching process is generated for the corresponding CPU, and the CPU which has received this interrupt The task switching is performed according to the interrupt.

In the above configuration, when a specific interrupt is issued to the CPU to which the task is assigned, the C
The task in the CPU interrupt waiting state, which has a higher priority than the task being executed by the PU, is assigned immediately after the state change of the task.

[0019]

1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. The multiprocessor system shown in FIG. 1 has a plurality of CPs operating in parallel.
U, for example, three CPUs 10-0 to 10-2 and each of these Cs
Shared memory 20 shared by PUs 10-0 to 10-2
And a system bus 30 interconnecting the CPUs 10-0 to 10-2 and the shared memory 20. CPU1
0-0 to 10-2 have CPU numbers # 0 as CPU identifiers.
~ # 2 is assigned.

In the example of FIG. 1, the CPU 10-0 executes the task 11
A is executed, CPU 10-1 executes task 11B, and C
It is shown that the PU 10-2 is executing the task 11C. It is assumed that the task 11A has a priority (execution priority) of 1, the task 11B has a priority of 5, and the task 11C has a priority of 4.

In the shared memory 20, a CPU executing task priority data queue 40, a task ready queue 50 and a “waiting” task group 60 are placed. The CPU executing task priority data queue 40 has CPUs 10-0 to 10-10.
-2 is a data structure that manages the priority of the task being executed, and data that records the execution priority of each CPU number and the task being executed (hereinafter referred to as the CPU executing task priority data block) is given priority. This is for connecting in ascending order (here, the higher the numerical value, the lower the priority).

CPU executing task priority data queue 4
0 has a queue entry 41 pointing to (the position of) the CPU priority task priority data block at the head. In the example of FIG. 1, the CPU pointed to by the queue entry 41 in the CPU executing task priority data queue 40.
Three Cs including the executing task priority data block 42
PU executing task priority data blocks 42 to 44 are connected.

In the CPU executing task priority data block 42, the CPU number # 1 of the CPU 10-1 and the CPU 10 # 1 are stored.
At -1, the priority 5 of the task 11B being executed is recorded. In addition, the CPU executing task priority data block 4
3 includes CPU number # 2 of CPU 10-2 and CPU 10-2.
The priority 4 of the task 11C being executed is recorded in
The CPU 1 is included in the executing task priority data block 44.
The CPU number # 0 of 0-0 and the priority 1 of the task 11A being executed by the CPU 10-0 are recorded.

Each CPU executing task priority data block 42-44 indicates a queue field 400 indicating (position of) the next CPU executing task priority data block.
have. When the next priority data block does not exist, the cue field 400 is set with specific data (for example, all “0” data) indicating that. In the example of FIG. 1, the queue field 400 of the CPU executing task priority data block 42 indicates the next CPU executing task priority data block 43, and the queue field 400 of the data block 43 executes the next CPU execution. A medium task priority data block 44 is indicated.

The task ready queue 50 is for connecting the task control blocks of tasks in the "executable" state and waiting for CPU allocation in order of priority (highest priority). Task ready cue 50
Has a queue entry 51 pointing to (position of) the head task control block. In the example of FIG. 1, there is no task control block connected to the task ready queue 50.

The "waiting" task group 60 is composed of task control blocks of tasks in the "waiting" state (tasks not in the ready state). In the example of FIG. 1, the “waiting” task group 6
0 consists of three task control blocks 61D to 61F. The task control blocks 61D to 61F include task IDs that are identifiers thereof, status information indicating whether the task is in the "executable" state (ready state) or the "waiting" state (wait state), and Execution environment,
It has information such as the execution priority of the task. As shown in FIG. 1, the priority levels of the tasks indicated by the task control blocks 61D, 61E, and 61F are 6, 2, and 3, respectively.
Shall be

Next, task scheduling processing in the multiprocessor system of FIG. 1 will be described.
First, the task 11A running on the CPU 10-0 (CPU number is # 0) "executes the task in the" waiting "state indicated by the task control blocks 61E and 61F included in the" waiting "task group 60. It has been changed to the state. That is, the state information of the task control blocks 61E and 61F is changed from the "waiting" state to the "executable" state.

In this case, the task control blocks 61E, 6
1F (the task indicated by) waits for CPU allocation, and C
It is connected to the task ready queue 50 by PU10-0 (task 11A being executed by PU10-0). Here, the priority of the task control block 61E (task thereof) is 2 and the priority of the task control block 61F (task thereof) is 3, so that as shown in FIG. Blocks 61F are connected in this order. Here, the task control block 61E on the task ready queue 50 is pointed to by the queue entry 51. The task control block 61E includes a queue field 50.
0 is set, and the field 500 indicates the next task control block 61F.

Now, the task 1 being executed by the CPU 10-0 (
1A) assigns CPUs to the tasks indicated by the task control blocks 61E and 61F, so processing for selecting a CPU that executes task switching (task switching execution C
The PU selection process) is performed as follows according to the flowchart of FIG.

First, the CPU 10-0 (task 11 being executed by
A) refers to the head CPU in-execution task priority data block connected to the CPU-in-execution task priority data queue 40, and starts CP from the priority data block.
The U number and the priority are extracted (step S1).

Next, the task 11 being executed by the CPU 10-0 (
A) refers to the head task control block connected to the task ready queue 50, and extracts the priority of the corresponding task from the block (step S2).

Then, the task 1 being executed by the CPU 10-0 (
1A) compares the two priorities extracted in steps S1 and S2 (step S3). In step S3 for the first time, the priority recorded in the first CPU executing task priority data block of the CPU executing task priority data queue 40 and the first priority data block of the task ready queue 50 are recorded. The priority is compared.

If the CPU extracted in step S1
The priority of the task being executed in any of 10-0 to 10-2 (CPU executing task) is the "executable" state task (that is, CPU allocation) on the task ready queue 50 side extracted in step S2. If the priority is higher than the (waiting task), CPU 10-0 (task 11A being executed)
Determines that the task switching is useless, and ends the task switching execution CPU selection processing without doing anything.

On the other hand, in step S2,
The task of the "ready" state (CPU allocation waiting task) on the task ready queue 50 side has a higher priority than the task being executed by any of the CPUs 10-0 to 10-2 fetched in step S1. If the priority is higher than that of the (CPU executing task), the "executable" state task (CPU allocation waiting task) in the CPU (CPU having the CPU number extracted in step S1)
CPU 10-0 to switch the task to
(The task 11A being executed at) executes an instruction for generating a task switching execution interrupt to the CPU (step S4). The interrupt processing in the CPU that receives the task switching execution interrupt will be described later.

CPU 10-0 (task 11A being executed by)
Executes step S4, (C
CPU for which the PU number and priority are retrieved
The queue field 400 of the executing task priority data block and the queue field 500 of the task control block that was the priority extraction target in step S2 are referenced (step S5) to determine whether at least one is the final block. Whether (i.e., whether at least one of the task priority data queue 40 and the task ready queue 50 during CPU execution refers to the final block) is determined (step S6).

If neither the CPU executing task priority data queue 40 nor the task ready queue 50 refers to the final block, that is, the priority to be compared (in step S3) is recorded. If the next block exists, the CPU 10-0 (task 11A being executed) again executes steps S1 and S2, and indicates the queue field 400 in the CPU executing task priority data block referred to in step S5. CP from the next CPU executing task priority data block
The U number and the priority are fetched, and the priority is fetched from the next task control block indicated by the queue field 500 in the task control block referred to in step S5.

In this way, the second step S1,
In S2, the CPU executing task priority data queue 40
The priority (CPU number and) recorded in the second CPU executing task priority data block and the priority recorded in the second priority data block of the task ready queue 50 are extracted. Subsequently, the two priorities are compared in the next step S3. If the task on the task ready queue 50 side has a higher priority, steps S4 to S6 are performed as described above.

In the processes of steps S1 to S6, it is judged in the priority comparison process that the priority of the task being executed by the CPU is higher (step S3), or at least one of the data to be compared is lost. Is repeated (step S6).

As is clear from the above description, in the example of FIG. 2, first, the CPU executing task priority data queue 40
CPU number # 1 and CPU number # from the task priority data block 42 for the first CPU being executed
The priority 5 of the task 11B being executed by the first CPU 10-1 is extracted, and the priority 2 of the task indicated by the block 61E is extracted from the first task control block 61E connected to the task ready queue 50.

Then, the task 1 being executed by the CPU 10-1
1B, that is, the lowest priority 5 among the tasks 11A to 11C being executed by the CPUs 10-0 to 10-2.
And the priority of the task indicated by the task control block 61E,
That is, the highest priority 2 among the priorities of the tasks (CPU allocation waiting tasks) in the “executable” state is compared.

Here, since the priority 2 of the task indicated by the task control block 61E is higher than the priority 5 of the task 11B being executed by the CPU 10-1, the CPU 10-0 (task 11A being executed by) is , Executes an instruction for generating a task switching execution interrupt to the CPU 10-1.

Next, from the second CPU executing task priority data block 43, which is connected to the CPU executing task priority data queue 40, the CPU number # 2 and the corresponding C number.
The priority 4 of the task 11C being executed by the CPU 10-2 having the PU number # 2 is taken out, and the task indicated by the second (= final) task control block 61F connected to the task ready queue 50 is shown. Priority of 3 is taken out.

Then, the task 1 being executed by the CPU 10-2
1C, which is the second lowest priority of the tasks 11A to 11C being executed by the CPUs 10-0 to 10-2, and the priority of the task indicated by the task control block 61F, that is, "execution". The second highest priority among the priorities of the tasks (CPU allocation waiting tasks) in the “possible” state is compared.

In this case, the priority 3 of the task indicated by the task control block 61F is higher than the priority 4 of the task 11C being executed by the CPU 10-2, so that the CPU 10-0 (task 11A being executed by) is , Executes an instruction for generating a task switching execution interrupt to the CPU 10-2.

There are only two C in the task ready queue 50.
There is no PU allocation waiting task. Therefore, in FIG.
The task switching execution CPU selection processing according to the flowchart of FIG.

Next, the interrupt processing in the CPU which has received the task switching execution interrupt will be described with reference to the flowchart of FIG. First, when the CPU 10-0 executes an instruction for generating a task switching execution interrupt to the CPU 10-1 or CPU 10-2 as described above, the CPU 10-0 to the CPU 10-1 or CPU 10
For -2, a task switching execution interrupt is issued via the system bus 30. In the above example, first the CPU
A task switching execution interrupt is issued to 10-1, and then a task switching execution interrupt is issued to the CPU 10-2.

Upon receipt of the task switching execution interrupt from the CPU 10-0, the CPU 10-1 generates a task control block for the task 11B being executed and stores it in the control block, as in the normal task switching process. The execution environment (contents of various registers in the CPU 10-0) of the running task 11B is saved, and the control block is connected to the task ready queue 50 (step S11). In the example of FIG. 2, the task control block of the task 11B is the end of the task ready queue 50 (task control block 61F).
Next). By performing the execution environment saving process in step S11 described above, the execution can be restarted when the CPU is assigned to the task of the corresponding task control block.

Next, the CPU 10-1 removes the leading task control block 61E from the task ready queue 50 and sets the execution environment saved in the block 61E to C.
It is loaded into a register or the like in the PU 10-1 (step S1)
2). At that time, the CPU 10-1 updates the contents of the queue field 400 so that the second task control block 61F of the task ready queue 50 is at the head.

Further, the CPU 10-1 attempts to newly start the execution in the CPU executing task priority data block 42 in which its own CPU number # 1 is set as the priority of the task being executed by itself. Set the priority of the task to execute (try to restart execution) (step S1)
3). That is, the CPU 10-1 updates the priority set in the CPU executing task priority data block 42 to the priority of the task whose execution is to be resumed. that time,
The CPU 10-1 is the CPU executing task priority data block 4 on the CPU executing task priority data queue 40.
Nos. 2 to 44 are re-connected in ascending order of priority.

Then, the CPU 10-1 follows the task ready queue 50 according to the execution environment loaded in step S12.
The execution of the task indicated by the task control block 61E removed from is restarted (step S14).

As described above, when the task 11A being executed by the CPU 10-0 changes the task in the "waiting" state indicated by the task control blocks 61E and 61F to the "executable" state, in the example of FIG. From -0 (CPU 10-0 ~
In response to an interrupt for executing task switching to the CPU 10-1 which was executing the task 11B having the lowest priority among 10-2), the task control block 61E from the task 11B having the priority of 5 in the CPU 10-1. Is switched to the task having the priority of 2 (the task having the highest priority among the tasks waiting for CPU allocation in the state of FIG. 2).

Next, from the CPU 10-0 (CPU 10-0 ...
When a task switching execution interrupt is issued to the CPU 10-2, which was executing the task 11C having the second lowest priority among 10-2), the same interrupt processing as that of the CPU 10-1 described above is performed. Then, in the CPU 10-2,
From the task 11C having the priority of 4 (because the task control block 61E is removed first, the task is connected to the head of the task ready queue 50 at that time)
The task control block 61F switches to the task with the priority of 3 (the task with the second highest priority among the tasks waiting for CPU allocation in the state of FIG. 2).

To summarize the above, in this embodiment, the CPU
In the state where the task 11A of priority 1 is executed at 10-0, the task 11B of priority 5 is executed at the CPU 10-1, and the task 11C of priority 4 is executed at the CPU 10-2,
Task 11A running at 10-0 has task control block 6
When the tasks in the "waiting" state with the priorities 2 and 3 indicated by 1E and 61F are changed to the "executable" state (therefore, waiting for CPU allocation), the tasks executed by the CPUs 10-0 to 10-2, The tasks waiting for CPU allocation are as follows.

First, the task with the highest priority among the CPU allocation tasks, that is, the task with the highest priority, that is, the task with the priority 2 indicated by the task control block 61E, is C.
Of the PUs 10-0 to 10-2, the task 11B with the lowest priority (and lower priority than the task indicated by the task control block 61E) (task 11B with priority 5) is assigned to the executing CPU 10-1. And is executed by the CPU 10-1. Then, the task 11B having the priority of 5 which has been executed by the CPU 10-1 until then becomes the CPU allocation wait.

Similarly, the task control block 61F having the second highest priority next to the task indicated by the task control block 61E
The task with the priority of 3 indicates the next lower priority of the CPUs 10-0 to 10-2 (and the task control block 6 concerned).
A task 11C having a lower priority than the task indicated by 1E (task 11C having a priority of 4) is assigned to the executing CPU 10-2 and executed by this CPU 10-2. Then, the task 1 of priority 4 which has been executed by the CPU 10-2 until then
1C is waiting for CPU allocation.

As described above, according to this embodiment, the CPU 10
The task 11A running at -0 is the task control block 61
"Runnable" task in "waiting" state indicated by E and 61F
When the state is changed to the state, in addition to the priority 1 of the running task 11A and the task priorities 2 and 3 indicated by the task control blocks 61E and 61F of the task ready queue 50, other CPUs 10-1 and 10- Tasks 11B and 11 running in 2
Since the CPUs that execute task switching and the number thereof are determined in consideration of the priorities 5 and 4 of C as well, the task control blocks 61E and 61 of the task ready queue 50.
Priority of tasks waiting for CPU allocation indicated by F 2, 3
However, even if the priority is lower than the priority 1 of the executing task 11A that has changed the task in the "waiting" state to the "executable" state, the tasks having the priorities 2 and 3 are further lowered in priority 5 and 4
CPUs 10-1 and 10 executing tasks 11B and 11C of
Since it can be assigned to -2, effective scheduling that makes use of the multiprocessor configuration can be performed.

The above is the same when the tasks in the "waiting" state are changed to the "executable" state in the other CPUs 10-1 and 10-2. It should be noted that in the above-described embodiment, the case where it is implemented in a multiprocessor system having three CPUs has been described, but the present invention is applicable to all processor systems including a plurality of CPUs.

Further, in the above-described embodiment, the CPU that has accepted the task switching execution interrupt removes the first task control block from the task ready queue 50 and switches to the task indicated by the block. In this method, after a series of task switching execution CPU selection processing shown in the flowchart of FIG. 3 is completed, task switching is performed according to the task switching execution interrupt, and the task switching order is the corresponding task switching execution interrupt. There is no problem if they match the issue order. However, if this is not the case, the task that should be assigned to one CPU may be assigned to another CPU.

Therefore, in order to prevent such inconvenience, the CPU that has accepted the task switching execution interrupt
The following method may be applied instead of the method of removing the first task control block from the task ready queue 50 and switching to the task indicated by the block.

That is, for example, in the shared memory 20, a state management area (state management means) such as a flag indicating that the task switching execution CPU selection processing state (mode) is present, and each CPU 10-0 to 10-2 are associated. Then, a task ID area (task ID management means) in which the task ID is set is provided. Then, when a certain CPU (for example, the CPU 10-0) starts the task switching execution CPU selection processing, information indicating that it is in the processing state is set in the state management area (that is, the task switching execution CPU selection processing mode). Set),
When a task switching execution interrupt is generated, the task ID of the task assigned to the interrupt destination CPU
Is set in the task ID area corresponding to the CPU.
This task ID can be acquired when the priority is extracted from the task control block in step S2 of FIG. Further, when ending the series of task switching execution CPU selection processing, information indicating that the processing state is set in the state management area is cleared (that is, the task switching execution CPU selection processing mode is released).

C which has received the task switching execution interrupt
The PU refers to the state management area and executes task switching C
If it is not in the PU selection processing mode, immediately if it is in the task switching execution CPU selection processing mode, after waiting for the mode to be released (that is, the task switching execution CPU selection processing in the interrupt source CPU is completed), From the task ID area corresponding to itself, the task ID of the task to be switched (newly executed) is acquired, the task control block having the task ID is removed from the task ready queue 50, and the task control block Switch to the task shown.

In this way, the CPU that has received the task switching execution interrupt can execute the task switching execution after another CPU that has received the task switching execution interrupt has not finished the task switching. Correct task switching can be performed even if the other CPU that has received the interrupt has completed the task switching first.

When the task switching execution CPU selection process is started during task switching, the task switching process changes the states of the CPU executing task priority data queue 40 and the task ready queue 50. Therefore, there is a fear that the task switching execution CPU selection process cannot be performed correctly. Therefore, in order to prevent this, during the task switching period, information indicating that (task switching mode) is set in the state management area, and during this period, the task switching execution CPU selection process is made to wait. You can That is, the task switching process and the task switching execution CPU selection process may be exclusively controlled.

Further, in the above embodiment, in order to efficiently perform the task switching execution CPU selection processing, the priority being executed by each CPU in the multiprocessor system is the CPU.
Assuming that tasks that are being managed by the task-in-progress priority data queue 40 in ascending order of priority, and tasks that are waiting for CPU allocation in the “executable” state are managed by the task ready queue 50 in order of increasing priority. Although described, the present invention is not limited to these priority management methods. If the processing efficiency is not considered, it is not always necessary to manage in order of priority.

[0065]

As described above in detail, according to the present invention,
When task scheduling processing is required during execution of a task on a CPU in a multiprocessor system, not only the priority of the task being executed and the priority of the task group in the CPU allocation waiting state but also other CPUs In consideration of the priority of the task being executed, all the CPUs that should execute the task switching are configured so that the task having the lower priority is determined in order from the CPU that is executing. Therefore, the multiprocessor configuration is utilized. Optimal task scheduling can be performed.

Further, according to the present invention, the CPU that has accepted the interrupt is configured by generating a specific interrupt for activating the task switching process to the CPU that is determined to execute the task switching. In, the task switching to the task with higher priority can be performed immediately.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a task control block 61E, 61F in a “waiting” task group 60 in the same embodiment;
The figure which shows the system state at the time of being connected to the task ready queue 50 by changing from the "waiting" state to the "executable" state by the task 11A being executed by the CPU 10-0.

FIG. 3 is a flowchart for explaining task switching execution CPU selection processing in the embodiment.

FIG. 4 is a flowchart for explaining an interrupt process at the time of accepting a task switching execution interrupt in the embodiment.

[Explanation of symbols]

10-0 to 10-2 ... CPU (CPU selecting means, specific interrupt generating means), 11A to 11C ... Task, 20 ... Shared memory, 30 ... System bus, 40 ... CPU executing task priority data queue (first Management means), 42-44 ...
CPU executing task priority data block, 50 ... Task ready queue (second management means), 61D to 61F
... task control block.

Claims (5)

[Claims] 1. In a multiprocessor system in which a plurality of CPUs operate in parallel, a first management unit that manages the execution priority of a task that is being executed by each CPU, and a CPU allocation wait state in an executable state. A second managing means for managing a group of tasks that have become active, and when a task being executed by the CPU on the multiprocessor system changes the state of at least one other task, task scheduling processing is required. ,
By the CPU, the execution priority of the task being executed by each CPU managed by the first managing means and the execution of each task in the CPU allocation waiting state managed by the second managing means. Based on the priority, all the CPUs for which the task switching should be executed are sequentially determined in descending order of the execution priority of the task being executed by the CPU, and the task switching is executed by this CPU selecting means. Each time a CPU to be determined is determined, a specific interrupt generation unit that generates a specific interrupt for activating a task switching process for the CPU, and a CPU that has received the specific interrupt perform task switching according to the interrupt. A multiprocessor system comprising: interrupt processing means for performing. 2. In a multiprocessor system in which a plurality of CPUs operate in parallel, first management means for managing the execution priority of tasks being executed by each CPU in ascending order of priority, and an executable state. Second managing means for managing a task group waiting for CPU allocation in descending order of execution priority, and a task being executed by the CPU on the multiprocessor system changes the state of at least one other task. As a result, when task scheduling processing becomes necessary,
By the CPU, the execution priority of the task being executed by each CPU managed by the first managing means and the execution of each task in the CPU allocation waiting state managed by the second managing means. The priorities are taken out synchronously in order from the beginning, and both priorities are compared each time, and the CPU
If the execution priority of the task in the allocation waiting state is higher than the execution priority of the executing task, the CPU selecting means for determining the CPU on which the executing task is executed as the CPU to execute the task switching. Each time the CPU selecting means determines a CPU to execute the task switching, a specific interrupt generating means for generating a specific interrupt for activating the task switching process to the CPU, and a specific interrupt generating means for receiving the specific interrupt A multiprocessor system, comprising: an interrupt processing unit that switches a task in accordance with the interrupt in the CPU. 3. A task scheduling method in a multiprocessor system in which a plurality of CPUs operate in parallel, wherein a task being executed by a CPU on the multiprocessor system changes the state of at least one other task. When the scheduling process is required, the tasks in the CPU allocation waiting state at that time are executed in the order of higher priority of the tasks on the multiprocessor system which is executing the tasks of lower execution priority than the tasks. A task scheduling method in a multiprocessor system, wherein a task having a lower execution priority is sequentially assigned to the CPU of the first CPU. 4. A task scheduling method in a multiprocessor system in which a plurality of CPUs operate in parallel, wherein a task being executed by a CPU in the multiprocessor system changes the state of at least one other task. When a scheduling process becomes necessary, the execution priority of the task being executed by each CPU on the multiprocessor system at that time and the execution priority of the execution priority of each task in the CPU allocation waiting state are calculated based on the execution priority. All CPUs that should execute task switching
Is sequentially determined in the order of decreasing execution priority of tasks being executed by that CPU, and every time a CPU that executes task switching is determined in this first step, a task is executed for that CPU. A multistage comprising a second step of generating a specific interrupt for activating the switching process, and a third step of performing task switching in response to the interrupt in the CPU that has received the specific interrupt. Task scheduling method for processor system. 5. A task scheduling method in a multiprocessor system in which a plurality of CPUs operate in parallel, a task scheduling process as a result of a task being executed by a CPU on the multiprocessor system changing the state of at least one other task. When it becomes necessary, the operation of sequentially extracting the execution priorities of the tasks being executed by the CPUs in the ascending order of priority, and the execution priorities of the tasks in the CPU allocation waiting state in the descending order of priority. A first step of synchronously executing sequentially extracting operations, and at the first step, one execution priority of the task under execution and one execution priority of the task in the CPU allocation waiting state are extracted. Each time it is executed, the second step of comparing the two priorities is performed, and in the second step, the CPU allocation waiting state is set. Each time it is determined that the task execution priority is higher than the execution priority of the executing task, a specific interrupt for activating the task switching process is issued to the CPU on which the executing task is executed. And a fourth step of performing task switching in response to the interrupt in the CPU that has received the specific interrupt. The first to third steps are executed for the execution of the running task. It is judged in the second step that the priority is higher than the execution priority of the task in the CPU allocation waiting state, or the execution of the task being executed in the CPU to be compared in the second step. A task task in a multiprocessor system characterized by continuing until at least one of the priority and the execution priority of the task in the CPU allocation waiting state is exhausted. Scheduling method.