JPH08340532A - Quantization and reverse quantization arithmetic unit - Google Patents

Abstract

PURPOSE: To obtain a quantization/reverse quantization arithmetic unit with a small amount of hardware and a small area by calculating both quantization and reverse quantization in time division through the use of a fixed decimal point pipeline arithmetic unit. CONSTITUTION: In the quantization arithmetic operation of a quantization/reverse quantization arithmetic unit 100, selectors 11-1 to 11-4 respectively select quantized data F, a quantization weight coefficient Wq <-1> , an integer P, a reciprocal Mq <-1> of a quantization step and the data F and the coefficient Wq <-1> are given to a multiplier 7-1 and the result is stored in a register 10. Then a fraction part of the register 10 is processed by an arithmetic unit 8-1, a multiplier 7-1 and an adder/subtractor 9 and then processed by a multiplier 7-2 and an arithmetic unit 8-2 for the quantization. Then in the reverse quantization, the unit 100 receives an input (q) of a q-bit integer Q, a quantization weight coefficient Wi , a quantization step Mi and an integer N, the multiplier 7-1, the arithmetic unit 8-1 calculate q'=2q×Wi and an adder/substractor 9 calculates q"=q'+Sign(q).(N×Wi ) and the multiplier 7-1 and the arithmetic unit 8-2 calculate F'=q"×Mi .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for performing quantization and dequantization in an LSI that executes image signal encoding / decoding.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a hardware configuration of a conventional quantization / inverse quantization calculator 400 for performing quantization and inverse quantization in an image encoding / decoding LSI.

The quantizer / inverse-quantizer operator 400 will be described below by taking a fixed number of operations in two's complement representation as an example.

A conventional quantizer / inverse quantizer operator 400 is
It comprises a quantizer 1 and an inverse quantizer 2, and the quantizer 1
Input n _F- bit integer quantized data F, and n _Q
The quantizer 2 outputs a bit integer Q, and the inverse quantizer 2 inputs 2 · q (q is an integer of n _Q bits) and outputs an integer F ′ of n _{F, q} bits. It is an inverse quantizer, and executes a quantization operation and an inverse quantization operation by individual hardware.

FIG. 5 shows the quantizer / inverse-quantizer operator 40.
It is a figure which shows the quantizer 1 and the dequantizer 2 in 0 concretely.

The quantizer 1 and the inverse quantizer 2 shown in FIG. 5 are introduced in IPSJ Transactions Vol. 35 No. 7 "Research on Dedicated Video Coding Method for Multimedia". 2 is a configuration of a quantizer / inverse quantizer.

In FIG. 5, the quantizer 1 comprises an ALU 3 and a rounding / overflow calculator 4. A
The LU3 is an arithmetic operation unit having two multipliers as cores, and the quantized data F of n _F bit integers and the integer part are n.
_{W, q} bits, the reciprocal of the quantization weighting coefficient W _q ^-1 _, where the decimal part is f _{W, q} bits, and n _{M, q} bits for the integer part and f for the decimal part
_M, inputs the inverse M _q ^-1 of the quantization step is _q bits, calculates the ^{_{Q = {F × W q -1}} + sign (F × W q -1) · P} × M q -1, When x <0, x = 0, x> 0, si
The calculation is such that gn (x) is -1, 0, 1 respectively.

Further, the rounding / overflow calculator 4 is
The representation is standardized so that the number of digits of the output of the ALU 3 becomes the number of digits required for encoding.

In FIG. 5, the inverse quantizer 2 has an ALU5.
And accuracy adjuster 6. The ALU5 is also an arithmetic operation unit having two multipliers as its core. The input q of an n _Q- bit integer Q, the integer part is n _{W, i} bits, and the decimal part is f.
Quantization weight coefficient W _i , which is _{W, i} bits, and the integer part is n
_{M, i} bits, fewer unit inputs the quantization step M _i is f _{M, i} bits, n _F, 'a, F' integer F _q-bit = {2q + sign (q) · N} × W i It is calculated by × M _i . The accuracy adjuster 6 is
The standardized format is unified by preventing the calculation result from exceeding the specified value of the encoder.

[0010]

FIG. 6 is a schematic diagram of FIG.
It is a figure which shows the arithmetic unit structure of LU3, SPIE Vol.1605 Vi
sual Communications and Image Processing '91: Visua
l “VLSI Imprementation of A Buffe”
r, Universal quantizer and Frame rate control Proc
This is the configuration introduced in "essor".

In FIG. 6, the ALU 3 has two multipliers 7a and 7b and rounding and truncating circuits 8a and 8b for rounding and truncating the outputs of the multipliers 7a and 7b, respectively.
The ALU 3 has other small arithmetic circuits and pipeline registers for performing pipeline processing, but these are omitted in FIG.

In the conventional quantization / inverse quantization calculator 400, each of the quantization operation and the inverse quantization operation requires two multipliers. Therefore, in the above-mentioned conventional example, a total of four multipliers are required to perform the quantization and the dequantization, which results in a large amount of hardware of the quantization / dequantization operator. However, there is a problem that the occupied area of the quantization / inverse quantization calculator is large.

An object of the present invention is to provide a quantizer / inverse-quantizer operator having a small amount of hardware and a small area.

[0014]

According to the invention described in claims 1, 2, and 3, both quantization and dequantization are performed in a time division manner by using one fixed decimal point pipeline arithmetic unit. It is something that is calculated.

According to a fourth aspect of the present invention, two multiplications in the quantization and dequantization operations are executed by using one multiplier in time division.

According to a fifth aspect of the present invention, in the inverse quantization operation, the data with the smallest significant figures are sequentially multiplied.

[0017]

According to the invention described in claims 1, 2, and 3, both the quantization and the dequantization are performed in a time division manner by using one fixed decimal point pipeline arithmetic unit.
The amount of hardware required for quantization and dequantization operations can be reduced.

According to the fourth aspect of the present invention, two multiplications in the quantization and dequantization operations are executed by using one multiplier in time division, so that the quantization and the dequantization operations are required. The amount of hardware can be reduced.

According to the fifth aspect of the present invention, in the inverse quantization operation, the data having the smallest effective number is sequentially multiplied, so that the data width necessary for the inverse quantization operation is reduced and the wiring of the operator unit is reduced. can do.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a quantization / inverse quantization calculator 100 according to a first embodiment of the present invention.

The quantizer / inverse-quantizer operator 100 performs both quantization and inverse-quantization in time division by a single fixed-point pipeline arithmetic unit.

The quantization / inverse quantization calculator 100 includes multipliers 7-1 and 7-2, a rounding / truncating calculator 8-1 for rounding / truncating the multiplication result output from the multiplier 7-1, An arithmetic unit 8-2 that rounds / truncates the multiplication result output from the multiplier 7-2, an adder / subtractor 9, a plurality of pipeline registers 10, and 2-input 1-output selectors 11-1 and 11-.
2, 11-3, 11-4, 11-5 and the zero detector 12
And the input q of the integer Q is arithmetically shifted to the left by 1 bit, and 2q
And a shifter 16 for outputting

In FIG. 1, reference numeral 13 is a zero detection result for the output of the rounding / truncating calculator 8-1,
Reference numeral 14 is a sign flag output from the rounding / truncating calculator 8-1, and 15 is a switching signal for quantization / inverse quantization.

Further, the quantization / inverse quantization calculator 100 is
n _F bit integer quantized data F and integer part n _{W, q}
Bit, the reciprocal quantized weight coefficient W _q ⁻¹ whose fractional part is f _{W, q} bits, and n _{M, q} bits for the integer part and f _{M, q for the} decimal part
Input the reciprocal of the quantization step M _q ⁻¹ which is a bit and the integer P whose integer part is n _{P, q} bits, and F ₀ = F × W _q ⁻¹ Q = (F ₀ + sign (F ₀ ). • P) × M _q ⁻¹ x <0, x = 0, and x> 0, then sign (x)
Quantization operation is performed by obtaining an integer Q of n _Q bits by an operation in which each becomes -1, 0, 1.

Further, the quantization / inverse quantization calculator 100
Is an input q of an n _Q- bit integer Q and a quantization weighting coefficient W _i whose integer part is n _{W, i} bits and whose decimal part is f _{W, i} bits.
And a quantization step M _{i in} which the integer part is n _{M, i} bits and the decimal part is f _{M, i} bits, and an integer N in which the integer part is n _{n, i} bits, and F ′ = (2q + sign The inverse quantization operation is performed by outputting an integer F ′ of n _{F, q} bits by the operation of (q) · N) × W _i × M _i .

Next, the operation of the quantization / inverse quantization calculator 100 will be described.

First, the case where the quantization / inverse quantization calculator 100 performs a quantization operation will be described. At the time of the quantization operation, the quantized data F of n _F bit integer and the integer part are n
_{W, q} bits, the reciprocal of the quantization weighting coefficient W _q ^-1 _, where the decimal part is f _{W, q} bits, and n _{M, q} bits for the integer part and f for the decimal part
The reciprocal of the quantization step of _{M, q} bits M _q ^-1 and the integer _{P of} which the integer part is n _{P, q} bits are input, and the multiplier 7-
1 and the arithmetic unit 8-1 calculates F ₀ = F × W _q ⁻¹ , and then the adder / subtractor 9 calculates F ₁ = F ₀ + sign (F ₀ ). -The second multiplier composed of the multiplier 7-2 and the calculator 8-2 calculates P and calculates Q = F ₁ × M _q ^-1 .

That is, in the first pipeline stage, the selectors 11-1, 11-2, 11-3, 11-4 are used.
Are the quantized data F and the quantization weight coefficient W _q , respectively.
^-1 , integer P, the reciprocal of the quantization step M _q ^-1 , and
The quantized data F and the quantization weight coefficient W _q ⁻¹ are input to the multiplier 7-1 and the result is stored in the register 10.

In the second pipeline stage, the arithmetic unit 8-1 rounds / truncates the decimal part of the register 10 and converts the output result of the multiplier 7-1 into an integer. In the third pipeline stage, the adder / subtractor 9 adds and subtracts the output of the rounding / truncating calculator 8-1 and the value of P selected by the selector 11-3.

Here, when the output of the rounding / truncating arithmetic unit 8-1 is "0", the output of the zero detector 12 becomes "1", and the selector 11-5 selects "0" and outputs it. To do.

In the fourth pipeline stage, the multiplier 7-2 outputs the output of the selector 11-5 to the selector 11-.
The output of 4 (M _q ^-1 ) is multiplied. In the fifth pipeline stage, the rounding / truncating calculator 8-2 operates as the multiplier 7
The output of the multiplier 7-2 is converted into an integer by rounding / truncating the decimal part of the output of -2. The quantization operation is completed by the above operation.

Next, the case where the quantization / inverse quantization calculator 100 performs an inverse quantization operation will be described.

At the time of inverse quantization, the input q of the n _Q- bit integer Q
And a quantization weight coefficient W _{i in} which the integer part is n _{W, i} bits and the decimal part is f _{W, i} bits, and quantization in which the integer part is n _{M, i} bits and the decimal part is f _{M, i} bits The step M _i and the integer N whose integer part is n _{n, i} bits are input, and the multiplier 7-1
And a calculator 8-1 calculate q ′ = 2q × W _i , and then the adder / subtractor 9 calculates q ″ = q ′ + sign (q) · (N × W _i ), and the second multiplier composed of the multiplier 7-1 and the calculator 8-2 calculates F ′ = q ″ × M _i .

That is, in the first pipeline stage, the selectors 11-1, 11-2, 11-3, 11-4 are used.
Are the output 2q of the shifter 16 and the integer part n _{W, i} , respectively.
Bit, the quantization weighting coefficient W whose decimal part is f _{W, i} bits
_i, the integer portion n _n, an integer N · W _i is a _i-bit integer part is n _{M, i} bits, the fractional part selects f _M, a _i-bit quantization step M _i.

The output 2q and the quantization weight coefficient W _i are input to the multiplier 7-1, and the multiplication result is stored in the register 10. In the second pipeline stage, the rounding / truncating calculator 8-1 rounds / truncates the contents of the register 10 and adjusts the significant figures. In the third pipeline stage, the output of the rounding / truncating calculator 8-1 and the value of the integer N · W _i selected by the selector 11-3 are added and subtracted.

Here, when the output of the rounding / truncating calculator 8-1 is "0", the output of the zero detector 12 becomes "1", the selector 11-5 selects "0", and the output To do.
Note that when sign (x) = 0, the selector 11-5
Selects "0".

By the way, in the case of detecting zero in the output result of the rounding / truncating arithmetic unit, if the number of digits of the number to be zero detected is large, the delay due to the zero detecting operation cannot be ignored, but the zero detecting operation is performed. Can be executed in parallel with addition and subtraction, so that the delay due to the zero detection operation can be canceled, and the delay due to the zero detection operation does not actually pose a problem.

In the above embodiment, the sign is
When (x) = 0, the output of the adder / subtractor 9 is always “0”. Therefore, when sign (x) = 0, the selector 1
1-5 is used to forcibly set the operation result to "0". However, instead of doing so, the definition of the formula may be directly realized.

Then, in the fourth pipeline stage, the multiplier 7-2 is used, and the output of the selector 11-5 is
Multiply by M _i which is the output of the selector 11-4. In the fifth pipeline stage, the first rounding / truncating process of the output of the multiplier 7-2 is performed to adjust the significant figures. The above operation completes the inverse quantization operation.

Quantization / inverse quantization calculator 100 shown in FIG.
In the above, both quantization and dequantization are performed in the order of multiplication, rounding / truncation, addition / subtraction, multiplication, and rounding / truncation. May be.

In the above embodiment, the quantizing / inverse quantizing switching signal 15 and the input signals of the selectors 11-3 and 11-4 pass through the pipeline register 10, and the timing adjusts the timing of the pipeline stage. It is carried out. However, without using the pipeline register 10, the above signals are input from the outside at an appropriate timing,
You may make it supply to the arithmetic unit of a pipeline stage.

In the quantization / inverse quantization calculator 100,
Whether you perform a quantization operation or an inverse quantization operation,
The same fixed-point pipeline arithmetic unit (mainly the multipliers 7-1 and 7-2 and the rounding / truncating arithmetic unit 8-1,
8-2 and the adder / subtractor 9), it is sufficient to provide two multipliers as a whole, thus reducing the amount of hardware required for the quantization operation and the inverse quantization operation. can do. It should be noted that the selector 11-1 and the selector 11-1, depending on whether the quantization operation is performed or the inverse quantization operation is performed,
Since the parameters 11-2, 11-3, and 11-4 time-share the parameters to be used, parameter collision does not occur.

FIG. 2 is a diagram showing a quantization / inverse quantization calculator 200 according to a second embodiment of the present invention.

The quantization / inverse quantization calculator 200 executes two multiplications in the quantization and inverse quantization operations by using one multiplier in time division.

The quantization / inverse quantization calculator 200 has a 4-input 1-output selector 17 and a 3-input 1-output selector 18. The signal 15-1 is the selector 17 and the selector 18.
Is a quantization / inverse-quantization switching signal for switching parameters input to and, and a signal 15-2 is a switching signal for switching the signal input to the rounding / truncating calculator 8-2 for quantization / inverse quantization. It is a signal.

When the signal 19-1 is quantized / dequantized, the selector 17 selects whether the input of the first multiplication or the input of the second multiplication is selected. This is a switching signal for switching to the selector 18. The signal 19-2 determines whether to perform rounding / truncation operation of the first multiplication result or rounding / truncation operation of the second multiplication result when performing quantization / inverse quantization processing. This is a switching signal for switching to the round-down calculator 8-2. In addition, 20 is a return path of the addition result.

Next, the operation of the quantization / inverse quantization calculator 200 will be described.

First, the case where the quantizing / inverse quantizing calculator 200 performs a quantizing operation will be described. In the first pipeline stage, the selectors 17 and 18 output the quantized data F and the inverse W _q ⁻¹ of the quantization weighting coefficient, respectively. In the second pipeline stage, the multiplier 7-2
Performs the first multiplication. In the third pipeline stage, the rounding / truncating arithmetic unit 8-2 performs rounding / truncating processing on the result of the first multiplication to perform integerization. Four
In the th pipeline stage, the adder / subtractor 9 adds the rounded-down results. This addition result is returned to the return path 20.
To the selector 18 through.

After that, the selector 17 outputs the reciprocal of the quantization step M _q ^-1 , and the selector 18 outputs the addition result of the adder / subtractor 9. In the fifth pipeline stage,
The multiplier 7-2 performs the second multiplication. In the sixth pipeline stage, the arithmetic unit 8-2 rounds / truncates the second multiplication result, performs integer conversion, and outputs the result as the quantization result.

Next, the case where the quantization / inverse quantization calculator 200 performs an inverse quantization operation will be described.

[0051] In the first pipeline stage, the selector 17 outputs 2q, a W _i, respectively, in the second pipeline stage, arithmetic unit 7-2 performs a multiplication of 1 time. In the third pipeline stage, the arithmetic unit 8-2 rounds and truncates the result of the first multiplication to convert it into an integer. In the fourth pipeline stage, the rounding-down result is added by the subtractor 9, and the addition result is input to the selector 18 through the feedback path 20.

After that, the selector 17 outputs M _i , and the selector 18 outputs the addition result of the adder / subtractor 9. 5
In the th pipeline stage, the multiplier 7-2 performs the second multiplication. In the sixth pipeline stage,
The arithmetic unit 8-2 rounds and rounds the first multiplication result, converts it into an integer, and outputs the result as an inverse quantization result.

In the quantization / inverse quantization calculator 200,
The quantized data F is input once every two cycles, and the inverse quantized data q is also input once every two cycles. In this case, there must be an even number of pipeline stages between the pipeline stage that performs multiplication and the pipeline stage that performs rounding / truncation. That is, when the first quantization / inverse quantization multiplication is executed in the odd-numbered pipeline stages, if the second multiplication is performed in the even-numbered pipeline stages, a certain data It is possible to avoid the competition between the multiplier for the first multiplication and the multiplier for the second multiplication. Note that if the first multiplication is executed in the even stages, the second multiplication is executed in the odd stages.

As described above, unless the relationship that an even number of pipeline stages always exists between the pipeline stage for performing multiplication and the pipeline stage for performing rounding / truncation is not damaged, the pipeline register 10 Can be arranged freely.

In the quantization / inverse quantization calculator 200,
Since the multiplication in the quantization operation and the multiplication in the dequantization operation are performed twice using one multiplier 7-2, it is necessary for the quantization operation and the dequantization operation. The amount of hardware can be reduced more than ever before. Since the selectors 17, 18, and 15-2 time-share the parameters between the case of performing the quantization operation and the case of performing the inverse quantization, the parameter collision does not occur.

In the quantizer / inverse-quantizer operator 200 shown in FIG. 2, even if the inputs F and Q of the selector 18 and the inputs W _i and W _q ^{-1 of} the selector 17 are exchanged, Similar effects are obtained.

FIG. 3 is a diagram showing a quantization / inverse quantization calculator 300 according to a third embodiment of the present invention.
． Quantization /
The inverse quantization calculator 300 multiplies in order from the data with the smallest significant number in the inverse quantization operation.

In the quantization / inverse quantization calculator 300,
Reference numeral 10 indicates a pipeline register,
Of these, reference numerals 10-1, 10-2, and 10-3 denote the third
Are newly numbered to describe the embodiment of FIG.

Further, the quantization / inverse quantization calculator 300 is
It has 4-input 1-output selectors 17-1 and 17-2, selectors 11-1 and 11-2, and a shifter 16. If the switching signal 19-1 specifies quantization, the shifter 16
If the input of the shifter 16 is output as it is and the inverse quantization is designated, the input of the shifter 16 is shifted to the left by 1 bit and is output (the input is doubled and output).

The adder / subtractor input switching signal 14 is supplied to the adder / subtractor 9
Is a switching signal for switching whether the operation of is used in the quantization operation or the inverse quantization operation in the cycle.

The feedback path 21 is a line connecting the output of the selector 11-3 and the input of the selector 17-2, and the feedback path 22 is a line connecting the output of the register 10-3 and the input of the selector 17. Yes, the feedback path 23 is a register 1 that stores the result of the rounding / truncating operation performed by the arithmetic unit 8.
The output of 0 is a line connecting the selector 17-1 and the input of the selector 11-1 which is input to the adder / subtractor 9.

The reference numerals of other parts are associated with each other in the same manner as in FIG. 2, and the description thereof will be omitted. Also, signal 15-
1, 15-2, 19-1 and 19-2 are also associated with the quantization / inverse quantization calculator 200 shown in FIG.

Next, the operation of the quantization / inverse quantization calculator 300 will be described.

First, the operation of the quantizer / inverse-quantizer operator 300 when performing quantization will be described. In the first pipeline stage, the selector 17-1 outputs the reciprocal W _q ⁻¹ of the quantization weight coefficient, and the selector 17-2
Outputs the quantized data F. In the second pipeline stage, the multiplier 7-2 performs the first multiplication. Three
In the second pipeline stage, the rounding / truncating calculator 8 converts the first multiplication result into an integer. In the fourth pipeline stage, the product of the first multiplication obtained in the third stage is passed through the feedback path 23 to the selector 1
Enter in 1-1. The selector 11-1 uses the feedback path 23.
, The selector 11-2 selects the integer P.

The shifter 16 is activated by the switching signal 19-1.
Outputs the output of the selector 11-1 as it is. The adder / subtractor 9 adds and subtracts the output of the shifter 16 and the output of the selector 11-2, and inputs the result to the selector 17-2 via the feedback path 21. The selector 17-1 outputs the reciprocal M _q ^-1 of the quantization weighting coefficient, and the selector 17-2 outputs the value passed through the feedback path 21. In the fifth pipeline stage, the multiplier 7-2 performs the second multiplication,
In the th pipeline stage, the arithmetic unit 8 converts the product of the second multiplication into an integer and obtains the quantization result.

Next, the case where the quantization / inverse quantization calculator 300 performs inverse quantization will be described. In the first pipeline stage, the selector 17-1 outputs the quantization weight coefficient W _i , and the selector 17-2 outputs the quantization step M _i .

Here, the selector 17-1 outputs the quantization weight coefficient W _i , and the selector 17-2 outputs the quantization step M _{i.
When i} is output, n _Q > n _{W, i} and n _Q > n for integer Q _i , quantization weight coefficient W _i , and quantization step M _i.
Since the relationship of _{M and i} is maintained, the data with the smallest significant figures are sequentially multiplied.

The selector 11-1 selects the value of 2q, and the selector 11-2 selects N. Addition / subtraction input switching signal 1
By 9-1, the shifter 16 shifts the output of the selector 11-1 to the left by 1 bit and outputs it. The adder / subtractor 9 is
The output of the shifter 16 and the output of the selector 11-2 are added and subtracted, and the result of the selector 11-3 is added to the pipeline register 1
It is stored in 0-1.

In the second pipeline stage, the multiplier 7-2 performs the first multiplication. In the third pipeline stage, the rounding / truncating calculator 8 converts the first multiplication result into an integer, and the result is input to the selector 17-1 via the feedback path 23. In the fourth pipeline stage, the selector 17-1 selects the value of the feedback path 23, and the selector 17-2 receives the pipeline register 1 input to the selector 17-2 via the feedback path 22.
Select contents 0-3. In the fifth pipeline stage, the multiplier 7-2 performs the second multiplication. In the sixth pipeline stage, the arithmetic unit 8 converts the product of the second multiplication into an integer to obtain an inverse quantization result.

In the quantization / inverse quantization calculator 300,
The quantized data F is input once every two cycles, and the dequantized data q is also input once every two cycles. At this time, there must be an even number of pipeline stages between the pipeline stage that performs multiplication and the pipeline stage that performs rounding / truncation. The pipeline register 10 can be freely arranged as long as this relationship is not damaged.

In the quantizer / inverse-quantizer operator 200, for input data, n _Q > n _{W, i} and n
_{If Q} > n _{M, i} , the multiplication with 2q having the largest significant number as the multiplicand is performed first.

However, the quantization / inverse quantization calculator 300
Is multiplied in order from the data with the smallest significant number as described above at the time of the inverse quantization operation, and by doing so, the data width of the multiplication result becomes small, and therefore the data width required for the inverse quantization operation is also reduced. Since the size is reduced, the wiring of the arithmetic unit can be reduced.

That is, in the above embodiment, the parameter selecting means for switching and outputting the quantization parameter required for quantization and the inverse quantization parameter required for inverse quantization,
A common arithmetic means for executing the quantization operation based on the quantization parameter output by the parameter selecting means and an inverse quantization operation based on the inverse quantization parameter output by the parameter selecting means. Is a quantization / inverse quantization calculator having

In this case, the above-mentioned quantization operation is performed by reciprocal number W of the quantization weighting coefficient _F whose n _F bit integer is n _{W, q} bits and whose decimal part is f _{W, q} bits. _q ^-1
, And the reciprocal of the quantization step M _q ⁻¹ whose integer part is n _{M, q} bits and whose decimal part is f _{M, q} bits, and integer _P whose integer part is n _{P, q} bits, and F ₀ = F × W _q ⁻¹ Q = (F ₀ + sign (F ₀ ) · P) × M _q ^{−1 When} x <0, x = 0, x> 0, sign (x)
Is an operation to obtain an integer Q of n _Q bits by the operations of becoming -1, 0, and 1, respectively.

In the inverse quantization operation, the input q of the n _Q- bit integer Q, the integer part is n _{W, i} bits, and the decimal part is f.
Quantization weight coefficient W _i , which is _{W, i} bits, and the integer part is n
_M, Type _i bits, fractional part is f _M, and the quantization step M _i is the _i-bit integer part is n _n, the integer N is _i bits, F '= (2q + sign (q) · N) It is an operation of outputting an integer F ′ of n _{F, q} bits by an operation of × W _i × M _i .

[0076]

According to the present invention, since the number of multipliers used in the quantization / inverse quantization calculator can be reduced, the amount of hardware and the area in the quantization / inverse quantization calculator are small. Play.

[Brief description of drawings]

FIG. 1 is a block diagram showing a quantization / inverse quantization calculator 100 that is a first embodiment of the present invention.

FIG. 2 is a block diagram showing a quantization / inverse quantization calculator 200 according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a quantization / inverse quantization calculator 300 which is a third embodiment of the present invention.

FIG. 4 is a conventional quantization / inverse quantization calculator 40 for performing quantization and inverse quantization in an image encoding / decoding LSI.
It is a figure which shows the hardware constitutions of 0.

5 is a diagram specifically showing a quantizer 1 and an inverse quantizer 2 in the quantizer / inverse-quantizer operator 400. FIG.

6 is a diagram showing a configuration of an arithmetic unit of the ALU3 shown in FIG.

[Explanation of symbols]

100, 200, 300 ... Quantization / inverse quantization calculator, 7-1, 7-2 ... Multiplier, 8-1, 8-2 ... Rounding / truncating calculator, 9 ... Adder / subtractor, 10 ... Pipeline register , 11, 11-1, 11-2, 11-3, 11-4, 11
-5, 15-2, 17, 17-1, 17-2, 18, 1
9 ... Selector, 13 ... Zero detector, 14 ... Sign flag, 16 ... Shifter, F ... n _F bit integer quantized data, W _q ^-1 ... Integer part is n _{W, q} bits, and decimal part is f _{W ,} the reciprocal of the quantization weighting coefficient that is _q bits, M _q ⁻¹ ... The integer part is n _{M, q} bits, the decimal part is the reciprocal of the quantization step that is f _{M, q} bits, P ... The integer part is n _{P, q-} bit integer, Q ... n _Q- bit integer, q ... n _Q- bit integer Q input, W _i ... Quantization weight coefficient whose integer part is n _{W, i} bits, and decimal part is f _{W, i} bits , M _i ... Quantization step in which the integer part is n _{M, i} bits and the decimal part is f _{M, i} bits, N ... Integer in which the integer part is n _{n, i} bits.

Claims (5)

[Claims] 1. A quantization parameter required for quantization,
A parameter selecting means for switching and outputting an inverse quantization parameter necessary for inverse quantization; a quantization operation based on the quantization parameter output by the parameter selecting means, and a parameter selecting means And a common arithmetic means for executing an inverse quantization operation on the basis of the above-mentioned inverse quantization parameter output by the above-mentioned quantization / inverse quantization operator. 2. The quantized data according to claim 1, wherein the quantized data F is an n _F bit integer.
And the reciprocal of the quantization weighting coefficient W _q ^-1 , where the integer part is n _{W, q} bits and the decimal part is f _{W, q} bits, and the integer part is n _{M, q} bits, and the decimal part is f _{M, q} bits the reciprocal M _q ^-1 of the quantization step is, integer part inputs the integer P is n _{P, q bits, F 0 = F × W q} -1 Q = (F 0 + sign (F 0) · P) × M _q ⁻¹ x <0, x = 0, and x> 0, sign (x)
Is an operation for obtaining an n _Q- bit integer Q by an operation in which −1, 0, and 1, respectively, and the dequantization operation is performed by inputting an n _Q- bit integer Q and an integer part of n _{W, i} bits. , The quantizing weight coefficient W _i whose fractional part is f _{W, i} bits, and the integer part n _{M, i} bits, and the fractional part f
Quantization step M _i , which is _{M, i} bits, and the integer part is n
Inputting an integer N which is _{n, i} bits, and outputting the integer F ′ of n _{F, q} bits by the operation of F ′ = (2q + sign (q) · N) × W _i × M _i Quantization / dequantization calculator. 3. Quantized data F of n _F bit integers,
The reciprocal of the quantization weight coefficient W _q ⁻¹ _, where the integer part is n _{W, q} bits and the decimal part is f _{W, q} bits, and the integer part is n _{M, q} bits,
Reciprocal number of quantization step M _q whose fractional part is f _{M, q} bits
⁻¹ and an integer _P whose integer part is n _{P, q} bits are input, and F ₀ = F × W _q ⁻¹ Q = (F ₀ + sign (F ₀ ) · P) × M _q ⁻¹ x < When 0, x = 0, and x> 0, sign (x)
Quantization operation to obtain an integer Q of n _Q bits by an operation of becoming -1, 0, 1, an input q of an n _Q bit integer Q, and an integer part of n _{W, i} bits,
Quantization weight coefficient W _i having a decimal part of f _{W, i} bits, a quantization step M _i having an integer part of n _{M, i} bits and a decimal part of f _{M, i} bits, and an integer part of n _n, an integer N that is _i bits
Quantization / inverse quantification, which is performed by inputting and F ′ = (2q + sign (q) · N) × W _i × M _i and outputting an integer F ′ of n _{F, q} bits. In the quantization operation unit, the reciprocal W _q of the data to be quantized F and the quantization weight coefficient
⁻¹ , the reciprocal of the quantization step M _q ^−1, and the integer P, the input q, the quantization weight coefficient W _i , the quantization step M _i, and the integer N. A parameter selection means for switching and outputting the included inverse quantization parameter; a first multiplier having a product rounding function and a truncation function for multiplying the parameter output by the parameter selection means; And an adder / subtractor for inputting the output of the first multiplier; and a function for rounding and truncating the product and inputting the output of the adder / subtractor. And a second multiplier for performing a quantization operation, which is a pipeline arithmetic unit that outputs a valid arithmetic result no matter what timing data is input to the first multiplier. Inverse quantization calculator. 4. Quantized data F of n _F bit integers,
The reciprocal of the quantization weight coefficient W _q ⁻¹ _, where the integer part is n _{W, q} bits and the decimal part is f _{W, q} bits, and the integer part is n _{M, q} bits,
Reciprocal number of quantization step M _q whose fractional part is f _{M, q} bits
⁻¹ and an integer _P whose integer part is n _{P, q} bits are input, and F ₀ = F × W _q ⁻¹ Q = (F ₀ + sign (F ₀ ) · P) × M _q ⁻¹ x < When 0, x = 0, and x> 0, sign (x)
Quantization operation to obtain an integer Q of n _Q bits by an operation of becoming -1, 0, 1, an input q of an n _Q bit integer Q, and an integer part of n _{W, i} bits,
Quantization weight coefficient W _i having a decimal part of f _{W, i} bits, a quantization step M _i having an integer part of n _{M, i} bits and a decimal part of f _{M, i} bits, and an integer part of n _n, an integer N that is _i bits
Quantization / inverse quantification, which is performed by inputting and F ′ = (2q + sign (q) · N) × W _i × M _i and outputting an integer F ′ of n _{F, q} bits. In the quantization operation unit, the reciprocal W _q of the data to be quantized F and the quantization weight coefficient
⁻¹ , the reciprocal of the quantization step M _q ^−1, and the integer P, the input q, the quantization weight coefficient W _i , the quantization step M _i, and the integer N. A parameter selection means for switching and outputting the included dequantization parameter; a multiplier having a product rounding function and a truncation function for multiplying the parameter output by the parameter selection means; and an input of this multiplier A selector for selecting; an adder / subtractor having a function of switching operation contents depending on whether the augend is positive, zero, or negative; and a feedback for inputting the output of the adder / subtractor to the selector. The output of the multiplier is input to the multiplier again via the adder / subtractor and the selector after odd cycles, and data is input to the multiplier at any timing. Is also legitimate Quantization / dequantization calculator, which is a pipeline operation unit for outputting the operation result. 5. Quantized data F of n _F bit integers,
The reciprocal of the quantization weight coefficient W _q ⁻¹ _, where the integer part is n _{W, q} bits and the decimal part is f _{W, q} bits, and the integer part is n _{M, q} bits,
Reciprocal number of quantization step M _q whose fractional part is f _{M, q} bits
⁻¹ and an integer _P whose integer part is n _{P, q} bits are input, and F ₀ = F × W _q ⁻¹ Q = (F ₀ + sign (F ₀ ) · P) × M _q ⁻¹ x < When 0, x = 0, and x> 0, sign (x)
Quantization operation to obtain an integer Q of n _Q bits by an operation of becoming -1, 0, 1, an input q of an n _Q bit integer Q, and an integer part of n _{W, i} bits,
Quantization weight coefficient W _i having a decimal part of f _{W, i} bits, a quantization step M _i having an integer part of n _{M, i} bits and a decimal part of f _{M, i} bits, and an integer part of n _n, an integer N that is _i bits
Quantization / inverse quantification, which is performed by inputting and F ′ = (2q + sign (q) · N) × W _i × M _i and outputting an integer F ′ of n _{F, q} bits. In the quantization operation unit, the reciprocal W _q of the data to be quantized F and the quantization weight coefficient
⁻¹ , the reciprocal of the quantization step M _q ^−1, and the integer P, the input q, the quantization weight coefficient W _i , the quantization step M _i, and the integer N. A parameter selecting means for switching and outputting the included inverse quantization parameter; a multiplier having a product rounding function and a truncating function, and multiplying the output of the parameter selecting means; An adder / subtractor that switches the content of the operation depending on the negative; and a temporary storage register that stores the output of this adder / subtractor; integer Q _i ;
_i , the quantization step M _i , when there is a relation of n _Q > n _{W, i} and n _Q > n _{M, i} , the output of the parameter selecting means is input to the multiplier, and the parameter selecting means Is connected to the input of the parameter selecting means via the adder / subtractor and the feedback path, and via the parameter selecting means and the temporary storage register, and after an odd number of cycles, the output of the adder / subtractor is sent to the multiplier. Input again, the addition and subtraction by the adder / subtractor and the selection of the multiplier and the multiplicand by the parameter selection means are performed in the same pipeline stage, and no matter what timing the data is input to the multiplier, a valid operation result is obtained. Quantization / inverse quantization calculator, which is a pipeline calculator that outputs