JPH08340239A - Correcting group delay generating circuit - Google Patents

Abstract

PURPOSE: To set a circuit prior to the measurement of a group delay characteristic by generating group delay with quantity corresponding to the resistance value of a group delay quantity setting resistor by frequency corresponding to a frequency setting signal and correcting a group delay characteristic appearing on transmission characteristics. CONSTITUTION: Voltage controlled oscillator(VCO) 5 in a clock oscillation circuit 1 is oscillated with frequency corresponding to DC voltage supplied from a phase locked loop(PLL) 4 and the PLL 4 impresses DC voltage generated by comparing the phase of an n-divided frequency signal with that of a signal obtained by dividing the frequency of a reference clock into m components to the VCO 5. When a dip switch 3 is manually set, the frequency divider ratio (n) is changed and the frequency of a clock can be changed. A group delay correcting filter 2 for generating group delay in accordance with the frequency of the clock generates group delay with quantity corresponding to the resistance value of a variable resistor R3 by changing the resistance value to correct a group delay characteristic appearing on the transmission characteristics of a receiver or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correcting group delay generating circuit for generating a group delay for correcting a group delay characteristic appearing in a transmission characteristic of a receiver or the like.

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a correction group delay generation circuit according to a conventional example. The circuit shown in this figure comprises a clock oscillation circuit 1 and a group delay correction filter 2.

The clock oscillation circuit 1 generates a clock of a predetermined frequency and supplies it to the group delay correction filter 2 via a clock input terminal CLK. The group delay correction filter 2 is
At a frequency that is an integral fraction of this clock, the resistor R3
An amount of group delay that is determined by the resistance value of is generated. When a group delay is generated by the group delay correction filter 2, the values of the resistors R1 and R2 connected to the group delay correction filter 2 are set to the same value, and the value of the resistor R3 is set to the required group delay. Set according to the amount of. After setting in this way, when a signal output from a receiver or the like, that is, a signal whose group delay characteristic is to be corrected is input from one of the terminals of the group delay correction filter 2 that is connected to the resistor R1 , A terminal having a connection with the resistor R2 provides a signal having a characteristic in which the group delay at a frequency of an integral fraction of the clock is corrected by an amount corresponding to the value of the resistor R3.

[0004]

When attempting to correct the group delay characteristic using such a circuit, it is an object of correction of the group delay characteristic before designing the clock oscillation circuit 1 and the group delay correction filter 2. It is necessary to measure the group delay characteristics of the signal, for example, the output signal of the receiver. That is, in the conventional circuit, the clock oscillation circuit 1 and the group delay correction filter 2 cannot be designed until the adjustment stage is reached and the group delay characteristics of the receiver or the like are measured. Had to occur.
Further, when the group delay characteristic of the receiver or the like changes due to aging or the like, the clock oscillation circuit 1 and the group delay correction filter 2 have been forced to be redesigned.

The present invention has been made to solve the above problems, and it is possible to easily and variably set the characteristics of the filter for correcting the group delay so that the signal to be corrected can be adjusted. The purpose of the present invention is to enable circuit design prior to measuring the group delay characteristic, and to suppress the inevitable delay in the design process. The present invention
An object of the present invention is to make it possible to deal with a case where the group delay characteristic changes due to aging etc. without redesigning the circuit. An object of the present invention is to make it possible to correct the group delay characteristic more accurately than before.

[0006]

In order to achieve such an object, the present invention provides an oscillator circuit for generating a frequency setting signal whose frequency can be variably set, and a group delay whose resistance value can be variably set. A group that appears in the transmission characteristics of a receiver, etc., and that includes a quantity setting resistor and a filter that generates a group delay at a frequency that corresponds to the frequency of the frequency setting signal and that corresponds to the resistance value of the group delay setting resistance. A feature is that a group delay for correcting the delay characteristic is generated.

Further, according to the present invention, the oscillator circuit oscillates at a frequency according to the applied voltage, and a signal obtained by dividing the signal obtained from the VCO by n (n: natural number). And a reference signal of a predetermined frequency divided by m (m:
PLL (phase locked loop) that generates a voltage to be applied to the VCO by comparing the phase with a signal that is a natural number)
And a switch for manually setting the frequency division ratio n.

[0008]

According to the present invention, the frequency setting signal indicating the frequency at which the group delay is generated is supplied from the transmission circuit to the filter for generating the group delay, and the amount of the group delay to be generated is set by the group delay amount. Directed by the circuit. The frequency of the frequency setting signal and the resistance value of the group delay amount setting resistor can be variably set. Therefore, when correcting the group delay characteristics appearing in the transmission characteristics of the receiver,
Since the frequency and amount of the group delay for that purpose can be variably set, in the present invention, it becomes possible to design the circuit prior to the measurement of the group delay characteristic to be corrected, and avoid or shorten the delay in the design process. be able to. Further, in the present invention, even if the group delay characteristic to be corrected changes due to aging or the like, this change can be dealt with without redesigning the circuit.

Further, in the present invention, the above-mentioned oscillation circuit is realized by a VCO, a PLL and a switch. VC
The signal obtained from O is divided by n in the PLL, and the reference signal is further divided by m in the PLL. PL
The L generates a voltage to be applied to the VCO by comparing the phase of the signal obtained by the frequency division by n and the signal obtained by the frequency division by m. Further, the frequency division ratio n is manually set by the switch. Therefore, in the present invention,
When the frequency division ratio n is changed by 1, the oscillation frequency of the VCO changes by 1 / m of the frequency of the reference signal. Therefore, by appropriately setting m, the frequency can be set more precisely than in the conventional case.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. The same or corresponding components as those of the conventional circuit shown in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 shows the configuration of a correction group delay generation circuit according to an embodiment of the present invention. In this embodiment, the resistor R3 for setting the amount of group delay generated by the group delay correction filter 2 is configured as a variable resistor. Therefore, in this embodiment, the amount of group delay to be generated in the group delay correction filter 2 can be changed by appropriately changing the value of the resistor R3. Further, since this change can be continuous, the amount of group delay to be generated can be set more accurately than in the conventional case.

Further, the clock oscillation circuit 1 in the present embodiment includes a dip switch 3, a PLL 4, a VCO 5 and 2.
It is composed of a frequency dividing circuit 6. VCO5 is PLL4
It oscillates at a frequency according to the DC voltage supplied from the circuit, and supplies the oscillated signal to the PLL 4 and the frequency dividing circuit 6. PL
L4 divides the reference clock externally supplied to its OSC terminal by m while dividing the signal supplied from the VCO 5 by n, and the signal obtained by the m division and the signal obtained by the n division. And are compared in phase. The PLL 4 generates a DC voltage based on the result of this phase comparison and applies it to the VCO 5. The frequency division ratio n is set by the DIP switch 3. The frequency divider circuit 2 divides the signal obtained by the VCO 5 by 2
By dividing the frequency, a clock with a duty ratio of 50% is generated, and this clock is supplied to the group delay correction filter 2 via the clock input terminal CLK.

Therefore, in this embodiment, the frequency division ratio n can be changed and the clock frequency can be changed by manually operating the dip switch 3 as appropriate. Here, the output of the VCO 5 is divided by 2 by the dividing circuit 6 and the reference clock is divided by m prior to the phase comparison. When the set value is changed by 1, the clock frequency changes by 1 / (2 × m) of the reference clock frequency. Therefore, by setting the frequency division ratio m applied to the reference clock to an appropriate value, the frequency of the clock can be adjusted with sufficient resolution although it is not continuous.

Therefore, according to this embodiment, it is necessary to measure the group delay characteristic in advance for the signal input to the group delay correction filter 2 from the terminal connected to the resistor R1, for example, the output signal of the receiver. Disappear. That is, it is possible to design the circuit in advance of the schedule of the group delay characteristic, so that the delay in the design process can be avoided or reduced. Further, even when the group delay characteristic of the signal to be corrected changes due to aging or the like, it is possible to deal with it promptly by changing and setting the values of the DIP switch 3 and the resistor R3. In addition, the value of the resistor R3 can be continuously changed, and the frequency of the clock can be changed with sufficient resolution. Therefore, the frequency and amount of the group delay should be precisely adjusted or set. It becomes possible to do.

[0015]

As described above, according to the present invention,
Since the frequency and resistance value of the frequency setting signal and the group delay amount setting resistor can be variably set, it is not necessary to measure the group delay characteristic prior to the circuit design, and the delay in the design process can be avoided or shortened. . Further, even when the delay characteristic changes due to aging or the like, the change can be quickly dealt with by adjusting the frequency absolute signal and the group delay amount setting resistance. Further, according to the present invention, since the above-mentioned oscillation circuit is realized by the VCO, the PLL and the switch, and the frequency division ratio n related to the output of the VCO is manually set by the switch, a group delay should be generated. Precise adjustment or setting can be performed for both the frequency and the amount thereof.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a correction group delay generation circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a correction group delay generation circuit according to a conventional example.

[Explanation of symbols]

1 clock oscillator circuit, 2 group delay correction filter, 3
DIP switch, 4PLL, 5 VCO, 62 divider circuit, R3 Group delay amount setting resistor.

Claims (2)

[Claims] 1. An oscillator circuit for generating a frequency setting signal whose frequency can be variably set, a group delay amount setting resistor whose resistance value can be variably set, and a group at a frequency corresponding to the frequency of the frequency setting signal. A correction that includes a filter that generates an amount of group delay according to the resistance value of the delay amount setting resistor, and that generates a group delay for correcting the group delay characteristic that appears in the transmission characteristics of the receiver, etc. Group delay generator circuit. 2. The correction group delay generation circuit according to claim 1, wherein the oscillation circuit oscillates at a frequency corresponding to an applied voltage, and a signal obtained from the VCO is divided by n (n:
V is obtained by phase-comparing a signal obtained by frequency-dividing the reference signal having a predetermined frequency and a signal obtained by dividing the reference signal having a predetermined frequency by m (m: natural number).
A correction group delay generation circuit comprising: a PLL for generating a voltage applied to CO; and a switch for manually setting a frequency division ratio n.