JPH08339995A - Formation of silicon oxide film and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To uniformize the thickness of a silicon oxide film by forming the silicon oxide film by the low pressure CVD method which uses silane gas at a specific temperature. CONSTITUTION: A method is provided to form a silicon oxide film by the low pressure CVD method which uses silane gas and dinitrogen monoxide gas as the major material. The silicon oxide film is deposited under the conditions where the deposition temperature is set at 800 deg.C or below, the gas pressure of the major material at 150Pa or below and the gas flow of the major material at 0.018l/min. or less under the standard conditions, which is per 1l reaction container at 25 deg.C at 1atm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention utilizes a method of forming a silicon oxide film used in a semiconductor device such as a VLSI by a low pressure CVD (chemical vapor deposition) method, and a method of forming the silicon oxide film. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art As a method for forming a silicon oxide film used in a semiconductor device such as a VLSI, a low pressure CVD method, an atmospheric pressure CVD method and a plasma CVD method are known.

When aluminum is used as the wiring material, the melting point of aluminum is as low as 660 ° C.
An atmospheric pressure CVD method or a plasma CVD method that can deposit a film at a low temperature near 0 ° C. is often used.

However, the silicon oxide film formed by the low pressure CVD method is superior in denseness and purity to the silicon oxide film formed by the atmospheric pressure CVD method or the plasma CVD method. Therefore, it is desirable to use a silicon oxide film formed by the low pressure CVD method for the gate electrode, the insulating film of the metal wiring layer, the sidewall of the gate electrode, and the like.

The silicon oxide film is deposited at a low temperature of about 400 ° C. by an atmospheric pressure CVD method or a plasma CVD method.
TO (Low Temperature Oxide)
Film and HTO (High Temperature) deposited at a high temperature of 700 to 850 ° C. by the low pressure CVD method.
Oxide) film. Therefore, in the following description, the silicon oxide film deposited by the atmospheric pressure CVD method or the plasma CVD method is called the LTO film, and the silicon oxide film deposited by the low pressure CVD method is called the HTO film.

When forming an HTO film, silane (SiH
₄ ) A method using gas and nitrous oxide (N ₂ O) gas as main raw materials, and tetraethoxysilicate (Si (OC ₂ H ₅ ) ₄ ; hereinafter referred to as TEOS) which is an organic gas and oxygen or ozone. A method using oxygen containing oxygen is known.

By the way, in recent years, further integration and miniaturization of VLSIs have been demanded from the viewpoint of speeding up of semiconductor devices and operation of low power consumption. In order to meet this demand, it is necessary to control the impurity diffusion profile more accurately in order to prevent deterioration of transistor performance and reliability. From such a viewpoint, it is necessary to lower the deposition temperature and shorten the deposition time in the step of forming the silicon oxide film by the low pressure CVD method.

According to the method using TEOS, 700 ° C.
Since a silicon oxide film can be deposited at a deposition temperature of about 6 to 7 nm / min at a deposition rate of about 6 to 7 nm / min, it is superior to the method using silane gas in terms of lowering the process temperature and mass productivity. For this reason, the low pressure CVD method using TEOS is often adopted in the manufacturing process of semiconductor devices such as VLSI.

[0009]

[Problems to be Solved by the Invention] However, TEO
The low pressure CVD method using S has some problems as described below.

First, the first problem is that the HTO film has a high shrinkage ratio, so that the HTO film may be cracked by heat treatment at about 900 ° C. for activation of impurities. Such cracks are a factor that causes peeling of the film and deterioration of the insulating property, which causes a reduction in yield.

The second problem is that a large amount of reaction by-products adhere to the inner wall of the exhaust pipe. This is because TEOS and T are used in the exhaust pipe whose temperature is lower than that of the reaction pipe.
This is because liquefaction and aggregation of the reaction intermediate generated by the thermal decomposition of EOS are likely to occur. The by-product adhering to the inner wall of the exhaust pipe causes dust and clogs of the exhaust pipe, so that the maintenance cycle becomes extremely short.

Thus, low pressure CVD using TEOS
The method has a problem in that the yield is greatly reduced and the device maintenance cost is increased.

Therefore, for the silicon oxide film formed in the manufacturing process of the semiconductor device such as the ultra LSI, the low pressure CVD method using silane gas is desired.

In this case, in order to improve the yield,
Although it is necessary to make the film thickness of the silicon oxide film uniform, the first problem is that the silicon oxide film obtained by the conventional low pressure CVD method using silane gas is not satisfactory in terms of film thickness uniformity. .

Further, since the low-pressure CVD method using silane gas has a slow deposition rate, the conventional deposition temperature is 82.
Although 0 ° C. or higher is adopted, if the deposition temperature is 820 ° C. or higher, the impurity diffusion profile cannot be accurately controlled. Therefore, in order to accurately control the diffusion profile of impurities, it is necessary to form a silicon oxide film at a temperature of 800 ° C. or lower and in a short deposition time. However, conventional low pressure CVD using silane gas
If the deposition temperature is set to 800 ° C. or lower in the method, the deposition time is inevitably lengthened, and thus the second problem is that the diffusion profile of impurities cannot be accurately controlled.

In view of the above, the first object of the present invention is to make the thickness of the obtained silicon oxide film uniform in the method of forming the silicon oxide film by the low pressure CVD method using silane gas. The second object is to enable accurate control of the diffusion of impurities.

[0017]

In order to achieve the first object, the means for solving the problems according to the invention of claim 1 is to form a silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main materials. Targeting the forming method, the deposition conditions of the silicon oxide film are 0.018 liter / min or less under the standard conditions that the deposition temperature is 800 ° C. or less and the gas flow rate of the main raw material is 25 ° C. 1 atm per liter of the reaction vessel. It is set to become.

In the structure of claim 1, the deposition temperature is 80
When the temperature is 0 ° C. and the gas flow rate of the main raw material is 0.018 liter / min under the standard conditions per 1 liter of the reaction vessel, the uniformity of the film thickness of the obtained silicon oxide film is the limit of the allowable range. As the deposition temperature becomes lower than 800 ° C., the frequency of collision between reaction products (deposits) decreases, so that the uniformity of the film thickness of the silicon oxide film is improved. If so, the uniformity of the film thickness of the silicon oxide film falls within the allowable range. Further, when the gas flow rate of the main raw material is lower than 0.018 liter / min under the standard conditions per 1 liter of the reaction vessel, the gas flow in the reaction vessel becomes more laminar and the gas vortex is generated between the wafers. Is less likely to occur, the uniformity of the film thickness of the silicon oxide film deposited on the wafer is improved. Therefore, if the gas flow rate of the main source gas is 0.018 liter / min or less, the film thickness of the silicon oxide film Uniformity is within acceptable limits.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the deposition condition of the silicon oxide film is set such that the gas pressure of the main raw material is set to 170 Pa or less. .

According to a third aspect of the present invention, in addition to the configuration of the first aspect, the deposition condition of the silicon oxide film is set so that the gas pressure of the main raw material is set to 125 Pa or less. .

A solution means taken by the invention of claim 4 is directed to a method for forming a silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials. Is 800 ° C. or less and the gas pressure of the main raw material is 100 Pa or more.

According to the structure of claim 4, the deposition temperature is 800
Since the gas pressure of the main raw material is 100 Pa or more at a temperature of ℃ or less, the diffusion of impurities can be surely suppressed, and the effective gate length that is usually adopted in the VLSI manufacturing process becomes 80% or more of the designed gate length. Such criteria can be satisfied. Since the effective gate length is most sensitive to the adverse effect due to impurity diffusion in the VLSI manufacturing process, if the criteria that the effective gate length is 80% or more of the designed gate length are satisfied, the silicon oxide film will flash. It can be sufficiently adapted even when used as an insulating film such as an insulating film between the control gate and the floating gate of the memory.

A fifth aspect of the present invention is the structure of the fourth aspect, wherein the deposition temperature is set to 780 ° C. or higher and 800 ° C. or lower, and the gas pressure of the main raw material is set to 100 Pa or higher. It is something to add.

According to a sixth aspect of the invention, in the structure of the fourth aspect, the deposition temperature is set to 740 ° C. or higher and 800 ° C. or lower, and the gas pressure of the main raw material is set to 125 Pa or higher. It is something to add.

According to a seventh aspect of the present invention, there is provided a solving means for forming a gate electrode on a semiconductor substrate on which a low concentration impurity region is formed, and a side surface of the gate electrode on the semiconductor substrate. A side wall forming step of forming a side wall made of a silicon oxide film on the semiconductor substrate; and a step of forming a high concentration impurity region by implanting impurities into the semiconductor substrate by using the gate electrode and the side wall as a mask. Based on a manufacturing method, the sidewall forming step is performed by a low pressure CVD method using the silane gas and the nitrous oxide gas as main raw materials for the silicon oxide film at a deposition temperature of 800 ° C. or less and a gas pressure of the main raw material of The configuration includes a step of forming under a deposition condition such that the pressure becomes 100 Pa or more.

According to the structure of claim 7, by the same effect as in claim 4, in the step of depositing the silicon oxide film in the sidewall forming step, the diffusion of impurities in the low concentration impurity region formed in the semiconductor substrate is suppressed. You can

According to an eighth aspect of the present invention, a means for solving the problems is to form a wiring layer on a semiconductor substrate doped with impurities, and to form an insulating film made of a silicon oxide film on the wiring layer. On the premise of a method for manufacturing a semiconductor device including an insulating film depositing step of depositing, the insulating film depositing step comprises depositing the silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials. Is 800 ° C
The following is a configuration including a step of forming under a deposition condition such that the gas pressure of the main raw material is 100 Pa or more.

According to the structure of claim 8, due to the same effect as in claim 4, in the step of forming the insulating layer made of the silicon oxide film on the wiring layer, the diffusion of impurities doped in the semiconductor substrate is suppressed. be able to.

According to a ninth aspect of the present invention, a means for solving the problems is an insulating film deposition step of depositing an insulating film made of a silicon oxide film on a semiconductor substrate doped with impurities, and a conductive film on the insulating film. Presuming a method of manufacturing a semiconductor device, comprising: a conductive film deposition step of depositing a conductive film; and an etching step of etching the conductive film using the insulating film as an etching stopper. A structure including a step of forming an oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials under deposition conditions such that the deposition temperature is 800 ° C. or lower and the gas pressure of the main raw material is 100 Pa or higher. It is what

According to the structure of claim 9, the semiconductor substrate is doped with the same effect as in claim 4 in the step of forming the insulating layer made of the silicon oxide film which serves as an etching stopper when etching the conductive film. The diffusion of impurities can be suppressed.

According to a tenth aspect of the present invention, there is provided a first conductive film deposition step of depositing a first conductive film to be a floating gate on a semiconductor substrate doped with impurities. An insulating film deposition step of depositing an insulating film made of a silicon oxide film on the first conductive film; and a second conductive film deposition of depositing a second conductive film to serve as a control gate on the insulating film. And a deposition temperature of 800 ° C. or less by the low pressure CVD method using silane gas and nitrous oxide gas as main raw materials in the insulating film deposition step. ,
It is configured to include a step of forming under a deposition condition such that the gas pressure of the main raw material is 100 Pa or more.

According to the structure of the tenth aspect, due to the same effect as the fourth aspect, in the step of forming the insulating layer made of the silicon oxide film between the floating gate and the control gate, the impurity doped in the semiconductor substrate is removed. Diffusion can be suppressed. Further, when the first conductive film is made of polysilicon, the grain growth of polysilicon can be suppressed in the step of depositing the silicon oxide film.
Breakage of the insulating film in contact with the first conductive film and mechanical stress applied to the insulating film can be reduced.

According to an eleventh aspect of the present invention, there is provided a means for solving the problems, comprising a first conductive film depositing step of depositing a first conductive film to be a floating gate on a semiconductor substrate doped with impurities, and the first conductive film depositing step. An insulating film deposition step of depositing an insulating film made of a silicon oxide film on the first conductive film; and a second conductive film deposition of depositing a second conductive film to serve as a control gate on the insulating film. And a deposition temperature of 800 ° C. or less by the low pressure CVD method using silane gas and nitrous oxide gas as main raw materials in the insulating film deposition step. ,
The gas flow rate of the main raw material is 25 ° C. per liter of the reaction vessel
The structure includes a step of forming under a deposition condition such that the pressure is 0.018 l / min or less under a standard condition of 1 atm.

According to the eleventh aspect, it is possible to suppress the variation in the film thickness of the insulating layer formed of the silicon oxide film formed between the floating gate and the control gate by the same operation as the first aspect.

The solution of the invention of claim 12 is I
Semiconductor device including an insulating film deposition step of depositing an insulating film of a silicon oxide film on a TO substrate, and a conductive film forming step of forming a conductive film to be source / drain regions on the insulating film In the insulating film deposition step, the silicon oxide film is deposited by a low-pressure CVD method using silane gas and nitrous oxide gas as main raw materials at a deposition temperature of 800 ° C. or lower and the main raw material gas is used. Pressure is 10
The structure includes a step of forming under a deposition condition such that the pressure becomes 0 Pa or more.

According to the twelfth aspect, it is possible to reduce thermal damage to the ITO substrate in the step of depositing the insulating film made of the silicon oxide film on the ITO substrate.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION A low pressure CVD apparatus used in a low pressure CVD method using silane gas and nitrous oxide gas will be described below with reference to FIG. 1. FIG. 1 shows the configuration of the low pressure CVD apparatus. In FIG. 1, 1 is a wafer support board that holds a plurality of wafers in a horizontal state, 2 is an inner tube as a reaction container that houses the wafer support board 1, 3 is an outer tube that covers the inner tube 2, and 4 is an outer tube 3. A heater provided on the outer side of the gas guide tube 5, a gas introduction tube for introducing the raw material gas into the inner tube 2, 6 a mass flow controller for controlling the flow rate of the gas introduced from the gas introduction tube 5,
Reference numeral 7 is an exhaust means for discharging gas or the like from the inner tube 2, 8 is an external thermocouple, 9 is an internal thermocouple, 10 is a pressure gauge,
Reference numeral 11 is a control means.

Silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O), which are raw material gases, are introduced into the inner tube 2 through the gas introducing pipe 5, and the wafer supporting board 1
A silicon oxide film is formed on the wafer held by.

The raw material gas in the inner tube 2 and nitrogen, water vapor, hydrogen, etc., which are the products of the reaction, are discharged from the exhaust means 7 through the outer tube 3.

The temperature inside the inner tube 2, the gas pressure,
The gas flow rate is 8 for external thermocouple, 9 for internal thermocouple, and 10 for pressure gauge.
And is measured by the mass flow controller 6. The deviation between the measured value and the set value is compared by the control means 11, and the power input to the heater 4, the exhaust amount of the exhaust means 7, the valve opening degree of the mass flow controller 6, etc. are controlled by the control means 11 so as to maintain the set value. Controlled by.

A method of forming a silicon oxide film by the low pressure CVD method according to the first embodiment of the present invention will be described below.

The first embodiment is directed to a method for forming a silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials. The deposition conditions for the silicon oxide film are as follows: The film thickness of the silicon oxide film is made uniform by setting the gas flow rate of the main raw material to be 0.018 liter / min or less under standard conditions of 25 ° C. and 1 atmosphere per liter of the reaction vessel. .

FIG. 2 shows the relationship between the gas pressure (Pa) in the reaction vessel and the film thickness uniformity (%) using the flow rate of the main raw material gas as a parameter. In FIG. 2, ◯ indicates the main raw material gas. Indicates a flow rate of 0.018 liters / minute under standard conditions of 25 ° C./atm per liter of reaction vessel, and ● indicates that the main raw material gas flow rate is 0. 045 liters /
It shows the case of minutes. In addition, ◯ and ● are the cases where the deposition temperature is 800 ° C. As for the film thickness uniformity of the silicon oxide film in a semiconductor device such as a VLSI, 4% or less is an allowable range and 3% or less is ideal, and each is shown by a dashed line.

As can be seen from FIG. 2, when the gas pressure decreases, the film thickness uniformity decreases. It is considered that this is because when the gas pressure is reduced, the number of collisions of the particles of the main raw material gas in the reaction vessel is reduced.

As can be seen from the comparison between the solid line connecting the circles and the solid line connecting the black circles in FIG. 2, when the gas pressures are the same,
When the gas flow rate increases, the uniformity of the film thickness of the silicon oxide film deteriorates. It is considered that this is because when the flow rate of gas increases, the state of gas flowing between the wafers held on the wafer support board 1 shown in FIG. 1 changes from laminar flow to turbulent flow. In other words, it is considered that when the gas flow becomes turbulent, a gas vortex occurs between the wafers, and the film thickness of the silicon oxide film deposited on the wafer is not uniform due to the vortex. The deposition rate of the silicon oxide film has little relation to the increase and decrease of the gas flow rate, and depends on the gas pressure and the deposition temperature.

As can be seen from FIG. 2, the gas flow rate of the main raw material is 0.01 per liter of the reaction vessel under standard conditions.
When it is 8 liters, the uniformity of the film thickness is within the allowable range of 4% or less when the gas pressure is 170 Pa or less, and the film thickness uniformity becomes 3% or less when the gas pressure is 125 Pa or less. Become.

Note that FIG. 2 shows the case where the deposition temperature is 800 ° C., but the frequency of collision between reaction products (deposits) decreases as the deposition temperature decreases, so the film thickness The uniformity is improved. Therefore, if the gas flow rate is limited as described above, it is apparent that the uniformity of the film thickness is ensured in the temperature range where the deposition temperature is 800 ° C. or lower.

A method of forming a silicon oxide film by the low pressure CVD method according to the second embodiment of the present invention will be described below.

The second embodiment is intended for a method of forming a silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main materials, and the deposition conditions of the silicon oxide film are as follows: The silicon oxide film is formed while suppressing the diffusion of impurities by setting the gas pressure of the main raw material to 100 Pa or less.

In the second embodiment, the effective gate length: L _eff is the design gate length: L, which is usually adopted in the manufacturing process of the field effect transistor having the LDD structure.
_The basic policy is to suppress the diffusion of impurities so that the standard of 80% or more of the _design is satisfied. In the manufacturing process of semiconductor devices such as VLSI, LD
The strictest criterion is that the effective gate length of a field-effect transistor having a D structure is 80% or more of the designed gate length. If this criterion is met, the silicon oxide film and the silicon oxide film float with the control gate of the flash memory. It is also sufficiently suitable for use as another insulating film such as an insulating film between the gate and the like.

Since the effective gate length / designed gate length is inversely proportional to the product of the diffusion of impurities and the deposition time,
It can be said that (ease of impurity diffusion) × (deposition time) is proportional to the amount of impurity diffusion.

Therefore, when the deposition condition of the silicon oxide film is set so that L _eff ≧ 0.24 μm when L _design = 0.30 μm, the impurity diffusion suppression condition required in the VLSI manufacturing process is set. Will be satisfied.

FIG. 3 shows the relationship between the deposition temperature (° C.) and the deposition rate (deposition rate: nm / min) such that L _eff = 0.24 μm when L _design = 0.30 μm. . Hatching indicates a region where L _eff ≧ 0.24 μm when L _design = 0.30 μm. When the silicon oxide film is deposited in the hatched region, the effective gate length becomes 80% or more of the design gate length. Become.

FIG. 4 shows the relationship between the deposition temperature (° C.) and the deposition rate (nm / min) using the gas pressure of the main raw material as a parameter, and shows the gas pressures of 125 Pa, 100 Pa and 73 Pa. There is. The dashed-dotted line in FIG. 4 is the same as the solid line in FIG. 3, and in FIG. 4, hatching is omitted for convenience of illustration.

As can be seen from FIG. 4, that is, since the solid line connecting the circles when the gas pressure is 100 Pa is located above and in the vicinity of the alternate long and short dash line, the deposition temperature is 800 ° C.
In the following cases, in order to secure the effective gate length, it is necessary to set the gas pressure to 100 Pa or more. In addition, the deposition temperature is 780 to 800 ° C. and the gas pressure is 100 Pa or more, or the deposition temperature is 740 to 740.
It can also be seen that if the temperature is 800 ° C. and the gas pressure is 125 Pa or higher, the effective gate length can always be ensured because it is located above the one-dot chain line, that is, in the hatched region in FIG.

The evaluation tests conducted for evaluating the present invention will be described below. As an example embodying the first and second embodiments, a deposition temperature: 800 ° C., a gas pressure: 125 Pa, a raw material gas flow rate: 1 SLM (St
and (Litter Minute, flow rate of standard condition of 25 ° C. and 1 atm per liter of reaction vessel) were used, and as a comparative example, deposition temperature: 840 ° C., gas pressure: 73 Pa, raw material gas flow rate: 1 SLM. Using.

According to the above embodiment, the deposition temperature is 800 ° C.
Even below, it was possible to secure a deposition rate equal to or higher than that of the comparative example in which the deposition temperature was 840 ° C.

In addition, the number of dust particles on the HTO film deposited by the above-mentioned example and comparative example was 6 inches (about 130 c).
was measured using a sample of m ^2), 0 Both.
10 to 30 dust particles with a diameter of 3 μm or more,
It has been confirmed that the present invention does not increase the number of dusts.

Further, the refractive index and the etching rate of wet etching of the HTO film deposited according to the above-mentioned Examples and Comparative Examples were measured. Both have refractive indices of 1.45 to 1.
It was 455. The etching rate is at room temperature
It was defined as the difference in film thickness between the HTO film before and after etching in a hydrofluoric acid solution diluted 20 times with ammonium fluoride for 1 minute. The etching rate was 55.5 nm / min in the comparative example and 54.8 nm / min in the example. From this, it was confirmed that the film quality of the HTO film was comparable between the comparative example and the example.

Further, when the step coverage of the HTO film deposited according to the above-mentioned Examples and Comparative Examples was measured,
Both of the step coverages were 95 to 100%, and the step coverage was not deteriorated by the above embodiment.

Each method of manufacturing a semiconductor device using the method of forming a silicon oxide film according to the first embodiment or the second embodiment will be described below.

5 to 9 show each step of the first manufacturing method of the semiconductor device.

First, as shown in FIG. 5A, a twin well region 13 and an element isolation region 14 are formed on a semiconductor substrate 12.
After the silicon oxide film 15 and the silicon oxide film 15 are sequentially formed, a polysilicon film is deposited on the silicon oxide film 15. Then, a trichlorophosphoric acid (POCl ₃ ) gas is caused to flow in the diffusion furnace to introduce phosphorus into the polysilicon film to form the N-type polysilicon film 1
After forming 6, the first HTO film 17 is deposited on the N-type polysilicon film 16.

Next, the silicon oxide film 15, the N-type polysilicon film 16 and the first HTO film 17 are subjected to photolithography and dry etching to obtain the structure shown in FIG.
As shown in (b), after forming the under-gate insulating film 15A, the gate electrode 16A, and the over-gate insulating film 17A, phosphorus is ion-implanted into the semiconductor substrate 12 to form an N ⁻ region.

Next, as shown in FIG. 5C, the first
After the second HTO film 18 is deposited by using the method for forming a silicon oxide film according to the first embodiment or the second embodiment, the second HTO film 18 is etched back, and the second HTO film 18 shown in FIG. ), The gate electrode sidewall 18
After forming A, arsenic and boron are ion-implanted into the semiconductor substrate 12 to form the source / drain regions 19.

Next, as shown in FIG. 6B, the third H
TO film 20, polysilicon film 21 into which impurities are introduced,
Tungsten silicide film 22 and fourth HTO film 23
Are sequentially deposited, and then the polysilicon film 21, the tungsten silicide film 22, and the fourth HTO film 23 are subjected to photolithography and dry etching, so that as shown in FIG. A polycide wiring 24 made of a tungsten silicide film 22 and an on-wiring insulating film 23A made of a fourth HTO film 23 are formed. In this case, the third HTO film 20 and the fourth HTO film 23 are the same as those in the first embodiment or the second embodiment.
Deposition is performed using the method for forming a silicon oxide film according to the above embodiment.

Next, as shown in FIG. 7B, the first
After depositing the fifth HTO film 25 by using the method for forming a silicon oxide film according to the embodiment or the second embodiment, the fifth HTO film 25 is etched back,
As shown in FIG. 8A, the wiring sidewall 25A is formed.

Next, as shown in FIG. 8B, after forming a planarized first interlayer insulating film 26, a contact hole is opened in the first interlayer insulating film 26. Then, titanium 27, titanium nitride 28, and tungsten 29 are sequentially deposited in the contact hole to form a contact, and then a first aluminum wiring 30 is formed.

Next, as shown in FIG. 9, after the planarized second interlayer insulating film 31 is formed, a contact hole is opened in the second interlayer insulating film 31. Then, after forming the second aluminum wiring 32, a phosphorus glass (PSG) film 33 and a silicon nitride film 34 are sequentially deposited by a plasma CVD method to form a passivation film. Then, an opening 35 for an electrode pad is opened in the phosphor glass film 33 and the silicon nitride film 34.

The second to fifth HTO films 18, 20,
When depositing 23 and 25, impurities in the N ⁻ layer and the source / drain regions 19 formed in the semiconductor substrate 12 diffuse in the surface direction of the substrate. This reduces the effective channel length (L _eff ). In this case, according to the conventional method, the short channel effect becomes remarkable and the device performance is deteriorated. However, according to the method of the present invention, the second to fifth HTOs are used.
Since the deposition temperature of the films 18, 20, 23, 25 is low, it is possible to suppress the diffusion of impurities, and thus it is possible to suppress the above-mentioned short channel effect.

In the first method of manufacturing the semiconductor device, the third HTO film 20 and the fifth HTO film 25 are used.
Instead of this, another silicide film, such as a titanium silicide film, may be deposited as a protective film.

FIG. 10 shows the degree of decrease in the effective channel length (ΔL _eff ) when the HTO film was deposited under the conditions of the above-mentioned Examples and Comparative Examples. Where ΔL _eff =
(Decrease of L _eff produced in the manufacturing process in the case of depositing a HTO film under the conditions of Comparative Example) - in (decrease of L _eff produced in the manufacturing process in the case of depositing a HTO film under the conditions of Example) is there.

Degree of decrease in effective channel length: ΔL
_eff is 0.05 in the case of an N-channel transistor.
˜0.10 μm, and in the case of a P-channel transistor, it was 0.06 to 0.12 μm. Therefore, it is possible to suppress the decrease of the effective channel length: L _eff of the N-channel transistor at the maximum of about 0.1 μm and the P-channel transistor at the maximum of about 0.12 μm.

As described above, according to the first and second embodiments, the effect of preventing the reduction of the effective channel length: L _eff is great especially in the transistor of 0.5 μm rule or less. Further, by depositing the HTO film under the conditions shown in the first and second embodiments, it is possible to suppress excessive thermal diffusion of impurities, so that improvement in transistor performance can be expected and deterioration of element isolation characteristics can be expected. Can also be prevented.

11 to 13 show a flash EEPRO.
M (Electrical Erasable Pro)
Gramable Read Only Memor
The respective steps of the second manufacturing method of the semiconductor device consisting of y) are shown.

First, as shown in FIG. 11A, an element isolation region 44 and a silicon oxide film 45 are formed on a semiconductor substrate 42.
Are sequentially formed, a polysilicon film is deposited on the silicon oxide film 45. After that, a trichlorophosphoric acid (POCl ₃ ) gas is flown in the diffusion furnace to introduce phosphorus into the polysilicon film to form the first N-type polysilicon film 46.

Next, as shown in FIG. 11B, the method for forming the silicon oxide film according to the first embodiment or the second embodiment on the first N-type polysilicon film 46 is performed. The first HTO film 47 is deposited to a thickness of 10 to 25 nm by using the above, and then a second N-type polysilicon film 48 doped with phosphorus is deposited on the first HTO film 47.

Next, as shown in FIG. 11C, with respect to the silicon oxide film 45, the first N-type polysilicon film 46, the first HTO film 47 and the second N-type polysilicon film 48. Photolithography and dry etching are performed to form an under-gate insulating film 45A, a floating gate electrode 46A, an inter-gate insulating film 47A and a control gate electrode 48A.

Next, as shown in FIG. 12A, phosphorus is ion-implanted into the semiconductor substrate 42 to form an N ⁻ region.
Then, after depositing a second HTO film using the method for forming a silicon oxide film according to the first embodiment or the second embodiment, the second HTO film is etched back to perform gate back. The electrode sidewall 49 is formed. After that, arsenic and boron are ion-implanted into the semiconductor substrate 42 to form the source / drain regions 50.

Next, as shown in FIG. 12 (b), after forming a planarized first interlayer insulating film 51, a contact hole is opened in the first interlayer insulating film 51. After that, titanium 52, titanium nitride 53, and tungsten 54 are sequentially deposited in the contact hole to form a contact, and then a first aluminum wiring 55 is formed.

Next, as shown in FIG. 13, after forming the planarized second interlayer insulating film 56, a contact hole is opened in the second interlayer insulating film 56. Then, after forming the second aluminum wiring 57, a phosphorus glass (PSG) film 58 and a silicon nitride film 59 are sequentially deposited by a plasma CVD method to form a passivation film.
Then, an opening 60 for an electrode pad is opened in the phosphorus glass film 58 and the silicon nitride film 59.

Since the gas flow rate for depositing the first HTO film 47 is small, the film thickness of the inter-gate insulating film 47A becomes uniform, so that the variation in the performance of the flash EEPROM can be reduced. In addition, since the deposition temperature of the second HTO film that becomes the gate electrode sidewall 49 is low,
The diffusion of impurities in the N ⁻ layer and the source / drain region 50 can be suppressed, and the control gate electrode 4 can be formed.
6A suppresses excessive grain growth, and the inter-gate insulating film 4 is formed.
It is possible to reduce defects occurring in 7A and mechanical stress applied to the under-gate insulating film 45A.

Further, as compared with the case where a silicon nitride film or the like is formed on the first N-type polysilicon film 46, the interface state density can be reduced and leakage between the gate electrodes can be prevented, so that data retention The characteristics do not deteriorate.

In the second method of manufacturing a semiconductor device described above, the silicon oxide film 4 to be the under-gate insulating film 45A is formed.
Instead of 5, ONO (Oxide-Nitride-O
If the xide) film is used, the device reliability and data retention characteristics are further improved.

14 and 15 show TFTs (Thin).
It shows each step of the third manufacturing method of the semiconductor device made of the Film Transistor).

First, as shown in FIG. 14A, ITO is used.
A gate electrode 72 made of high melting point metal or polysilicon doped with N-type impurities is formed on a substrate 71.

Next, as shown in FIG. 14B, an HTO film 73 is deposited using the method for forming a silicon oxide film according to the first embodiment or the second embodiment. afterwards,
After depositing an amorphous silicon film on the HTO film 73, the amorphous silicon film is irradiated with an excimer laser to form a polysilicon film 74 having a grain size of several μm or more.

Next, as shown in FIG. 14C, after forming a first resist pattern 75 on the polysilicon film 74, dry etching is performed to form the polysilicon film 7.
4 is patterned to form a patterned polysilicon film 74A.

Next, as shown in FIG. 15A, after forming a second resist pattern 76 on the patterned polysilicon film 74A, patterning is performed using the second resist pattern 76 as a mask. Polysilicon film 7
Ions are implanted into 4A to form source / drain regions 77.

Next, as shown in FIG. 15B, after depositing a metal film over the entire surface, patterning is performed on the metal film to form source / drain electrodes 78.

Next, as shown in FIG. 15C, after depositing the first passivation film 79 on the entire surface, the passivation film 79 is subjected to hydrogenation treatment.

Next, after forming a contact on the first passivation film 79, an aluminum wiring connecting to the contact is formed, and then a second passivation film (not shown) is formed and then the second passivation film is formed. To form an opening.

According to the third method of manufacturing a semiconductor device, the HTO film 73 is deposited by using the method of forming a silicon oxide film according to the first and second embodiments.
Since it is possible to suppress variations in the film thickness of the ITO substrate, it is possible to stabilize the gate current and reduce heat damage to the ITO substrate 71. As a result, TFTs of excellent quality can be manufactured with high yield.

[0094]

According to the method for forming a silicon oxide film of the first aspect of the present invention, the conditions for depositing the silicon oxide film are as follows: the deposition temperature is 800 ° C. or less, and the gas flow rate of the main raw material is the reaction vessel 1.
0.018 liters / liter under standard conditions
Since it is set to be not more than the minute, the uniformity of the film thickness of the obtained silicon oxide film is improved.

According to the method for forming a silicon oxide film of the second aspect of the present invention, since the deposition conditions for the silicon oxide film are set so that the gas pressure of the main raw material is 170 Pa or less, the uniformity of the obtained silicon oxide film is high. Is within the allowable range of 4% or less.

According to the method for forming a silicon oxide film according to the third aspect of the present invention, the deposition conditions for the silicon oxide film are set so that the gas pressure of the main raw material is 125 Pa or less. Is an ideal state of 3% or less.

According to the method for forming a silicon oxide film of the fourth aspect of the present invention, the deposition conditions for the silicon oxide film are set so that the deposition temperature is 800 ° C. or lower and the gas pressure of the main raw material is 100 Pa or higher. Therefore, the silicon oxide film can be deposited while surely suppressing the diffusion of impurities.

According to the method for forming a silicon oxide film of the fifth aspect, the deposition temperature is 780 ° C. or higher and 800 ° C.
In addition to setting below, the gas pressure of the main raw material is 100 Pa.
Since the above settings are made, the effective gate length / designed gate length is 8
The diffusion of impurities can be suppressed so as to be 0% or less.

According to the method for forming a silicon oxide film of the sixth aspect, the deposition temperature is 740 ° C. or higher and 800 ° C.
Set the following and set the gas pressure of the main raw material to 125 Pa.
Since the above settings are made, the effective gate length / designed gate length is 8
The diffusion of impurities can be suppressed so as to be 0% or less.

Therefore, according to the inventions of claims 1 to 6, the yield of semiconductor devices can be improved without modifying the low pressure CVD apparatus.

According to the semiconductor device manufacturing method of the seventh aspect of the present invention, in the sidewall forming step, the silicon oxide film is deposited such that the deposition temperature is 800 ° C. or lower and the gas pressure of the main raw material is 100 Pa or higher. Since it is formed under the conditions, diffusion of impurities in the low concentration impurity region formed in the semiconductor substrate can be suppressed in the step of depositing the silicon oxide film, so that the characteristics of the semiconductor device having the LDD structure can be improved.

According to the semiconductor device manufacturing method of the present invention, the deposition temperature of the silicon acid on the wiring layer is 80
Since the formation is performed under the deposition conditions such that the gas pressure of the main raw material is 100 Pa or higher at 0 ° C. or lower, diffusion of impurities doped in the semiconductor substrate can be suppressed in the step of depositing the silicon oxide film. The characteristics can be improved.

In the method of manufacturing a semiconductor device according to the ninth aspect of the present invention, the deposition temperature of the silicon oxide film, which serves as an etching stopper when the conductive film is etched, is 800 ° C.
In the following, since the formation is performed under the deposition conditions such that the gas pressure of the main raw material is 100 Pa or more, the diffusion of impurities doped in the semiconductor substrate can be suppressed in the step of depositing the silicon oxide film. Can be improved.

According to the semiconductor device manufacturing method of the tenth aspect of the present invention, the deposition temperature of the silicon oxide film between the floating gate and the control gate is 800 ° C. or less, and the gas pressure of the main raw material is 100 Pa or more. Since the silicon oxide film is formed under such a deposition condition, diffusion of impurities doped in the semiconductor substrate can be suppressed in the step of depositing the silicon oxide film, so that the characteristics of a semiconductor device such as a flash memory can be improved. Further, when the floating gate is made of a polysilicon film, it is possible to reduce the defects of the insulating film in contact with the floating gate and the mechanical stress applied to the insulating film, thus improving the characteristics of the semiconductor device such as a flash memory. be able to.

According to the semiconductor device manufacturing method of the eleventh aspect of the present invention, the deposition temperature of the silicon oxide film of the floating gate and the control gate is 800 ° C. or less, and the gas flow rate of the main raw material is 25 per liter of the reaction vessel. ℃
Since the film is formed under a deposition condition of 0.018 liter / min or less under the standard condition of 1 atm, it is possible to suppress the variation in the film thickness of the insulating layer between the floating gate and the control gate. The characteristics of the device can be improved.

According to the method of manufacturing a semiconductor device according to the twelfth aspect of the present invention, the thermal damage to the ITO substrate can be reduced in the step of depositing the insulating film made of the silicon oxide film on the ITO substrate. The characteristics of the TFT formed above can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a low pressure CVD apparatus used in a method for forming a silicon oxide film according to each embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a gas pressure in a reaction container and a film thickness uniformity with a flow rate of a main raw material gas as a parameter.

FIG. 3 is a diagram showing the relationship between the deposition temperature and the deposition rate such that the effective gate length: L _eff = 0.24 μm when the design gate length: L _design = 0.30 μm.

FIG. 4 is a diagram showing a relationship between a deposition temperature and a deposition rate using a gas pressure of a main raw material as a parameter.

5A to 5C are cross-sectional views showing each step of the first method for manufacturing a semiconductor device according to the present invention.

6A and 6B are cross-sectional views showing each step of the first method for manufacturing a semiconductor device according to the present invention.

7A and 7B are cross-sectional views showing each step of the first method for manufacturing a semiconductor device according to the present invention.

8A and 8B are cross-sectional views showing each step of the first manufacturing method of the semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view showing a step of the first manufacturing method of the semiconductor device according to the present invention.

FIG. 10 is a diagram showing the degree of reduction in effective channel length when an HTO film was deposited under the conditions of Examples and Comparative Examples to evaluate the present invention.

11A to 11C are cross-sectional views showing each step of the second manufacturing method of the semiconductor device according to the present invention.

12A and 12B are cross-sectional views showing each step of the second method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view showing each step of the second manufacturing method of the semiconductor device according to the present invention.

14A to 14C are cross-sectional views showing the steps of a third method of manufacturing a semiconductor device according to the present invention.

15A to 15C are cross-sectional views showing the steps of a third method of manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

 1 Wafer Support Board 2 Inner Tube (Reaction Vessel) 3 Outer Tube 4 Heater 5 Gas Inlet Tube 6 Mass Flow Controller 7 Exhaust Means 8 External Thermocouple 9 Internal Thermocouple 10 Pressure Gauge 11 Control Means 12 Semiconductor Substrate 13 Twinwell Area 14 Element Separation Layer 15 Silicon oxide film 16 N-type polysilicon film 17 First HTO film 18 Second HTO film 18A Gate electrode sidewall 19 Source / drain region 20 Third HTO film 21 Polysilicon film 22 Tungsten silicide film 22 23 Second 4 HTO film 23A Wiring upper electrode 24 Polycide wiring 25 Fifth HTO film 25A Wiring sidewall 26 First interlayer insulating film 27 Titanium 28 Titanium nitride 29 Tungsten 30 First aluminum wiring 31 Second interlayer insulating film 32 Second Aluminum Wiring 33 Phosphorus Glass Film 34 Silicon Nitride Film 35 Opening 42 Semiconductor Substrate 44 Element Isolation Area 45 Silicon Oxide Film 45A Under Gate Insulation Film 46 First N-type Polysilicon Film 46A Floating Gate Electrode 47 First HTO film 47A Inter-gate insulating film 48 Second N-type polysilicon film 48A Control gate electrode 49 Gate electrode sidewall 50 Source / drain region 51 First interlayer insulating film 52 Titanium 53 Titanium nitride 54 Tungsten 55 First aluminum Wiring 56 Second interlayer insulating film 57 Second aluminum wiring 58 Phosphor glass film 59 Silicon nitride film 60 Opening 71 ITO substrate 72 Gate electrode 73 HTO film 74 Polysilicon film 74A Patterned polysilicon film 75 First resist pattern 76 Second resist pattern 77 Source / drain region 78 Source / drain electrode 79 First passivation film

Claims (12)

[Claims] 1. A method for forming a silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main materials, wherein the deposition condition of the silicon oxide film is a deposition temperature of 80.
The silicon oxide film is characterized in that the gas flow rate of the main raw material is set to 0.018 liters / minute or less per 1 liter of the reaction vessel at 0 ° C. or less under standard conditions of 25 ° C. and 1 atmosphere. Forming method. 2. The method for forming a silicon oxide film according to claim 1, wherein the deposition conditions for the silicon oxide film are set such that the gas pressure of the main raw material is 170 Pa or less. 3. The method for forming a silicon oxide film according to claim 1, wherein the deposition conditions for the silicon oxide film are set so that the gas pressure of the main raw material is 125 Pa or less. 4. A method for forming a silicon oxide film by a low pressure CVD method using silane gas and nitrous oxide gas as main materials, wherein the deposition condition of the silicon oxide film is a deposition temperature of 80.
A method for forming a silicon oxide film, wherein the gas pressure of the main raw material is set to 100 Pa or higher at 0 ° C. or lower. 5. The deposition temperature is 780 ° C. or higher and 800
The gas pressure of the main raw material is set to 10 ° C or lower.
5. It is set to 0 Pa or more, and
A method for forming a silicon oxide film according to item 1. 6. The deposition temperature is 740 ° C. or higher and 800
The gas pressure of the main raw material is 12
5. The pressure is set to 5 Pa or higher, and
A method for forming a silicon oxide film according to item 1. 7. A gate electrode forming step of forming a gate electrode on a semiconductor substrate on which a low concentration impurity region is formed,
A sidewall forming step of forming a sidewall made of a silicon oxide film on a side surface of the gate electrode on the semiconductor substrate, and a high concentration impurity region by implanting impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask In the method for manufacturing a semiconductor device including a step of forming a silicon oxide film, a deposition temperature of the silicon oxide film is 800 ° C. or less by a low pressure CVD method using silane gas and nitrous oxide gas as main materials. 2. A method of manufacturing a semiconductor device, comprising the step of forming under a deposition condition such that the gas pressure of the main raw material is 100 Pa or more. 8. A wiring layer forming step of forming a wiring layer on a semiconductor substrate doped with impurities, and an insulating film depositing step of depositing an insulating film made of a silicon oxide film on the wiring layer. In the method of manufacturing a semiconductor device, in the insulating film deposition step, the silicon oxide film is deposited by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials at a deposition temperature of 800 ° C. or less and a gas pressure of the main raw material. A method of manufacturing a semiconductor device, comprising the step of forming under a deposition condition such that the pressure is 100 Pa or more. 9. An insulating film depositing step of depositing an insulating film of a silicon oxide film on a semiconductor substrate doped with impurities, and a conductive film depositing step of depositing a conductive film on the insulating film. In the method of manufacturing a semiconductor device, comprising: an etching step of etching the conductive film using the insulating film as an etching stopper, the insulating film depositing step is mainly performed on the silicon oxide film, a silane gas and a nitrous oxide gas. A method for manufacturing a semiconductor device, comprising: forming by a low pressure CVD method as a raw material under a deposition condition such that a deposition temperature is 800 ° C. or lower and a gas pressure of the main raw material is 100 Pa or higher. 10. A first conductive film deposition step of depositing a first conductive film to be a floating gate on a semiconductor substrate doped with impurities, and a silicon oxide film on the first conductive film. Method of manufacturing a semiconductor device, comprising: an insulating film deposition step of depositing an insulating film made of a film; and a second conductive film deposition step of depositing a second conductive film to be a control gate on the insulating film. In the insulating film depositing step, the silicon oxide film is deposited by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials at a deposition temperature of 800 ° C. or lower and a gas pressure of the main raw material of 100 Pa or higher. A method of manufacturing a semiconductor device, comprising the step of forming under such deposition conditions. 11. A first conductive film deposition step of depositing a first conductive film to be a floating gate on a semiconductor substrate doped with impurities, and a silicon oxide film on the first conductive film. Method of manufacturing a semiconductor device, comprising: an insulating film deposition step of depositing an insulating film made of a film; and a second conductive film deposition step of depositing a second conductive film to be a control gate on the insulating film. In the insulating film deposition step, the silicon oxide film is deposited by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials at a deposition temperature of 800 ° C. or less and a gas flow rate of the main raw material is 1 liter of a reaction vessel. A method of manufacturing a semiconductor device, comprising a step of forming under a deposition condition of 0.018 liters / minute or less under standard conditions of 25 ° C. and 1 atm. 12. An insulating film deposition step of depositing an insulating film made of a silicon oxide film on an ITO substrate, and a conductive film forming step of forming a conductive film to be source / drain regions on the insulating film. In the method for manufacturing a semiconductor device, the step of depositing an insulating film, wherein the silicon oxide film is deposited by a low pressure CVD method using silane gas and nitrous oxide gas as main raw materials at a deposition temperature of 800 ° C. or lower, A method of manufacturing a semiconductor device, comprising the step of forming the gas pressure of 100 Pa or more under deposition conditions.