JPH08339697A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit which enhances the efficiency of a test as a whole by a method wherein a two-phase clock is used in a high-speed test and a one-phase clock is used in a low-speed test. CONSTITUTION: By means of clock signals CK00, CK10 having a phase difference, the address input latch timing of memory parts 101, 102 is shifted, and an internal operation by using a plurality of memory parts is performed at high speed as a whole. A semiconductor integrated circuit is provided with data latch circuits 107, 108, and the time up to the data output of the memory parts from the address latch of address input latch circuits 105, 106 can be tested. Control circuits 115, 116 select a state in which an address latch timing in a test mode and a data latch timing are performed by two-phase clock signals CK00, CK01 and a state in which the timings are performed by the one-phase clock signal CK00.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a circuit having a plurality of memory units and performing a logical operation using data read from the memory units, and more specifically to a memory of the circuits. The present invention relates to a technique for improving the efficiency of a test for a unit, for example, a technique effectively applied to an associative memory or a memory with a logical function.

[0002]

2. Description of the Related Art Cache memory, address translation buffer, address translation mechanism, AI (Artificial Intelligenc)
e) In a semiconductor integrated circuit to which an associative memory structure such as a memory is applied, the output of one memory unit is used as it is or after performing a required logical operation as address information of another memory unit. At this time, in order to sequentially synchronize the data supply from the previous stage to the next stage with the clock signal, a latch circuit or a register whose latch operation is controlled by the clock signal can be arranged at a required portion of the signal path.

[0003]

In particular, the present inventor completes the operation in the middle of the clock signal cycle when all the operations of the memory section built in the semiconductor integrated circuit are synchronized with a certain operation reference clock signal. In such a case, it has been necessary to wait for the next cycle, and it has been found that such a waste due to the waiting time cannot be ignored in a semiconductor integrated circuit intended for high speed operation. Therefore, using a plurality of phases of clock signals whose phases are slightly shifted from each other, it has been studied to operate a plurality of memory units incorporated in a semiconductor integrated circuit by shifting the timing as necessary. According to this, an address latch circuit is provided in the address input stage of the memory unit, and the address latch timing is shifted by clock signals whose phases are mutually shifted, so that the timing for obtaining necessary data from a plurality of memories is made uniform, or It is possible to avoid wasting time until the operation of the stage circuit is started. At this time, considering the test operation of each memory unit, the previous access data is held from the time when the address latch circuit latches the address signal until the data is fixed after the address latch circuit latches the address signal. It has been found useful to arrange a test-dedicated data latch circuit also on the output side of the memory section in a test of various access times such as a waiting time.

However, when the address input latch circuit and the data latch circuit are controlled by different clock signals for testing, a large number of clock signals are used to minimize the error between the clock signals. For this reason, it takes time to adjust the clocks, and the determination of one access time for one memory unit must consider the waveforms of two types of clock signals. For this reason, if all tests are performed on the memory section by controlling the address input latch circuit and the data latch circuit with different clock signals, the test time becomes huge and the test becomes inefficient. It was made clear by the inventor.

An object of the present invention is to improve the test efficiency for a plurality of memory units built in a semiconductor integrated circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the semiconductor integrated circuit (1, 2) is
The memory unit (101) and an address input latch circuit (105) which holds an internal address signal and supplies it to the memory unit in synchronization with a change in the signal supplied to the clock terminal from the first state to the second state. And a memory which transmits an input to an output in a second state of a signal supplied to a clock terminal and holds and outputs input data in synchronization with a change of the signal from the second state to the first state. A data output latch circuit (107) and a clock input terminal of the data output latch circuit are fixed to a first clock signal (CK00), a second clock signal (CK01), and the second state. And a control circuit (115) for selectively supplying any one signal selected from the signals, and a logic circuit for receiving the output of the data output latch circuit and performing a logical operation ( 10) comprises a, formed by one chip. For example, the address input latch circuit is an edge trigger type latch circuit, and the data output latch circuit is a D type latch circuit.

The control circuit supplies a clock signal (CK0) based on a mode signal (S1, S2) of a plurality of bits.
0), the clock signal (CK01), or the signal fixed in the second state.

In the entire semiconductor integrated circuit, the memory section, the address input latch circuit, the data output latch circuit,
And a control circuit, and the other set of circuits including the respective circuits, the external clock input terminals (P00, P01 and P10, P11) dedicated to each of the address input and data. It receives the clock signal for output individually.

[0011]

According to the above-mentioned means, in order to speed up the internal operation of the entire semiconductor integrated circuit using a plurality of memory sections, different memories are used by using clock signals of a plurality of phases having phase differences. It is possible to shift the address input latch timing of each unit. In the semiconductor integrated circuit having such a premise, in the test of the memory section (101, 102), the address input latch circuit (105, 106)
Tests various access times, such as the time from when the address signal is latched until the data is determined, and the time when the previous access data is held after the address input latch circuit (105, 106) latches the address signal. Therefore, the data output latch circuit (107, 108) is provided for that purpose. The control circuit (115, 116) performs the address latch timing and the data latch timing in the test mode by respectively different two-phase clock signals as illustrated in FIG. 6 and illustrated in FIG. 7. As described above, it is possible to select a state in which the one-phase clock signal is used. The test using the one-phase clock signal can be used for a relatively low speed test on the memory unit, and the test using the two-phase clock signal can be used for a relatively high speed test on the memory unit. For example, the minimum time from the address latch timing to the read data confirmation timing is
It can be detected as the time from the rising timing of the first clock signal (CK00) to the falling timing of the second clock signal (CK01). Furthermore, by changing the phase difference of the second clock signal (CK01), it is possible to detect the timing at which the data read by the previous access is held. As described above, various tests can be performed on the memory unit by using the two-phase clock signals. However, when controlling the address input latch circuit and the data output latch circuit with clock signals having different phases, use a large number of clock signals as a whole to minimize errors between these clock signals. In addition to the time-consuming work of adjusting the clock, the determination of one access time for one memory unit must consider the waveforms of two types of clock signals. Therefore, if all tests are performed on the memory unit by the method of controlling the address input latch circuit and the data latch circuit with different clock signals,
The test time becomes huge and the test becomes inefficient. In order to improve the test efficiency, the one-phase clock signal (CK00) is used for both the address input latch and the data output latch as illustrated in FIGS. 8 (F) and 8 (G).
At this time, the access time depends on the clock signal (CK0
It is possible to easily obtain the time from the rising timing to the falling timing of 0). Since the control of both latch timings is performed by the one-phase clock signal,
It is not necessary to match the errors between the clock signals as in the case of using the two-phase clock signals. These can improve the test efficiency. However, in the high-speed test in which the cycle time of memory access is shortened (the cycle time is not much longer than the access time from address input to data output),
As is clear from the waveforms illustrated in (F) and (G), the frequency of the clock signal (CK00) is increased and the duty ratio thereof is increased. In order to generate it, an expensive or considerably high-performance tester is required. Therefore, by using the two-phase clock for the high-speed test and using the one-phase clock for the low-speed test, it is possible to improve the overall test efficiency.

[0012]

1 is a block diagram of a memory with logic according to an embodiment of the present invention. The memory with logic 1 shown in the figure is not particularly limited, but includes two mutually identical memory blocks 101 and 102, and receives data read from the memory blocks 101 and 102 to perform a logical operation. A circuit 103 is provided.

The memory blocks 101 and 102 are ECL-CMOS type high speed SRAMs (static random access memories), although not particularly limited thereto. For example, as shown in FIG. 2, static memory cells MC are arranged in a matrix. The memory cell array 130. A select terminal of memory cell MC is coupled to a representative word line WL, and a data terminal of memory cell MC is coupled to a representative complementary bit line BL. The row address decoder 131 decodes the internal row address signal applied to the address input terminal 140, and the result of the decoding is applied to the word driver 132.
The word line corresponding to the internal row address signal is driven to the selection level. The column address decoder 133 decodes the internal column address signal applied to the address input terminal 141, selectively operates the column switch circuit 134 according to the decoding result, and outputs n pairs of complementary data lines corresponding to the internal row address signal. Reed
The write amplifiers AMP1 to AMPn are connected and controlled. As a result, the selection terminal is coupled to the word line selected by the internal row address signal, and the data terminal is coupled to the complementary bit line selected by the internal column address signal.
Read / write amplifier AMP with n memory cells
1 to AMPn. Read / write amplifier AM
When the read operation is instructed by the write enable signal WE, the P1 to AMPn amplify the read data from the memory cell selected as described above and supply the amplified data to the data output terminal 142. Further, the read / write amplifiers AMP1 to AMPn amplify the write data supplied from the data input terminal 143 when the write operation is instructed by the write enable signal WE and select the memory selected as described above. Supply to the cell.

In the memory blocks 101 and 102 of FIG. 1, an internal address signal (internal row address signal and internal column address signal) is formed by an address input buffer 104 for inputting an external address signal. The output of the address input buffer 104 is the address input latch circuit (LA
Tai) 105, 106, and then each memory block 10
It is supplied to the address input terminals 140 and 141 of 1,102. The data output terminals 142 of the memory blocks 101 and 102 are data output latch circuits (LATdo) 107,
It is supplied to the logic circuit 103 via 108. The data input terminal 143 of each memory block 101, 102 is connected to the data input buffer 109. Although the write enable signal WE and the chip selection signal are omitted in FIG. 1, they are supplied from the access entity of the memory with logic 1.

A clock signal CK00 is supplied to a clock terminal of the address input latch circuit 105 via a clock buffer 111, and an edge for latching the address input is synchronized with a rising change (change from low level to high level) thereof. It is a trigger type latch circuit. Similarly, the clock signal C is supplied to the clock terminal of the address input latch circuit 106 via the clock buffer 112.
The edge trigger type latch circuit is supplied with K10 and latches the address input in synchronization with the rising change. The clock signal CKdo0 is supplied to the clock terminal of the data output latch circuit 107, the input data is transmitted to the output during the high level period, and the input data is latched in synchronization with the change from the low level to the high level. It is a D-type latch circuit. Similarly, the clock signal CK is applied to the clock terminal of the data output latch circuit 108.
It is a D (delay) type latch circuit which is supplied with do1 and transmits input data to the output during the high level period and latches the input data in synchronization with the change from the low level to the high level. Data output latch circuit 107, 1
The latch operation of 08 is exclusively used for testing the memory units 101 and 102, and the clock signal C is used in the normal operation.
Kdo0 and CKdo1 are fixed to the high level, and both data output latch circuits 107 and 108 are controlled to output the input data through. The details of the control will be described later.

Here, the specific logic operation in the logic circuit 103 in the memory with logic 1 of the present embodiment will not be described in detail, but for example, the data output latch circuit 1
The output of 07 is output to the logic circuit 103 in the preceding logic circuit 110.
Is supplied to the logic circuit 103 after being compared with the data supplied from the logic circuit or subjected to a shift operation according to the control data supplied from the logic circuit 103. The logic circuit 103 performs a predetermined logic operation using the output of the preceding logic circuit 110 and the output of the data output latch circuit 108, and outputs the result. At this time, in the normal operation, the clock signal C
The time from when the address input latch circuit 105 latches the address signal in synchronization with the rising transition of K00 until the output of the preceding logic circuit 111 is determined, and the address input latch circuit 106 in synchronization with the rising transition of the clock signal CK10. There is a considerable difference between the time from when the address signal is latched until the output of the data output latch circuit is determined. In FIG. 3A, the former time is referred to as T0 and the latter time is referred to as T1. In the present embodiment, the clock signal CK0 as shown in FIG.
0 and CK10 are clock signals having the same frequency and a constant phase shift (for example, a quarter cycle shift). The phase shift is an amount including the time of the difference between the times T0 and T1. And the time T0 is the clock signal CK
The time is longer than one cycle of 00. In this way, by shifting the address latch timing with the two-phase clock signals CK00 and CK01 having a phase difference, the logic circuit 1
03 can input data read from both memory blocks 101 and 102 at substantially the same timing and perform a logical operation. The logic operation of the logic circuit is synchronized with the clock signal CK10. As shown in FIG. 3B, if it is assumed that only the one-phase clock signal CK00 is operated, the start of the logic operation of the logic circuit 103 will be delayed. As is clear from the above, in order to speed up the internal operation, the address input latch timing is shifted using the clock signals of a plurality of phases having phase differences. In FIG. 3, the address input buffer 1
The address signal supplied from 04 to the inside of the memory with logic 1 is valid for a period of two cycles of the clock signal CK00. Further, P00, P01, P10 and P11 are external input terminals for the clock signals CK00, CK01, CK10 and CK11.

In the test of the memory blocks 101 and 102 in the memory with logic 1 having such a premise,
The time from the address input latch circuits 105 and 106 latching the address signal until the data is determined, the time from the address input latch circuits 105 and 106 latching the address signal to the time when the previous access data is held, etc. It is necessary to test various access times, for which purpose the data output latch circuit 10
7, 108 are provided. Further, test pads 113 and 114 for observing output data are arranged near the output terminals of the data output latch circuits 107 and 108. The test pads 113 and 114 are connected to the input terminals of the tester and used for observing the output of the data output latch circuit.

The clock signals CKdo0 and CKdo1
Are controlled by the clock control circuits 115 and 116. The clock control circuits 115 and 116 have the same circuit configuration as each other, and FIG. 4 shows an example of the clock control circuit 115. The clock control circuit 115 inputs the control signals S1 and S2 common to the clock control circuits 115 and 116 and the clock signals CK00 and CK01. The signal S2 indicates the normal mode or the test mode, and when S2 = low level (designation of the normal mode), the output of the NAND gate NAND1 is fixed to the high level, which causes the data output latch circuit 107 to be set as shown in FIG. Thru the input to the output.

When S2 = high level (test mode designation), the output of the NAND gate NAND1 is the AND gate AN.
It is determined by the output of D. When the signal S1 is at the low level (L), the output of the NAND gate NAND2 is fixed at the high level, and as a result, CKdo0 = CK01. Therefore, as shown in FIG. 6, the address input latch circuit 105 is latched in synchronization with the rising edge of the clock signal CK00, and the read data is latched in synchronization with the falling transition of the clock signal CK01. On the other hand, when the signal S1 is at the high level (H), the output of the NAND gate NAND1 is fixed at the high level, so that CKdo0 = CK00. Therefore, FIG.
6, the address input latch circuit 105 is latched in synchronization with the rising edge of the clock signal CK00, and the read data is latched in synchronization with the falling transition of the clock signal CK00. In FIG. 4, IVT
Is an inverter.

FIG. 7 shows a state where the clock control circuits 115 and 116 perform the address latch timing and the data latch timing in the test mode by the respective two-phase clock signals as shown in FIG. As described above, it is possible to select a state in which the one-phase clock signal is used. The test based on the one-phase clock signal is used for a relatively low speed test on the memory block.
The test using the phase clock signal is used for a relatively high speed test for the memory block. The entire function test including the logic circuit 103 is performed using two-phase clock signals.

FIG. 8 shows an example of operation timing in the test mode. The timing shown in the figure focuses on the memory block 101. For example (A),
When an operation test is performed on the memory block 101 using the clock signal shown in (C), the clock signal C in (C) is used.
It is checked whether the data latched by K01 matches the expected value. Similarly, as in (D), it is checked whether or not the data latched by using the clock signal CK01 which is out of phase with (C) matches the expected value. As a result, the minimum time from the address latch timing to the read data determination timing can be detected as the time from the rising timing of CK00 to the falling timing of CK01. Further, the clock signal CK01
By setting the phase as shown in (E), it is possible to detect the timing at which the data read by the previous access is held. 2 like this
Various tests can be performed on the memory portion by using the phase clock signals. However, when testing by controlling the address input latch circuit and the data output latch circuit with clock signals with different phases,
By using a large number of clock signals as a whole, it takes time and effort to adjust the clocks in order to minimize an error between the clock signals, and two kinds of judgments for one access time to one memory unit are required. The waveform of the clock signal must be considered. Therefore, if all tests are performed on the memory section by the method of controlling the address input latch circuit and the data latch circuit by different clock signals, the test time becomes huge and the test becomes inefficient.

In order to improve the test efficiency, the one-phase clock signal CK00 is used for both the address input latch and the data output latch as shown in FIGS. 8 (F) and 8 (G). The access time can be easily obtained as the time from the rising timing to the falling timing of the clock signal CK00 as shown in (F) and (G). Since the control of both latch timings is performed by the one-phase clock signal, it is not necessary to match the error between the clock signals as in the case of using the two-phase clock signal. These can improve the test efficiency. However, in the high-speed test in which the cycle time of the memory access is shortened (the cycle time is not much longer than the access time from the address input to the data output), it is clear from the waveforms of (F) and (G) in FIG. As described above, since the frequency of the clock signal CK00 becomes high and the duty ratio thereof becomes large, an expensive or considerably highly functional tester is required to generate such a clock signal with high accuracy. . Therefore, a two-phase clock is used for high-speed tests and one for low-speed tests.
By using the phase clock, the overall test efficiency can be improved. For example, when testing the minimum access time, the cycle time is inevitably shortened, so it is a good idea to use a two-phase clock, and when testing the maximum access time, the cycle time is necessarily long. Therefore, it is sufficient to use the one-phase clock.

FIG. 9 shows a block diagram of a semiconductor integrated circuit 2 according to another embodiment of the present invention. The figure shows an address conversion table as an address conversion mechanism for converting a logical address into a physical address. In the figure, the address translation buffer is omitted. The logical address output by the central processing unit (not shown) is considered to be the segment number SEG, the page number PAG, and the offset OFT from the highest side, although not particularly limited. The address conversion table is composed of two memory blocks 101 and 102. A segment table is configured in the memory block 101. A plurality of page tables are configured in the memory block 102. The segment number SEG is an offset address from the start address of the segment table configured in the memory block 101. The start address of the segment table configured in the memory block 101 is stored in the register 120. The segment number SEG is added to the segment table start address of the register 120 by the adder 121 and supplied to the memory block 101 via the address input latch circuit 105. Segment table is segment number SEG
Holds the top address of the page table corresponding to the. The page number PAG included in the logical address is an offset from the page table start address. The page table top address read from the memory block 101 is added to the page number by the adder 122, and the memory block 102 is passed through the address input latch circuit 106.
Is supplied to. The page table holds the page head address corresponding to the page number PAG. Memory block 1
The page head address output from 02 via the data output latch 108 is a physical page address, and the information having the offset OFT coupled to the lower side thereof is the physical address information.

In the embodiment of FIG. 9, address input latch circuits 105 and 106 and data output latch circuits 107,
The clock signal is supplied to 108 by the same clock control circuits 115 and 116 as in the embodiment of FIG. Since the clock control circuits 115 and 116 have already been described, the detailed description thereof will be omitted. In addition, the same circuits as those described in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, the adders 121 and 12 are
2 constitutes a logic circuit. Address input latch circuit 10
6 must input the output of the adder 122 as an address signal. At this time, in the normal operation, the time from when the address input latch circuit 105 latches the address signal in synchronization with the rising change of the clock signal CK00 until the output of the adder 122 is determined and the rising change of the clock signal CK10. There is a considerable difference between the time from the address input latch circuit 106 latching the address signal in synchronization with the time when the output of the data output latch circuit 108 is determined. In FIG. 10A, the former time is referred to as T2 and the latter time is referred to as T3. In the present embodiment, as shown in FIG. 10A, the clock signals CK00 and CK10 are clock signals having the same frequency and a constant phase shift (for example, a 1/2 cycle shift). . The phase shift is the time T2 and T
The amount including the time of the difference of 3 is set. Then, the time T2 is set to a time that exceeds one cycle of the clock signal CK00. In this way, the two-phase clock signals CK00 and CK having a phase difference
By shifting the address latch timing at 01, the memory block 102 can start access at tm and perform address conversion without waiting until time tn. As shown in FIG. 10B, if it is assumed that the clock signal CK00 of only one phase is used for operation,
Address input latch circuit 106 of memory block 102
Latch operation starts from time tn, and the address conversion operation is delayed. In this embodiment as well, in order to speed up the internal operation, the address input latch timing is shifted by using the clock signals of a plurality of phases having phase differences. In addition, in this embodiment, FIG.
In (A) of 0, the logical address is the clock signal CK0.
Shall be defined over a period of 2 cycles of 0.

In the test of the memory blocks 101 and 102 in the semiconductor integrated circuit 2 having such a premise,
The time from the address input latch circuits 105 and 106 latching the address signal until the data is determined, the time from the address input latch circuits 105 and 106 latching the address signal to the time when the previous access data is held, etc. It is necessary to test various access times, for which purpose the data output latch circuit 10
7, 108 are provided. Further, test pads 113 and 114 for observing output data are arranged near the output terminals of the data output latch circuits 107 and 108. By the clock control circuits 115 and 116, the address latch timing and the data latch timing in the test mode are respectively controlled by different two-phase clock signals as shown in FIG. 6 and 1 as shown in FIG. It is made possible to select the state to be performed by the phase clock signal. 1
The test using the phase clock signal is used for a relatively low speed test on the memory block, and the test using the two phase clock signal is used for a relatively high speed test on the memory block. Therefore, also in this embodiment,
By using the two-phase clock for the high-speed test and the one-phase clock for the low-speed test, it is possible to improve the overall test efficiency.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes. For example, the number of memory blocks incorporated in the semiconductor integrated circuit, the configuration of the memory blocks, the data storage format of the memory blocks, etc. are not limited to the above-mentioned embodiment, and can be changed as appropriate. In addition to the address translation, the present invention also provides an address translation buffer,
It can be widely applied to various semiconductor integrated circuits such as cache memory and AI memory.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the address input latch timings of the memory units different from each other can be shifted by using the clock signals of a plurality of phases having a phase difference, the internal operation as a whole using the plurality of memory units can be performed at high speed. Can be converted. Under such a premise, since the data output latch circuits (107, 108) are provided, in the test of the memory section (101, 102), the address input latch circuit (105, 106) outputs the address signal. Various access times can be tested, such as the time from latching until the data is determined, and the time when the address input latch circuit (105, 106) latches the address signal and the previous access data is held. .
At this time, the control circuit (115, 116) selects a state in which the address latch timing and the data latch timing in the test mode are respectively performed with the respective two-phase clock signals and the one-phase clock signal. can do. Therefore, by using the two-phase clock for the high-speed test and using the one-phase clock for the low-speed test, it is possible to improve the overall test efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory with logic according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a memory block.

FIG. 3 is an explanatory diagram of a normal operation for performing address input latch control using two-phase clock signals in the memory with logic of FIG.

FIG. 4 is a logic circuit diagram of an example of a clock control circuit.

FIG. 5 is an explanatory diagram of clock control for a memory block when a normal operation mode is set in the clock control circuit.

FIG. 6 is an explanatory diagram of clock control for a memory block when a test mode using a two-phase clock is set in the clock control circuit.

FIG. 7 is an explanatory diagram of clock control for a memory block when a test mode using a one-phase clock is set in the clock control circuit.

FIG. 8 is an operation timing chart of an example in a test mode.

FIG. 9 is a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention.

10 is an explanatory diagram of a normal operation of performing address input latch control using two-phase clock signals in the semiconductor integrated circuit of FIG.

[Explanation of symbols]

1 memory with logic 2 semiconductor integrated circuit 101, 102 memory block 103 logic circuit 105, 106 address input latch circuit 107, 108 data output latch circuit 115, 116 clock control circuit CK00, CK01, CK10, CK11 clock signal S1, S2 control signal 122 adder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoru Isomura 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Kunihiko Yamaguchi 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Center Within

Claims (5)

[Claims] 1. A memory section for selecting a memory cell based on a decoding result of an internal address signal and reading data of the selected memory cell, and an output coupled to the internal address signal input terminal of the memory section to a clock terminal. An address input latch circuit that holds the internal address signal and supplies it to the memory unit in synchronization with the change of the supplied signal from the first state to the second state, and the data for reading the data of the memory unit. The input is transmitted to the output in the second state of the signal coupled to the terminal and supplied to the clock terminal, and the input data is held in synchronization with the change of the signal from the second state to the first state. A data output latch circuit, a first clock line connected to a clock input terminal of the address input latch circuit, and a clock of the data output latch circuit. To the input terminal, any one signal selected from the clock signal from the first clock wiring, the clock signal from the second clock wiring, and the signal fixed in the second state is selected. A plurality of sets of control circuits that are supplied to each other, and further including a logic circuit that receives the output of the data output latch circuit and performs a logical operation, which are integrated into one chip. Integrated circuit. 2. The clock signal, which is coupled to the first and second clock wirings, receives a mode signal of a plurality of bits, and is supplied from the first clock wiring according to the mode signal. , A clock signal supplied from a second clock wiring or a signal fixed to the second state, wherein the first clock wiring is connected to a first external clock input terminal and the second clock wiring is connected to the second external clock input terminal. 2. The semiconductor integrated circuit according to claim 1, wherein said clock wiring is connected to a second external clock input terminal. 3. An external clock dedicated to each of a set of circuits including the memory section, an address input latch circuit, a data output latch circuit, and a control circuit, and another set of circuits including the respective circuits. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is formed by being coupled to an input terminal. 4. The memory unit is a static random access memory.
The semiconductor integrated circuit described. 5. The semiconductor integrated circuit according to claim 4, wherein the address input latch circuit is an edge trigger type latch circuit, and the data output latch circuit is a D type latch circuit.