JPH08339388A - Logical simulation method in multiprocessor system - Google Patents

Abstract

PURPOSE: To perform a test accessing to the same memory area from each processor, regarding the logical simulation method in a multiprocessor system. CONSTITUTION: This method is the one in which a logical simulation and a software simulation are simultaneously operated and the result of the logical simulation and the result of the software simulation are compared by arbitrary timing. In the method, the reading and writing area 1 exclusive for each processor and the writing area 2 shared by all the processors are provided. An instruction to be read is made to be read from the reading and writing area 1 exclusive for each processor, an instruction to be written is made to be written in the reading and writing area 1 exclusive for each processor or the writing area 2 shared by all the processors. By the writing from each processor in the writing area 2 shared by all the processors, the tests of the competitions between processors are made to be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of memory units distributed in a plurality of processor modules or arranged in a memory module independent of the plurality of processor modules. For a multiprocessor system in which a unit is selectively accessed from a plurality of processor modules, a logical simulation and a soft simulation are simultaneously operated, and the result of the logical simulation and the result of the soft simulation are obtained at arbitrary timing. And a logical simulation method for comparing

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an example of the configuration of a multiprocessor system, and FIG. 8 is a diagram for explaining the problems of the conventional logic simulation.

In recent years, the speeding up of processors (CPUs) is approaching its limit, and in order to speed up computer systems, it is realized by increasing the number of processors (CPUs) to construct a multiprocessor system. In order to verify the operation of this multiprocessor system, verification by a test program is very important.

In this test program, it is necessary to verify the normality when the load is increased by increasing the data transfer between the processors (CPUs) in the multiprocessor configuration. Since it takes a huge amount of money to change a manufacturing process due to a design mistake of a processor (CPU) and to deal with a product after shipping, verification in the design process, specifically, verification by a logic simulation is important.

At the final stage of the logic simulation,
Since a normal test program has limitations, verification is generally performed by a random test program using a random method.

FIG. 7 is a diagram showing an example of the configuration of a multiprocessor system. In FIG. 7A, a shared memory 13 is distributed to a plurality of processor modules (PM0, PM1, ... PMn) 1. FIG. 7B shows a case where the shared memory 20 is installed in a plurality of processor modules (PM0, P0
It shows a case where the memory module (MM) 2 is independent from M1, to PMn) 1 independently.

In the multiprocessor system shown in FIG. 7A, memory units (MSU0,1, ... n) 13 are distributed and arranged in each processor module (PM0,1, ... n) 1. Within each processor module (PM0,1, ... n) 1, for example, in page units, which page is which processor module (P
M0,1, ... n) 1 is provided with a page correspondence table (not shown) indicating whether each processor (C
When PU0, ~) 10 accesses the shared memory 13,
Referring to the above page correspondence table, search whether or not the desired data exists in the memory unit (MSU0,1, ... n) 13 in its own processor module (PM0,1, ... n) 1 and Memory module (MSU) 13, Cache memory (Cache) of its own processor module (PM) 1 via the common bus (BUS) 3 It is controlled to read through 11.

In the multiprocessor system shown in FIG. 7 (b), the shared memory 20 has a memory module (M0, PM1, ... PMn) 1 independent of the plurality of processor modules (PM0, PM1, ... PMn) 1.
Since it is independent as M) 2, it is controlled to read the required data by directly accessing the corresponding address via the common bus (BUS) 3.

In the case of performing a logic simulation of the above multiprocessor system, a logic circuit of the multiprocessor system is constructed on the main memory of one computer, and one instruction unit is serially connected, for example, one instruction. (Or, a plurality of instructions) are repeatedly executed to perform a logical simulation of an apparent multiprocessor operation.

[0010]

When performing the above random instruction test on this logic simulation, there are the following problems.

(1) First, the expected value of the execution result of the random instruction sequence executed by each processor of the multiprocessor system is created in advance, and in the method of comparing with the result of the logic simulation, the expected value is created. There is a problem that it takes man-hours.

(2) Then, on the computer, the logical simulation and the soft simulation are simultaneously operated (actually, since they are executed on one computer, they are in serial operation), and an arbitrary There is a method of stopping each simulation operation at a timing and comparing the results of the logical simulation and the soft simulation at the stopped arbitrary timing.

Regarding the method of the logic simulation for executing the logic simulation and the soft simulation at the same time and comparing the results, Japanese Patent Application Laid-Open No. 5-225276, which is the prior application of the applicant of the present application, is a method of executing the logic simulation. ”, The details are disclosed. As a method of simultaneously executing the logical simulation and the soft simulation and comparing the results at arbitrary timings, the method disclosed in Japanese Patent Laid-Open No. 5-225276, "Method of executing logical simulation" is adopted. May be.

In this case, in the multiprocessor system, the operation timings of the logical simulation and the soft simulation in each processor (CPU) 1 are different. Specifically, for example, the logic simulation operates in units of clocks, the soft simulation operates in units of instructions, and the processing time for each instruction is different. Therefore, if the same access address to the memory is used, the contents of that address will change. , It is not possible to specify which processor (CPU0,1, ~ n) 1 has executed the result.
As shown in FIG. 8, the access area in each processor (CPU) 1 was divided and tested in advance. for that reason,
In a multiprocessor system, each processor (CPU0,1,
~ N) There was a problem that the test from 1 to access the same area on the shared memory 13 could not be performed.

(3) Also, the logic simulation is operated twice, and the order of the first and second instructions is different, but the contents of the register and the memory are the same at the first and second arbitrary timings. By creating an instruction sequence to be executed at the first time and the second time and comparing the contents of the register and the memory at the arbitrary timings at the first time and the second time,
There is a method of verifying the operation of the superscalar device.

According to this method, the order of the first and second instruction sequences is different, but it is very difficult to create a random instruction sequence in which the contents of registers and memories are the same.
There was a problem that man-hours would be large.

In view of the above-mentioned conventional drawbacks, the present invention executes a logic simulation and a soft simulation at the same time in a logic simulation method in a multiprocessor system, and compares the execution results of the logic simulation and the soft simulation at arbitrary timings. Method to access the same area on the shared memory from each processor (CPU), or execute the logic simulation twice and the order of the first and second instructions is different but at any timing. It is an object of the present invention to provide a method for easily generating a random instruction sequence that makes the contents of registers and memory the same.

[0018]

1 to 6 are schematic views showing an embodiment of the present invention. The above problems can be solved by a logic simulation method in a multiprocessor system configured as follows.

Also in the present invention, in view of the difference in operation timing between the logic simulation and the soft simulation as described above, the memory area accessed by each processor (CPU) 1 is set for each processor (CPU) 1. , It is assumed that the method of dividing in advance is adopted.

(1) Multiple memory units (MSU0,1, ...)
13 are distributed among a plurality of processor modules (PM0,1, ...) 1 or are arranged in a memory module (M0, M) independent of the plurality of processor modules (PM0,1, ...) 1.
M) 2 and the memory unit (MSU0,1, ...) 13 is selectively accessed from a plurality of processor modules (PM0,1, ...) 1 in a multiprocessor system (see FIG. 7). } A method of operating the logic simulation and the soft simulation at the same time and comparing the result of the logic simulation with the result of the soft simulation at an arbitrary timing, which comprises the plurality of memory units (MSU0,1, ...) 13 For each, a dedicated read / write area for each processor and a shared write area for all processors are assigned.Read instructions are read / write areas dedicated to each processor, and write instructions are read / write areas dedicated to each processor. Alternatively, write in the shared write area of all processors, so that each processor in the shared write area of all processors (CPU0, 1, to n) 10 Sessa (CPU0,1, ~n) by writing to the same address from the 10, configured to perform tests of conflicts between processors. {Refer to FIG. 1} (2) A plurality of memory units (MSU0,1,-) 13 are distributed and arranged in a plurality of processor modules (PM0,1,-) 1 or a plurality of processors Module (PM0,
1, ~) 1 is arranged in a memory module (MM) 2 independent of 1, and the memory unit (MSU0,1, ~) 13 is selectively accessed from a plurality of processor modules (PM0,1, ...) 1. In the multiprocessor system configured as described above, a method of operating a logical simulation and a soft simulation at the same time and comparing the result of the logical simulation and the result of the soft simulation at an arbitrary timing, wherein the plurality of memory units ( MSU0,1, ~
n) 13 to each processor (CPU0,1, to n) 10 dedicated read / write area and shared read / write area to all processors, read instructions are assigned to each processor Read from the writing area, or
With a read instruction designed to read into a specific register A, the read / write area for each other processor,
Or, read area and write area a shared by all processors
Read only undefined data from the specified register A, and do not use the specific register A loaded with the undefined data except for the specific read instruction, and exclude the result comparison between the logic simulation and the soft simulation. The write instruction is a dedicated read of each processor,
The write area or the write area a shared by all the processors is written, and the data shared by the specific register A is not compared, and the read shared by all the processors, the write operation to the write area a, and the like. Processor
(CPU0,1, ~ n) 10 dedicated read / write area,
Read between registers other than the above specific register A,
Check if there is any write disturbance and check the processor (CPU0,
1 to n) Configure to test for competition between 10. {Refer to FIG. 2} (3) A plurality of memory units (MSU0,1,-) 13 are distributed and arranged in a plurality of processor modules (PM0,1,-) 1 or a plurality of processors Module (PM0,
1, ~) 1 is arranged in a memory module (MM) 2 independent of 1, and the memory unit (MSU0,1, ~) 13 is selectively accessed from a plurality of processor modules (PM0,1, ...) 1. In the multiprocessor system configured as described above, a method of operating a logical simulation and a soft simulation at the same time and comparing the result of the logical simulation and the result of the soft simulation at an arbitrary timing, wherein the plurality of memory units ( MSU0,1, ~
n) For 13, the dedicated read / write area of each processor and the shared read / write area for all processors are assigned, and the shared read / write area for all the above processors (CPU0,1, ... n) 10 , Which is initialized in advance with an arbitrary numerical value, the read instruction is executed by each processor (CPU0,1, ... n) 1
Read only from 0, read from write area, or
With a read instruction designed to read into a specific register A, a shared read among all processors (CPU0,1, ... n) 10,
Read from the write area, this specific register A is used for all the processors (CPU0, 1, to n) 10 other than the common read and read from the write area. CPU0,1, ... n) 10 dedicated read / write area, or all processors (CPU
0,1, ~ n) 10 write to the shared write area, and write data to the shared write area for all the processors (CPU0,1, ~ n) 10 is for each processor (CPU0,1, ~ n) 10 And always
A fixed value different from the initialized value is set, and the read / write area values shared by all the specific registers are fixed to the initialized value or fixed to each processor at an arbitrary timing. Configure to check value. {Refer to FIG. 3} (4) A plurality of memory units (MSU0,1,-) 13 are distributed and arranged in a plurality of processor modules (PM0,1,-) 1 or a plurality of processors Module (PM0,
1, ~) 1 is arranged in a memory module (MM) 2 independent of 1, and the memory unit (MSU0,1, ~) 13 is selectively accessed from a plurality of processor modules (PM0,1, ...) 1. In this multiprocessor system, the contents of the memory unit of the other processor module (PM0,1, ... n) 1 is moved into the cache memory (Cache) 11 of its own processor module (PM0,1, ... n) 1. Cache memory in a multiprocessor system
The size of one cache line data stored in 11 is
1. When the read / write instruction has a size larger than the size of the read / write data, the logical simulation and the soft simulation are simultaneously operated in the multiprocessor system, and the result of the logical simulation and the result of the soft simulation are obtained at arbitrary timing. Of the processor modules (PM
0,1, ~ n) 1 shared memory units (MSU0,1,
~ N) 13,20, the data size of one cache line (for example, 16 bytes, 32 bytes, 64 bytes) corresponds to each processor (CPU0,1, ~ n) 10 CPU0,1, ... n) 10 size to read and write (word)
With each of the divided processors (CPU0, 1, ...
n) Unit of data size to read and write with 10 (word)
Corresponding to each processor (CPU0,1, ... n) 10 is divided into byte or multiple bit units, and each processor (CPU
0,1, ... n) 10 dedicated read / write area, each processor (CPU0,1, ... n) 10 has the above shared memory in the unit of read / write instruction data size (word)
It is configured to access the dedicated area assigned to each processor (CPU 0,1, to n) 10 on 13,20. {Fig. 4
Refer to (5) In the logic simulation method of items (1) to (4), a plurality of memory units (MSU0,1, ...) 13 are replaced by a plurality of processor modules (PM0,1, ...) 1. It can be distributed and placed, or multiple processor modules (PM0,
1, ~) 1 is arranged in a memory module (MM) 2 independent of 1, and the memory unit (MSU0,1, ~) 13 is selectively accessed from a plurality of processor modules (PM0,1, ...) 1. In such a multiprocessor system, each processor (CPU0, 1, to n) 10 is provided with a read or write command in a mode in which a read or write unit directly or crosses registers or memories. In a multiprocessor system, logical simulation and soft simulation are operated at the same time, and at arbitrary timing,
A method of comparing the result of the logical simulation and the result of the soft simulation, wherein the read and write modes are selectively set in each of a plurality of processor modules (PM0,1, ... n) 1. Run the same test program on each processor module (PM0,1, ... n) 1,
Each of the processor modules (PM0,1, ..., N) 1 is configured so that the memory access location is changed and tested depending on the mode difference. {Refer to FIG. 5} (6) In the logic simulation method of the items (1) to (5), the logic simulation is operated twice and the first and second
An instruction sequence having the same contents of the register and the memory is generated at an arbitrary timing of the first and second times although the order of the instructions is different from that of the second time, and the two instruction sequences are executed and the register is generated at an arbitrary timing. ， It is a method of comparing and testing that the contents of memory are the same, and the instruction sequence to be executed for the first time is the writing instruction to the writing area shared by all the processors (CPU0,1, ～ n) 10. The instruction sequence that does not include the instruction sequence to be executed the second time is the instruction sequence that does not include the write instruction to the write area shared by all the processors (CPU0, 1, to n) 10 described above. , ~ N) The write command to the write area shared by 10 is configured as a selectively inserted command sequence. {Refer to Fig. 6}

[0021]

That is, in the logic simulation method in the multiprocessor system according to the present invention, a plurality of memory units (MSU0,1, ...) 13 are dispersed in a plurality of processor modules (PM0,1, ...) 1. Or a plurality of processor modules (PM0,1, ...) 1 and a memory module (MM) 2 independent of the memory module (M
SU0,1, ...) 13 to multiple processor modules (PM0,1,
〜) In the multiprocessor system that is selectively accessed from 1, to simultaneously operate the logical simulation and the soft simulation and compare the result of the logical simulation with the result of the soft simulation at an arbitrary timing, Each memory unit
For (MSU0,1, ~ n) 13, allocate the dedicated read / write area of each processor and the shared write area of all the processors, and the read instruction is the read / write area of the dedicated read / write area of each processor. Is executed in all the processors (CPU0,1, ... n) 10 by performing a logic simulation with the instruction sequence designed to be written in the read / write area dedicated to each processor or the shared write area of all processors. It is possible to write to the same address from each processor (CPU 0, 1, to n) 1 in the shared write area, and it is possible to test the competition between processors. {Corresponding to FIG. 1, claim 1} Further, under the above-mentioned logic simulation conditions, the read instruction is read from a dedicated read / write area of each processor, or a read instruction which is read into a specific register A. , Each processor (CPU0, 1, to n) from the read / write area dedicated to each other processor, or the read / write area a shared by all processors
Only the undefined data that cannot be specified in 10 is read, and the specific register A loaded with the undefined data is not used at all except for the specific read instruction, and the result comparison between logic simulation and soft simulation is performed. The write instruction is excluded from the above, and the logic simulation is performed by a dedicated read / write area of each processor, or an instruction string written in the write area a shared by all the processors.

By executing such an instruction sequence, in the read operation common to all the processors and the write operation to the write area a, the shared read operation and the write operation from the plurality of processors (CPU 0, 1, to n) 10 are performed. It is possible to write to the same address in area a, and it is possible to test the competition between processors, and also to read the data exclusively for each processor (CPU0, 1, to n) 10, read in the write area, Read (load) to the above specific register during the write operation
By selectively inserting an instruction and checking whether or not there is a disturbance of a read / write operation between a register other than the specific register A and a dedicated memory area, the processor can be used in a case different from the instruction sequence described in FIG. 1 above. You can test the competition between (CPU0,1, ... n) 10. {Corresponding to FIG. 2 and Claim 2} In the logic simulation method according to Claim 2, each processor (CPU0,1) has a read / write area shared by the processors (CPU0,1, ... , ~ N) The data that was not recognized by 10 was written. Therefore, here, the read and write areas shared by all the processors (CPU 0, 1, to n) 10 are initialized at the beginning of the logic simulation, for example, a numerical value “5” is written. Further, write data from each processor (CPU 0, 1, to n) 10 to the shared read / write area is a fixed value different from the above initialization value, for example, "0" to.

Then, by executing the above-mentioned logic simulation, the contents of a specific register A or the values of the read / write area shared by all the processors (CPU0, 1, ... Check that the above initial value or a value unique to each processor (CPU0, 1, to n) 10 is set. If data other than the above values is detected, it means that an abnormality has occurred, so that the competition test by each processor (CPU 0, 1, to n) 10 can be performed. {Corresponding to FIG. 3 and Claim 3} The multiprocessor system shown in FIG. 7 has a memory unit (MSU0,
It is assumed that the contents of (1 to n) 13 are moved into its own cache memory (Cache) 11 via the common bus (BUS) 3. In this move-in, the size of data stored in each cache memory (Cache) 11 {1 cache line (also referred to as 1 block)} is a unit of read / write data by a read / write command (usually 1
Larger than words) (eg 16 bytes, 32 bytes, 6
4 bytes), the data size (word) to be read and written by each processor (CPU0, 1, to n) 10
(CPU0,1, ~ n) 10 corresponding to each processor (CPU0,1, ~ n)
n) Divide and allocate shared memory 13 to 10. {Fig. 4
(see (a)) Then, when a certain processor (CPU0) 10 accesses a specific word to access the area allocated to itself and it does not exist in its own cache (Cache) 11, another processor (CPU1,2, ~ n) From 10 memory units (MSU0,1, ~ n) 13 or cache (Cache) 11,
The data of the one cache line is moved in via the common bus 3, and a predetermined word in the one cache line thus moved in is loaded into the processor (CPU0) 10. Therefore, it is possible to increase the load in units of one cache line by generating an instruction sequence for performing the above-described processing in each processor (CPU 0, 1, to n) 10 and performing logical simulation. However, the movement of the data block of the one cache line in this case is performed by the cache memory (C
ache) 11 → Storage control unit (MMU) → Memory unit (MMU
SU0,1, ~ n) → common bus → memory unit (MSU0,1, ~ n) →
Storage control unit (MMU) → Cache memory (Cache) 11
Is the route.

This logic simulation method is disclosed in Japanese Patent Application No. 07-071853 “Cache memory operation test method and operation test system” filed by the applicant of the present application. In this method, as described above, 1
This is a method of performing a logic simulation by increasing the load in cache line units, but another method must be adopted to increase the load in a data size smaller than that.

Therefore, in the present invention, each processor (CPU
0,1, ... n) 1 word (4 bytes, 8 bytes, 16 bytes, etc.), which is the unit of reading and writing of 10, is read by each processor (CPU0,
1, to n) 10 read / write units, for example, bytes and multiple bits, and the read / write unit (word) area is divided as shown in FIG.
PU0,1, ~ n) 10 are assigned.

With this configuration, for example, a move-in in cache line units can be generated for each access in byte units or plural bit units, and the load in word units or cache line units can be increased. it can.
In this case, the moving data block is the processor
(CPU0,1, to n) 10 → Cache memory (Cache) 11 → Storage control unit (MMU) → Memory unit (MSU0,1, to n) → Common bus → Memory unit (MSU0,1, to n) → Storage Control unit (MMU) → Cache memory (Cache) 11 → Processor (C
PU0,1, ~ n) 10 routes. {Corresponding to FIG. 4 and Claim 4} FIG. 5 shows two modes for the reading and writing methods of the processor (CPU0, 1, to n) 10, that is, between the memory and the register, for example, in units of 2 bytes ( 1/4 half word), 4 bytes unit (half word) crossing reading and writing mode (method 1)
And the mode (method 2) for reading and writing in a straight line are shown. It is noted that the latest processor modules (PM0,1, ... n) 1 often support these two modes. For example, between two processors (PM0,1),
One is set to the mode 1 mode, and the other is operated in the mode 2 mode.

Processor (PM0) 10 and Processor (PM1) 10
When this kind of operation is performed between and, for example, write data from two processors (PM0,1) is stored in the adjacent 4 bytes of the memory unit (MSU0) 13 of the processor (PM0) 10. You can check the competition between processors (PM0,1). {Refer to Fig. 5 (a)} Fig. 5 (b) shows an example of competing actions in units of half words.
In principle, the operation is the same as that of FIG. {Corresponding to FIG. 5 and Claim 5} Next, as described in the prior art, the logic simulation is operated twice, and the first and second instructions have different orders, but the first and second instructions are different. Create a sequence of instructions to be executed at the first and second times so that the contents of the registers and memory will be the same at arbitrary timings, and compare the contents of registers and memory at the first and second arbitrary timings. By doing so, for example, there is a method of verifying the operation in the superscalar device. In this method, the contents of the register and memory at arbitrary timing are different even though the order of the first and second instruction sequences is different. It is very difficult to create the same random instruction sequence, and there is a problem that the number of steps is large.

Therefore, in the present invention, as shown in FIG. 6, the instruction sequence to be executed for the first time is all processors (CPU0, 1,
~ N) Generates an instruction sequence with no write instruction to the shared write area in 10.

The instruction sequence to be executed for the second time is the same as the instruction sequence to be executed for the first time in all processors (CPU0,1, ... n).
The instruction sequence to be executed the first time can be changed simply by selectively inserting the write instruction to the shared write area in 10, and in the superscalar device, the instruction pair to be executed simultaneously changes. Although the order of the first and second instruction sequences is different, it is possible to easily generate a random instruction sequence that makes the contents of registers and memories the same.
{Corresponding to FIG. 6 and claim 6}

[0030]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 to 6 described above are diagrams schematically showing an embodiment of the present invention.

According to the present invention, the logic simulation method is a method for comparing the result of the logic simulation with the result of the soft simulation, wherein the shared memory (MSU0,1, ... n) 13,20 of the multiprocessor system is Divide into read / write area dedicated to each processor (CPU0,1, ~ n) 10 and read / write area shared by each processor (CPU0,1, ~ n) 10 and select the two areas Means for generating a sequence of instructions to be used for logical simulation and performing logic simulation are necessary means for implementing the present invention. still,
The same reference numerals denote the same objects throughout the drawings.

The logic simulation method according to the present invention will be described below with reference to FIGS. A hardware model for implementing the logic simulation method of the multiprocessor system of the present invention is the multiprocessor system shown in FIGS. 7 (a) and 7 (b).

For example, as described above, the multiprocessor system shown in FIG.
Memory units (MSU0,1, ... n) 13 are distributed and arranged in (PM0,1, ... n) 1, and each processor module (P
M0,1, ... n) 1, for example, in page units, which page is the memory unit (M0,1, ... n) 1 of which processor module (PM0,1, ... n)
SU0,1, ... n) 13 is provided with a page correspondence table (not shown) indicating whether each processor
When (CPU0, ~) 10 accesses the memory, referring to the page correspondence table above, the desired data is the memory unit (MSU0, 1, n) in its own processor module (PM0, 1, ... n) 1.
~ N) It is searched whether it exists in 13, and if it is recognized that it exists in another processor module (PM) 1,
Memory unit (MSU) 13 of its own processor module (PM) 1 via the common bus (BUS) 2, cache memory
Works as if read via (Cache) 11.

FIG. 1 schematically shows conditions for generating an instruction sequence for performing a competition test between processors in the above-mentioned multiprocessor system. In particular, in particular, a plurality of processors (CPU0, 1, ~ N) shows how to enable writing from 10.

In the present embodiment, the relationship between the processor (CPU0,1, ... n) 10 of each processor module (PM0,1, ... n) 1 and the shared memory (MSU0,1, ... n) 13 is shown in FIG. As shown in. That is, the read instruction is for each processor (CPU0,1, ... n)
10 Read / write commands from the dedicated read / write area are stored in the dedicated read / write area of each processor (CPU0, 1, to n) 10 or shared write area of all processors (CPU0, 1, to n) 10. Be sure to write.

When an instruction sequence is generated under such a condition and a logic simulation is performed, all the processors (CPU0, 1, ...
n) Each processor (CPU
A write to the same address occurs from 0,1, ... n) 10, and the competition between each processor (CPU0,1, ... n) 10 can be tested.

When the contention occurs, a processor (CPUi)
The access of 10 becomes a wait, and by analyzing the result, the normality of the competing operation can be checked. For example, assuming that the processor (CPUi) 10 executes an instruction sequence of "ST regB shared memory area" and "LD dedicated memory area regB", the other processor (P
Since the operation of the above "ST regA shared memory area" becomes slow due to the competition with Mj) 10, check the contents of register B (regB) to confirm that processor (CPUi) 10 and processor (P
It is possible to confirm the normality when competing with Mj) 10.
{Embodiment corresponding to claim 1} FIG. 2 is a memory simulation under the same memory condition as FIG. 1 by enabling writing and reading from a plurality of processors (CPU 0, 1, to n) 10 to the same area. The method is shown schematically.

In this embodiment, as shown,
The read instruction is to be read from the dedicated read / write area of each processor (CPU0, 1, to n) 10, and further, by selecting a specific register A and reading it into the specific register A, As shown in the figure, dedicated read / write area for other processors (other than CPU0, 1, to n) 10 or shared read / write area for all processors (CPU0, 1, to n) 10 To be loaded (loaded). Then, the specific register A creates an instruction sequence so as not to be used except for the read instruction. At this time, all the processors (CPU0,1, ... n) 10 have a shared read / write area in which each processor (CPU0,1, ... n)
n) Since data that cannot be recognized by the instruction sequence executed in 10 is stored, data comparison with the result of the soft simulation is not performed for the specific register A.

The write command is issued to the dedicated read / write area of each processor (CPU 0,1, ... n) 10 or all processors (CPU 0,1, ... n) 10 as described in FIG. It is used to write in the shared writing area a.

By thus generating the instruction sequence and performing the logic simulation with the instruction sequence, the dedicated reading and reading to the writing area by each processor (CPU 0, 1, to n) 10 described in FIG. 1 is performed. ， Write processing and each processor
(CPU0,1, -n) 10 shared read and write processing to write area a, as well as dedicated read / write area of each other processor (except CPU0,1, ... n) 10 or all processors ( CPU0,1, -n) 10 can generate an instruction sequence that combines a shared read / write (load) instruction from the write area. With this instruction sequence, compared to the case of FIG.
A more complex logic simulation can be performed by an instruction sequence that combines read and write instructions of each processor (CPU 0, 1, to n) 10. However, the contents of the specific register A to be loaded cannot be confirmed.

For example, in the processor (CPUi) 10, "ST regB shared memory area""LD shared memory area regA" (however, reg
Assuming the execution of an instruction sequence (A is a specific register), if the operation of "ST regB shared memory area" is delayed due to competition between processors, the operation of the next "LD shared memory area regA" is affected. Although there is a possibility, since the regA (register A) is a specific register A, data comparison cannot be performed in the logical simulation. However, by inserting a read instruction (load instruction) from the shared memory area, the instruction sequence executed by each processor (CPU0, 1, to n) 10 is different from that before insertion, so that the processor With the above-mentioned superscalar device, it is possible to execute a logic simulation in an operation different from that before the insertion of the load instruction (that is, corresponding to FIG. 1). {Embodiment corresponding to claim 2} FIG. 3 enables writing and reading from a plurality of processors (CPU0, 1, to n) 10 to the same area, as in the case of FIG. FIG. 3 schematically shows a logic simulation method for checking the read / write data.

First, the read and write areas shared by all the processors (CPU 0, 1, to n) 10 are initialized in advance with an arbitrary numerical value, for example, "5". The read instruction can be read from the dedicated read / write area of each processor (CPU0, 1, to n) 10 or by the read instruction (load instruction) designed to read to the specific register A described above. CPU0,1, ... n) Loads from shared read / write area to CPU10. As described with reference to FIG. 2, the specific register A is not used except for the read instruction.

In the write command, the same operation as that described with reference to FIGS. 1 and 2, that is, each processor (CPU0, 1, to n) 10 dedicated read / write area, or all processors (CPU0,
1, to n) 10 is written to the shared write area, but the write data to the shared write area to all the processors (CPU0, 1, to n) 10 is written to each processor (CPU0, 1, to n) 10. , Always an eigenvalue different from the initial value “5”, for example, “0” to
The number is 3 (however, the total number of processors (CPUs) is 3).

A logical simulation is performed using such an instruction sequence, and the value of the specific register A and the value of the read area shared by all the processors (CPU0,1, ... “5” or each processor (C
Check that PU0,1, ... n) 10 has different fixed values "0"-"3". If all the processors (CPU0,
1, ~ n) The value of the area with the shared read area in 10 is
When it is "4", it can be recognized that an error has occurred in the logic simulation. {Embodiment corresponding to claim 3} As described above, FIG. 4 shows another processor module (PM0, 1, PM0, 1, in the multiprocessor system shown in FIG.
~ N) The contents of 1 memory unit (MSU0,1, ~ n) 13 are transferred to its own cache memory (Cache) 11 via the common bus 3.
Common bus (BUS) in systems that are moved in to
FIG. 7 is a diagram schematically showing a method of increasing the load at the time of move-in via 3.

In this move-in, each cache memory (C
ache) The size of the data stored in 11 {1 cache line (also referred to as 1 block)} is larger than the unit of read / write data by a read / write command (usually 1 word) (16 bytes, 32 bytes, 64 bytes, etc.), each processor (CPU0, 1, to n) 10
Data size (word) to be read and written by, corresponding to each processor (CPU0,1, ... n) 10 Shared memory area 1
Divide 3 and assign. {Refer to Fig. 4 (a)} Then, a certain processor (CPU0) 10
When a specific word in the above-mentioned self-allocated area on 13 is accessed and does not exist in its own cache (Cache) 11, another processor (CPU 1, 2, to n) 10 memory unit (MSU0, 1, to n) 13, or from the cache (Cache) 11, the data of the above 1 cache line is a common bus (BUS)
3 is moved in, and a predetermined word in one moved cache line is loaded into the processor (CPU0) 10. It is possible to increase the load in units of one cache line by generating an instruction sequence for performing the above processing in each processor (CPU 0, 1, to n) 10 and performing a logic simulation. However, in this case, movement of data in units of one cache line is performed by the cache memory (Cac
he) 11 → Storage control unit (MMU) → Memory unit (MSU
0,1, to n) → common bus → memory unit (MSU0, 1, to n) → storage control unit (MMU) → cache memory (Cache) 11

As described above, this logic simulation method is applied to the Japanese Patent Application No. 07-071853 previously filed by the applicant of the present application.
No. “Cache memory operation test method and operation test system”. With this method, 1
This is a method of increasing the load in cache line units and performing logical simulation. Another method is to increase the load in word units and one cache line unit when accessing with a data size smaller than that (for example, bytes). Need to take.

Therefore, in the present invention, each processor (CPU
0,1, ... n) 1 word (4 bytes, 8 bytes, 16 bytes, etc.), which is the unit of reading and writing of 10, is read by each processor (CPU0,
1, to n) 10 read / write units, for example, bytes and plural bits, and the read / write unit (word) area is divided and assigned as shown in FIG. 4 (b).

As a result, a move-in is generated in units of one cache line for each access in units of a plurality of bytes,
It is possible to increase the load in word units and one cache line unit. In this case, the data block transferred by the access is the processor (CPU0, 1, to n) 10 → cache memory (Cache) 11 → storage control unit (MMU) → memory unit (MSU0, 1, to n) → Common bus → Memory unit
(MSU0,1, -n) → Storage control unit (MMU) → Cache memory (Cache) 11 → Processor (CPU0,1, -n) 10 Route.

FIG. 5 shows a plurality of processors (CPU0,1, ... n).
The same test program is executed (that is, logic simulation) between 10 and, for example, two processors (CPU
0, 1) schematically shows a method of verifying two read / write modes provided in 0, 1).

As described above, the processor (CPU0,1, ... n) 1
There are two modes for reading and writing 0, that is, a mode of reading and writing between the memory and the register, for example, in units of 2 bytes (1/4 half word) and 4 bytes (half word). (Mode 1) and a mode for directly reading and writing (Method 2) are shown.
(PM0,1, -n) 1 often supports the two modes.

Therefore, in the logic simulation method of the present invention, the read / write mode is set in the two processors (CPU0, 1) 10 before the test program is executed.
Change the data read by two processors (CPU0, 1) 10 by setting a predetermined control register so that only 1/4 half-word or half-word is executed by write and read instructions. Is the fixed part (ie 1/4 half-word, or
Half-words), so that the two processors
(CPU0,1) 10 performs a logic simulation with the same test program.

As a result, two processors (CPU0,1) 10
Even if the same test program is executed in, the different read and write modes are set in advance, so the areas for memory access are different and the two read and write modes are verified without address collision between the processors. It can be performed.

In the above embodiment, two processors (CPU
0,1) 10 has been described as a method of executing the same test program, but in general, multiple processors (CPU0,1, ... n) 10
It goes without saying that the same thing can be carried out between the two. By performing such a logical simulation, it is possible to verify the mode in each processor (CPU 0, 1, to n) 10. {Embodiment corresponding to claim 5} The mode verification described above can also be applied when the instruction sequence of the logic simulation described in FIGS. 1 to 4 is generated.

FIG. 6 shows a method of creating an instruction sequence in which the logic simulation is operated twice, and the order of the first and second instructions is different, but the contents of the register and memory are not changed at any timing. It is the figure which showed typically.

First, as the instruction sequence to be executed for the first time, an instruction sequence having no write instruction to the shared write area in all the processors (CPU 0, 1, to n) 10 is generated. Then, the instruction sequence to be executed the second time is only necessary to selectively insert the write instruction to the shared write area in all the processors (CPU0, 1, to n) 10 into the instruction sequence to be executed the first time. The order of the instruction sequence executed at the first time can be changed, and in the superscalar device, the pair of instructions executed at the same time is changed. Therefore, the order of the instruction sequence at the first time is different from that at the second time. It is possible to easily generate a random instruction sequence that makes the contents of memory and memory the same.

The above-mentioned instruction sequence generation method can be applied to the generation of the instruction sequence for logic simulation described with reference to FIGS. {Example corresponding to claim 6}

[0057]

As described above in detail, according to the logic simulation method in the multiprocessor system of the present invention, a dedicated read / write area for each processor and a shared write area for all processors are provided, and read instructions are provided. Read from the dedicated read / write area of each processor, and write instructions are read / write exclusive to each processor.
By generating the instruction sequence by writing in the write area or the shared write area of all the processors, each processor can perform a test to access the same area in the shared write area of all the processors.
Also, the logic simulation is operated twice and the first and second
Although the order of the instructions is different from the first time, the instruction sequence in which the contents of the register and memory do not change at any timing is also accessed to the dedicated read / write area of each processor and the shared write area of all processors. It can be easily generated by combining the instruction sequences to be executed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 2 is a diagram showing an embodiment of the present invention (Part 2).

FIG. 3 is a diagram showing an embodiment of the present invention (part 3).

FIG. 4 is a diagram showing an embodiment of the present invention (No. 4).

FIG. 5 is a diagram showing an embodiment of the present invention (No. 5).

FIG. 6 is a diagram showing an embodiment of the present invention (No. 6).

FIG. 7 is a diagram showing a configuration example of a multiprocessor system.

FIG. 8 is a diagram for explaining the problems of the conventional logic simulation.

[Explanation of symbols]

1 Processor module (PM0,1, ~ n) 10 Processor (CPU0,1, ~ n) 11 Cache, cache memory (Cache) 12 Memory controller (MMU) 13,20 Memory unit, shared memory (MSU0,1, ~ n) n) 2 Memory module 3 Common bus (BUS) Read / write area dedicated to each processor Write area shared by all processors a Read / write area shared by all processors Specific register A, shared memory is divided for each processor Allocated area

Claims (6)

[Claims] 1. A plurality of memory units are arranged in a distributed manner among a plurality of processor modules, or arranged in a memory module independent of the plurality of processor modules, and the memory units are arranged in a plurality of processors. In a multiprocessor system adapted to selectively access from a module, a method of operating a logical simulation and a soft simulation at the same time and comparing the result of the logical simulation with the result of the soft simulation at an arbitrary timing, For each of the above memory units, a dedicated read / write area for each processor and a shared write area for all processors are assigned.Read instructions are read / write areas dedicated to each processor, and write instructions are for each processor. Dedicated reading,
Write to the write area or the shared write area of all processors, and test the contention between processors by writing to the same address from each processor in the write area shared by all processors. Logic simulation method for processor system. 2. A plurality of memory units are arranged in a distributed manner among a plurality of processor modules, or are arranged in a memory module independent of the plurality of processor modules, and the memory units are arranged in a plurality of processors. In a multiprocessor system adapted to selectively access from a module, a method of operating a logical simulation and a soft simulation at the same time and comparing the result of the logical simulation with the result of the soft simulation at an arbitrary timing, A dedicated read / write area for each processor and a shared read / write area for all processors are assigned to the above-mentioned plurality of memory units, and read instructions are read or written from the dedicated read / write area of each processor, or Read into a specific register In the read instruction, the read / write area dedicated to each other processor, or the read area / write area shared by all the processors is read, and the specific register is not used except for the read instruction. , A dedicated read / write area for each processor, or write to the above write area shared by all processors, and a data read / write area shared by all processors without comparing data in the specific register It is characterized in that a competition test between processors is performed by a read / write operation from a processor and a read / write operation in a dedicated read / write area of each processor with a register other than the specific register. Simulation method in a multiprocessor system for parallel processing. 3. A plurality of memory units are distributed and arranged in a plurality of processor modules, or arranged in a memory module independent of the plurality of processor modules, and the memory units are arranged in a plurality of processors. In a multiprocessor system adapted to selectively access from a module, a method of operating a logical simulation and a soft simulation at the same time and comparing the result of the logical simulation with the result of the soft simulation at an arbitrary timing, For each of the above memory units, a dedicated read / write area for each processor and a shared read / write area for all processors are assigned. Initialize with, and the read command is In a read instruction in which a read / write area dedicated to each processor is read or a specific register is read, the read / write area shared by all the processors is read, and this specific register is read by all the processors. Do not use it for anything other than reading from the shared read / write area, and use the write instruction for the read / write area dedicated to each processor, or to the write area shared by all processors.
The write data to the write area shared by all the processors is always a fixed value different from the initialized value in each processor, and the specific register and the read shared by all the processors are read at arbitrary timing. A logic simulation method in a multiprocessor system, characterized in that the value of the write area is confirmed to be the initialized value or a fixed value unique to each processor. 4. A plurality of memory units are arranged in a distributed manner in a plurality of processor modules, or arranged in a memory module independent of the plurality of processor modules, and the memory units are arranged in a plurality of processors. In a multiprocessor system in which a module is selectively accessed, the contents of a memory unit of another processor module are moved into the cache memory of its own processor module and stored in the cache memory in the multiprocessor system. The size of cache line data is 1 read, read by write command,
A method of simultaneously operating a logical simulation and a soft simulation in the multiprocessor system when the size is larger than the write data size, and comparing the result of the logical simulation and the result of the soft simulation at an arbitrary timing, On a plurality of memory units shared by the processor modules, the data size of the one cache line is divided into the sizes read and written by the processors corresponding to the processors, and further divided. The read / write size of each processor is divided into bytes or multiple bits corresponding to each processor and assigned as a dedicated read / write area for each processor. In units of allocated data size, Logic simulation method in a multiprocessor system, characterized in that access the dedicated region allocated to each processor in the serial shared memory. 5. A plurality of memory units are arranged in a distributed manner in a plurality of processor modules, or arranged in a memory module independent of the plurality of processor modules, and the memory units are arranged in a plurality of processors. In a multiprocessor system configured to be selectively accessed from a module, a read / write instruction in each processor can receive a register in a read unit or a write unit,
In a multiprocessor system having a mode of orthogonal or crossing between memories, a logic simulation and a soft simulation are simultaneously operated, and the results of the logic simulation and the soft simulation are compared at arbitrary timing. Then, the read / write mode is selectively set in each of the plurality of processor modules, the same test program is run in each processor module, and the memory access location is different in each processor module due to the difference in the above mode. 5. The logic simulation method in the multiprocessor system according to claim 1, further comprising: 6. The logic simulation is operated twice and 1
Although the order of the instructions is different between the second time and the second time, an instruction sequence having the same contents of the register and the memory is generated at an arbitrary timing of the first time and the second time, and the two instruction sequences are executed to perform an arbitrary timing. Then, in the method of comparing and testing that the contents of the register and the memory are the same, the instruction sequence to be executed for the first time is an instruction sequence that does not include the write instruction to the write area shared by all the processors, The instruction sequence to be executed the second time is an instruction sequence in which a write command to the write area shared by all the processors is selectively inserted in an instruction sequence that does not include the write instruction to the write area shared by all the processors. Claim 1 characterized by the above.
5. A logic simulation method in the multiprocessor system according to any one of 5 to 6.