CN102681937A - Correctness verifying method of cache consistency protocol - Google Patents
Correctness verifying method of cache consistency protocol Download PDFInfo
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Abstract
The invention provides a correctness verifying method of a cache consistency protocol. After a computer enters an operating system, the complexity of a core and the application of the operating system is higher; the action of a processor is not easy to control accurately; therefore, in order to keep verification correctness, a verifying program for the cache consistency protocol is necessary to embed in a systematic procedure; the program is embedded in a BIOS (basic input/output system) code; after the initialization of a memory subsystem is completed at the initialization initial stage of the system, the verifying program is started to be executed; the verifying program needs to be capable of accurately controlling actions of each processor of the system, supports a user to select a verification item to be particularly executed, and feeds back a verification result to the user; by using the method, the verification of the correctness of the cache consistency protocol is realized at a system level; all application scenes of a real system can be completely covered; the disadvantages that a conventional verifying method based on an analog way is low in efficiency and poor in verification coverage rate are made up; the design period and the verifying period of an inter-domain cache consistency chip of the processor can be shortened; the one-time taping-out mission success rate of the chip can be guaranteed effectively; and therefore, the correctness verifying method has an extremely wide development prospect and an extremely high technical value.
Description
Technical field
The present invention relates to field of computer technology, specifically a kind of buffer consistency agreement correctness verification method.
Background technology
The employing of cache technology is that the speed that improves constantly with processor is relevant.Because the speed of processor improves constantly, caused the contradiction of speed of access speed and the processor of storer.In order to solve the contradiction between the two, introduced high-speed cache, it is between processor and the internal memory, matees speed between the two, and the speed with high-speed cache is seen from CPU by the system that makes, the capacity of main memory.But after having introduced cache technology, also introduced another problem, that is exactly the consistency problem of high-speed cache.
Present stage; Along with the development of multiprocessor, multinuclear, many nuclear technology, the inconsistent problem of data all may appear in the storage hierarchy of multiple processor system between adjacent level and within one deck; Wherein, the data consistency problem of high-speed cache especially at present research focus.Because many separate asynchronously operations of processor, therefore the copy with a storage block maybe be different in a plurality of high-speed caches.When many copies of certain unit of processor pair shared storage in its local cache are safeguarded,, just possibly cause the overall inconsistent of storer as long as the local replica of this unit is made amendment.If the state of the data block of high-speed cache is consistent, just can prevent the appearance of inconsistent problem.
At present, the Computer System Design of parallel shared drive structure can be taked following two kinds of system architecture: SMP and CC-NUMA basically.SMP is owing to multiprocessor shared system bus, so extensibility is relatively poor, and when processor quantity expanded to certain scale, system bus must become bottleneck; Therefore the non-homogeneous memory access of buffer consistency system (CC-NUMA) is the comparatively ideal system structure that present industry adopts when the computer system of the parallel shared drive structure of design.The CC-NUMA system at system scale hour; Can be by the buffer consistency of the direct maintenance system of each processor; But when system scale expands to (more than 8 Socket) when fairly large; Then, can divide the territory with processor usually, use extra chip to carry out the maintenance of buffer consistency between domain processor based on the consideration of efficient and extensibility.
The chip of buffer consistency is as the core original paper of extensive CC-NUMA system between the maintenance processor territory; Design and proof procedure are very complicated; Because checking work in early stage is insufficient, cause the chip single to throw the sheet failure through regular meeting, need repeatedly throw sheet and carry out repeatedly; This has increased the chip design cost greatly, and has a strong impact on the R&D cycle.The common way of industry is to use simulated mode to carry out the protocol level checking now, but this verification mode efficient is low, is difficult to guarantee to travel through all scenes.Therefore, need to propose a kind of system-level buffer consistency agreement correctness verification method, guarantee to verify fully in earlier stage, once throw the sheet success ratio, and then reduce the chip design cost, shorten the R&D cycle with assurance in chip design.
Summary of the invention
The purpose of this invention is to provide a kind of buffer consistency agreement correctness verification method.
The objective of the invention is to realize that after computing machine got into operating system, the core and the application of complex property of operating system be higher by following mode; Be not easy accurate processor controls behavior, therefore, need in systematic procedure, embed the buffer consistency protocol verifier for keeping proving correctness; This program is embedded in the bios code; After system initialization initial stage memory subsystem initialization is accomplished, promptly begin to carry out proving program, proving program needs can each processor behavior of accuracy-control system; And support the user to select the checking item that specifically will carry out; To user feedback checking result, therefore, the proving program of buffer consistency agreement correctness verification method is made up of following several parts:
1) base library: comprise processor architecture module, processor flag module, caching module, internal memory operation module, digit manipulation module, latching operation module, fence synchronization module and input/output module, wherein:
The processor architecture module provides the visit to processor register, instruction-level, need support x86 and the relevant checking of itanium platform like proving program, needs to realize x86 and two kinds of processor architecture modules of ia64;
The processor flag module is used for each processor thread in the compartment system, is convenient to proving program and accurately carries out processor scheduling;
The caching module provides the instruction and the calcellation of Data Cache and writes back operations;
The internal memory operation module, provide to internal memory interval duplicate, the operation of zero clearing, read/write;
The digit manipulation module, the ability that provides the bit stages of digital to be provided with/to obtain;
The latching operation module provides various ranks are comprised in the domain processor, locking between domain processor, release, obtain the ability of lock state of operation;
The fence synchronization module provides the ability synchronous to the multiprocessor fence;
Input/output module provides the ability to user class input response and format output;
2) testing authentication collection: comprise that memory headroom covers authentication module, the IO space covers authentication module, processor core competition authentication module, data cached shared set traversal authentication module, buffer consistency affairs traversal authentication module, wherein:
Memory headroom covers authentication module, needs all memory address spaces of traversal, for improving traversal efficient, all threads in the dispatching system; Each thread is responsible for the visit to certain section interval, and the interval sum of the traversal of all threads is the whole memory address space of system, to individual address; Its address value is write this address, read back then, if consistent with the value of writing; Then explain the visit of this address normally,, think this pass if all address entries are all normal;
The IO space covers authentication module, needs all configure/status register space of traversal, IO space and interrupts the space, if the access process processor is normal, promptly thinks this pass;
Processor core competition authentication module comprises that spin lock checking and fence verify that synchronously the spin lock checking is the lock mechanisms that a plurality of thread execution realize based on software, if lock/release is normal, then thinks this pass;
The synchronous checking of fence refers to that promptly a plurality of threads carry appointed task and get into the fence critical section, as long as abortive thread is arranged, fence just is in guard mode, if it is synchronous normally to accomplish fence, then thinks this pass;
Data cached shared set traversal authentication module needs the various data cached shared collection scenario that all processor cores are combined in the Ergodic Theory, is specially the thread that is in shared set in advance certain section memory headroom is traveled through; One of them thread carries out write operation to a sector address space, and all are in the thread of sharing set and carry out read operation then, and all threads were all switched to after writing thread; Reset and share the thread that comprises in the set; Various data cached shared collection scenario traversal up to all processor cores are combined into is accomplished, and the single operation process is following, earlier by particular thread to certain specific region; Comprise like the granularity of 64M and carry out write operation; Comprise the id that writes this thread, and then notify other threads of sharing in the set to carry out read operation, the read back results and the value of writing are compared; If the result is consistent, think this pass;
Buffer consistency affairs traversal authentication module comprises not having conflict serial affairs, two overlapping, three overlapping, calcellation retries of affairs of affairs, wherein:
Do not have conflict serial transaction validation content comprise long-rangely write back, this locality reads+long-rangely read, read long-range reading+this locality, long-range reading+long-range read, this locality is write+long-rangely read, remote write+long-rangely read, remote write+this locality reads;
Two overlapping checking contents of affairs comprise long-range write back with this locality read, long-range write back with long-rangely read, long-range read or write with this locality read or write, long-range read or write with long-range read or write occur conflicting late period, earlier conflict appears in long-range reading or writing with long-range reading or writing;
Three overlapping checking contents of affairs comprise long-range write back with long-rangely read to read with this locality, long-range reading or writing with long-range reading or writing with this locality read or write;
Calcellation retry checking content comprises that replacing sign indicating number affairs is substituted a yard affairs calcellation retry, replaces the sign indicating number affairs and long-rangely read affairs calcellation retry, replace sign indicating number affairs and read affairs calcellation retry by this locality;
All checking subitems in the buffer consistency affairs traversals authentication module are basically all when particular transaction takes place; Normally whether the Cache catalogue upgraded, whether the affairs conflict can correctly be processed, cancel, and can retry normally carry out; If normal, then think this pass;
3) proving program entrance: point out the user to select the checking item that specifically will carry out, and dispatch corresponding testing authentication item and carry out.
The invention has the beneficial effects as follows:
This method has realized buffer consistency agreement accuracy verification system-level; Can contain all application scenarioss of real system fully; Remedied the deficiency that verification method efficient low, checking cover rate variance of tradition based on analog form; Can shorten and realize buffer consistency chip design between domain processor, proving period, and can guarantee effectively that chip once throws the sheet success ratio, thereby have boundless development prospect and high technological value.
Description of drawings
Fig. 1 is the proving program Organization Chart.
Embodiment
Explanation at length below with reference to Figure of description method of the present invention being done.
Like the implementation of the buffer consistency agreement correctness verification method described in the summary of the invention, detailed process is following:
Because after computing machine gets into operating system; The core and the application of complex property of operating system are higher; Be not easy accurate processor controls behavior, therefore, need in systematic procedure, embed the buffer consistency protocol verifier for keeping proving correctness; Usually can be embedded in the bios code, after the memory subsystem initialization of system initialization initial stage is accomplished, can begin to carry out proving program.Proving program needs can each processor behavior of accuracy-control system, and supports the user to select the checking item that specifically will carry out, to user feedback checking result.
Therefore realize that the proving program of buffer consistency agreement correctness verification method is made up of following several parts, shown in accompanying drawing 1:
4) base library: comprise processor architecture module, processor flag module, caching module, internal memory operation module, digit manipulation module, latching operation module, fence synchronization module and input/output module;
The processor architecture module provides the visit to processor register, instruction-level, need support x86 and the relevant checking of itanium platform like proving program, needs to realize x86 and two kinds of processor architecture modules of ia64;
The processor flag module is used for each processor thread in the compartment system, is convenient to proving program and accurately carries out processor scheduling;
The caching module provides the instruction and the calcellation of Data Cache and writes back operations;
The internal memory operation module, provide to internal memory interval duplicate, operations such as zero clearing, read/write;
The digit manipulation module, the ability that provides the bit stages of digital to be provided with/to obtain;
The latching operation module provides various ranks (as in the domain processor, between domain processor) are locked, release, obtain the ability of operation such as lock state;
The fence synchronization module provides the ability synchronous to the multiprocessor fence;
Input/output module provides the ability to user class input response and format output;
5) testing authentication collection: comprise that memory headroom covers authentication module, the IO space covers authentication module, processor core competition authentication module, data cached shared set traversal authentication module, buffer consistency affairs traversal authentication module;
Memory headroom covers authentication module, needs all memory address spaces of traversal, travels through efficient for improving, but all threads in the dispatching system, each thread is responsible for the visit to certain section interval, and the interval sum of the traversal of all threads is the whole memory address space of system.To individual address, its address value is write this address, read back then, if consistent, then explain the visit of this address normal with the value of writing.If all address entries are all normal, can think this pass;
The IO space covers authentication module, needs all configure/status register space of traversal, IO space and interrupts the space, if the access process processor is normal, can think this pass;
Processor core competition authentication module comprises that spin lock is verified and fence is verified synchronously.Spin lock checking is the lock mechanisms that a plurality of thread execution realize based on software, if lock/release is normal, then thinks this pass; The synchronous checking of fence refers to that promptly a plurality of threads carry appointed task and get into the fence critical section, as long as abortive thread is arranged, fence just is in guard mode, if it is synchronous normally to accomplish fence, then thinks this pass;
Data cached shared set traversal authentication module needs the various data cached shared collection scenario that all processor cores are combined in the Ergodic Theory.Being specially the thread that is in shared set in advance travels through certain section memory headroom; One of them thread carries out write operation to a sector address space; All are in the thread of sharing set and carry out read operation then; All threads were all switched to after writing thread, reseted and shared the thread that comprises in the set, accomplished up to the various data cached shared collection scenario traversal that all processor cores are combined into.The single operation process is following; Earlier certain specific region (like the granularity of 64M) carried out the write operation id of this thread (as write) by particular thread; And then notify other threads of sharing in the set to carry out read operation; Read back results and the value of writing are compared,, can think this pass if the result is consistent;
Buffer consistency affairs traversal authentication module comprises not having conflict serial affairs, two overlapping, three overlapping, calcellation retries of affairs of affairs.Wherein do not have conflict serial transaction validation content comprise long-rangely write back, this locality reads+long-rangely read, read long-range reading+this locality, long-range reading+long-range read, this locality is write+long-rangely read, remote write+long-rangely read, remote write+this locality reads; Two overlapping checking contents of affairs comprise long-range write back with this locality read, long-range write back with long-rangely read, long-range reading (writing) read with this locality that (writing), long-range reading (writing) occur conflicting late period with long-range reading (writing), long-range reading (writing) earlier conflict occurs with long-range reading (writing); Three overlapping checking contents of affairs comprise long-range write back with long-rangely read to read with this locality, long-range reading (writing) read (writing) with long-range reading (writing) and this locality; Calcellation retry checking content comprises that replacing sign indicating number affairs is substituted a yard affairs calcellation retry, replaces the sign indicating number affairs and long-rangely read affairs calcellation retry, replace sign indicating number affairs and read affairs calcellation retry by this locality.All checking subitems in the buffer consistency affairs traversals authentication module are basically all when particular transaction takes place; Normally whether the Cache catalogue upgraded, whether the affairs conflict can correctly be processed, cancel, and can retry normally carry out; If normal, then think this pass;
6) proving program entrance: point out the user to select the checking item that specifically will carry out, and dispatch corresponding testing authentication item and carry out.
Except that the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (1)
1. a buffer consistency agreement correctness verification method is characterized in that the core and the application of complex property of operating system are higher after computing machine gets into operating system; Be not easy accurate processor controls behavior, therefore, need in systematic procedure, embed the buffer consistency protocol verifier for keeping proving correctness; This program is embedded in the bios code; After system initialization initial stage memory subsystem initialization is accomplished, promptly begin to carry out proving program, proving program needs can each processor behavior of accuracy-control system; And support the user to select the checking item that specifically will carry out; To user feedback checking result, therefore, the proving program of buffer consistency agreement correctness verification method is made up of following several parts:
Base library: comprise processor architecture module, processor flag module, caching module, internal memory operation module, digit manipulation module, latching operation module, fence synchronization module and input/output module, wherein:
The processor architecture module provides the visit to processor register, instruction-level, need support x86 and the relevant checking of itanium platform like proving program, needs to realize x86 and two kinds of processor architecture modules of ia64;
The processor flag module is used for each processor thread in the compartment system, is convenient to proving program and accurately carries out processor scheduling;
The caching module provides the instruction and the calcellation of Data Cache and writes back operations;
The internal memory operation module, provide to internal memory interval duplicate, the operation of zero clearing, read/write;
The digit manipulation module, the ability that provides the bit stages of digital to be provided with/to obtain;
The latching operation module provides various ranks are comprised in the domain processor, locking between domain processor, release, obtain the ability of lock state of operation;
The fence synchronization module provides the ability synchronous to the multiprocessor fence;
Input/output module provides the ability to user class input response and format output;
The testing authentication collection: comprise that memory headroom covers authentication module, the IO space covers authentication module, processor core competition authentication module, data cached shared set traversal authentication module, buffer consistency affairs traversal authentication module, wherein:
Memory headroom covers authentication module, needs all memory address spaces of traversal, for improving traversal efficient, all threads in the dispatching system; Each thread is responsible for the visit to certain section interval, and the interval sum of the traversal of all threads is the whole memory address space of system, to individual address; Its address value is write this address, read back then, if consistent with the value of writing; Then explain the visit of this address normally,, think this pass if all address entries are all normal;
The IO space covers authentication module, needs all configure/status register space of traversal, IO space and interrupts the space, if the access process processor is normal, promptly thinks this pass;
Processor core competition authentication module comprises that spin lock checking and fence verify that synchronously the spin lock checking is the lock mechanisms that a plurality of thread execution realize based on software, if lock/release is normal, then thinks this pass;
The synchronous checking of fence refers to that promptly a plurality of threads carry appointed task and get into the fence critical section, as long as abortive thread is arranged, fence just is in guard mode, if it is synchronous normally to accomplish fence, then thinks this pass;
Data cached shared set traversal authentication module needs the various data cached shared collection scenario that all processor cores are combined in the Ergodic Theory, is specially the thread that is in shared set in advance certain section memory headroom is traveled through; One of them thread carries out write operation to a sector address space, and all are in the thread of sharing set and carry out read operation then, and all threads were all switched to after writing thread; Reset and share the thread that comprises in the set; Various data cached shared collection scenario traversal up to all processor cores are combined into is accomplished, and the single operation process is following, earlier by particular thread to certain specific region; Comprise like the granularity of 64M and carry out write operation; Comprise the id that writes this thread, and then notify other threads of sharing in the set to carry out read operation, the read back results and the value of writing are compared; If the result is consistent, think this pass;
Buffer consistency affairs traversal authentication module comprises not having conflict serial affairs, two overlapping, three overlapping, calcellation retries of affairs of affairs, wherein:
Do not have conflict serial transaction validation content comprise long-rangely write back, this locality reads+long-rangely read, read long-range reading+this locality, long-range reading+long-range read, this locality is write+long-rangely read, remote write+long-rangely read, remote write+this locality reads;
Two overlapping checking contents of affairs comprise long-range write back with this locality read, long-range write back with long-rangely read, long-range read or write with this locality read or write, long-range read or write with long-range read or write occur conflicting late period, earlier conflict appears in long-range reading or writing with long-range reading or writing;
Three overlapping checking contents of affairs comprise long-range write back with long-rangely read to read with this locality, long-range reading or writing with long-range reading or writing with this locality read or write;
Calcellation retry checking content comprises that replacing sign indicating number affairs is substituted a yard affairs calcellation retry, replaces the sign indicating number affairs and long-rangely read affairs calcellation retry, replace sign indicating number affairs and read affairs calcellation retry by this locality;
All checking subitems in the buffer consistency affairs traversals authentication module are basically all when particular transaction takes place; Normally whether the Cache catalogue upgraded, whether the affairs conflict can correctly be processed, cancel, and can retry normally carry out; If normal, then think this pass;
Proving program entrance: point out the user to select the checking item that specifically will carry out, and dispatch corresponding testing authentication item and carry out.
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| CN111782217A (en) * | 2020-06-23 | 2020-10-16 | 上海赛昉科技有限公司 | System and method for quickly and efficiently generating cache consistency test C program |
| CN112055054A (en) * | 2020-08-07 | 2020-12-08 | 之江实验室 | Multi-edge cluster data synchronization method and system based on multiple consistency protocols |
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