JPH0833878B2 - Bit-slice digital processor for correlation and convolution - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bit slice digital processor for computing mathematically equivalent convolutions and correlations. This processor is a bit-level systolic array (bit-l
evel systolic array) is a type of processor formed as.

Known convolution and correlation digital processors formed as bit-level systolic arrays have been described in 1983.
UK Patent Application No. 2106287A (reference 1) published on May 7
It is described in. In this prior patent application, FIGS.
The folding means are shown in the figure. This device consists of a rectangular array of gated full adders arranged in a matrix. Each cell is only connected to the immediate row and column. That is, each cell is connected to up to four other cells. The operation of the cell is the data bit in the array,
It is controlled by a clocked latch that operates on the movement of the coefficient bit, carry bit and cumulative sum bit. Each cell evaluates the product of the input data bits and the input coefficient bits received from the right and left neighbors, respectively, and adds this product to the product of the input carry bits and the cumulative sum bit received from the right and above, respectively. Once the new carry bit and cumulative sum bit are formed, they are output to the left and down, and the input data bits and coefficient bits are moved to the right and left, respectively. Each coefficient word is a bit that sequentially circulates through each array row. Each data word traverses each row sequentially in a spiral (more precisely in a zigzag manner) to move through the array. The series of carries moves with the coefficient bits, and the series of cumulative sums moves down the columns of the array. The data moves in the opposite direction with respect to the cumulative sum formation direction and the coefficient and carry propagation directions. The cumulative sum formation is cascaded down the rows of the array to form the partial sum output from the array. Multiple partial sums with the same bit weight are sent out sequentially from the same array row and accumulated by a full adder configured to feed back the output sums to form the convolution result.

Interspersing zero bits in the data and coefficient words to avoid the generation of unwanted partial products is a disadvantage for the use of the processor described in reference 1. A processor of this kind will always have at least half of the cells in the array,
In some cases, 3/4 computes a zero partial product, so interspersing zero bits makes the array inefficient and much larger than would be needed if one could avoid zero bit interspersing. Is.

Yet another bit-level systolic array is described in British Patent Application No. 2144245A (reference 2) published Feb. 27, 1985. This prior patent application relates to an array similar to ref. 1 for performing a multiplication of two matrices with multi-bit coefficients. In this array, the row elements of one matrix propagate along the array rows in the opposite direction to the column elements of the other array, and the carry bits cycle through each cell rather than moving along the rows. It is like this. The use of so-called "guard bands" is also described, which means that the coefficient words are extended by zero bits in order to get the word growth of the accumulated result.

British Patent Application No. 2147721A (reference 3), published May 15, 1985, discloses yet another bit-level systolic array for matrix-vector multiplication. In this case the efficiency of the array is improved in two ways. First, the array outputs are accumulated such that the array portion corresponding to the inactive region of reference 1 contributes to the convolution result. Secondly, the need for zeros between data bits and coefficient bits is avoided by complex clocking means which act on bit movement on adjacent rows in alternating clock cycles. Similar to references 1 and 2, the multiplicand bits move backwards along the rows of the array. Further, as in Reference 2, the carry bit recirculates each cell, and word extension by a guard band is also used.

GEC Journal of Research, Vol.2, No.1, (1984)
By RBUrquhart and D. Wood in the static coefficie for bit-level systolic arrays.
The concept of using nts) is introduced. Each cell of the array is associated with a corresponding single bit of a coefficient and the coefficient word is associated with a corresponding array row. The cells are configured to recycle the carry bits and data is input into and moved over each array row. Cumulative sums are formed in a cascade fashion down the columns of the array, with guard bands to achieve word growth. Multiple partial products of the same bit weights may be used in various array sequences with relative delay or synchronization depending on whether the input data encounters coefficient bits in ascending or opposite bit weight order. Sent from. Such a structure provides 100% cell utilization or array efficiency without the use of complex clocking devices.

Each cell computes the product every clock cycle, and all latches are similarly clocked. Unfortunately, however, the array accumulation method as described above does not give an accurate convolution or correlation result. This is because the structure as described above has many errors in the accumulation of partial sums and carry bits corresponding to various results.

In the field of digital arithmetic circuits, it is important to unify components if possible. This is very easy to achieve if it is possible to connect or cascade multiple integrated circuits designed to perform small calculations in order to be able to perform larger calculations. It is also important to provide some degree of fault tolerance to such integrated circuit arrays in order to prevent the entire array from failing due to relatively small failures, but this is extremely difficult to achieve. this is,
Wafer scale in
It is a particularly important problem in the development field, that is, the field where the yield of wafers can be substantially zero without some fault tolerance.

One of the objects of the present invention is to provide a digital processor for correlation or convolution that can be cascaded to form a fault tolerant assembly.

The present invention provides a bit-slice digital processor that performs correlation and convolution operations on bit parallel, word serial, bit zigzag M-bit word data streams and N single-bit coefficients. According to the present invention, (1) the processor includes a logic cell array of N rows and M columns, (2) each logic cell inputs (a) a data bit, a carry bit and a cumulative sum bit, and (b) a data bit. And (c) generate an output cumulative sum bit and an output carry bit corresponding to the product of the input data bit and the coefficient bit corresponding to the cell of each row, the input cumulative sum, and the total sum of the input carry bit. (3) Interconnect lines of cells carry carry bits along rows of the array, and data streams and cascaded cumulative sums in a single direction descending along the columns of the array. And (4) the cell interconnect line includes clock excitation delay means, wherein the delay means array the data bits at a rate twice or half the rate of the cumulative sum bit. Along the row of And carry bits are transmitted faster along the rows of the array than both the cumulative sum bits and the data bits in the direction of increasing data bit weights.

It is to be understood that the term “bit rate” and its related expressions herein refer to cell crossing rate rather than physical distance traveled.

 The processor of the present invention has four major advantages.

First, all the cells are operated with real data at the time of clock excitation, so that the efficiency is 100%, and only one known non-overlapping two-phase clock is used. Unlike the prior art of Reference 1, there is no need to insert 0 bit between input data bits, and bit transmission is performed between adjacent rows or columns in every other cycle unlike Reference 2. No complicated clock control configuration is required. Second, as will be described later, it is easy to adapt to integrated circuit building blocks for constructing arrays of circuits that perform larger calculations. In particular, it may be adapted to calculations involving multi-bit coefficients by deploying one processor per coefficient bit slice and accumulating the processor outputs with appropriate adjustments of timing and bit order. In addition, the processors can be cascaded in series to accommodate large sets of coefficients, and long data words can be processed by being divided into each byte supplied to each processor. Third, because the data and result streams are configured to be unidirectional, they incorporate input data and result bypass connections divided into fast switchable sections by clock excitation latches. The processor can be designed. Cascaded series-connected processor chains can be fault tolerant without the disadvantage of reduced operating speed. This is because a faulty processor in the chain can be bypassed without limiting the speed of operation by the time constant of the total length of the bypass connection. Such a design is not possible, for example in the processor of Ref. 1, where data and results are transmitted countercurrently and the clock excitation bypass latch corrupts the calculation timing. Fourthly, it is not necessary to extend the guard band of the input data, and therefore, the disadvantage of lowering the data throughput speed does not occur.

Each logic cell may correspond to a respective stationary coefficient bit. However, preferably, additional cell interconnect lines and clock excitation delay means are provided to configure the coefficient bits to be transmitted along the rows of each array in the same direction as the carry bits and at the same rate. This facilitates coefficient programming via row coefficient input. Another advantage of such embodiments of the present invention is that coefficient programming is obtained while maintaining 100% cell utilization. For example, in Reference 3, a steady-state coefficient is required to achieve 100% efficiency.

The processor of the present invention may include programmable delay means capable of transferring the array output to the first input of the multi-bit full adder. The adder has a second input configured to receive the output from the second processor and has an output configured to be connected to the second input of the equivalent adder of the third processor. This form of processor is suitable for use as a building block that constitutes a processor array for calculations involving long data words or coefficient sets or processor arrays including multi-bit coefficients. Programmable delay means are used to adjust the relative timing of the outputs from the various processors and the difference in output bit order between the processors is corrected by the appropriate adder input connections.

The processor may be used with all positive or two's complement data and coefficients if sign bit extension is added appropriately. However, the processor still needs to operate on data that does not produce carry bits that cannot be stored in an array row. In other words, the cumulative word growth of the result must not exceed the array size. if needed,
The array size can be expanded to accommodate word growth by extending the array rows with half adders. The nth row contains log ₂ n half adders (n = 1,2 ...) Or log ₂ (n-1) adders (n = 2,3 ...) A delay means between the carry output and the sum input of the half adder of the appropriate nth row is included in the connection.

The present invention will be more fully understood from the following description in the accompanying drawings.

FIG. 1 shows a bit slice processor 10 of the present invention. Although the processor 10 is described and analyzed with respect to the operation of the correlation function, the processor is also suitable for mathematically equivalent convolution operations, as described below. Processor 10 is a continuous 4-bit number with individual bits x ▲ ^b _n ▼ (b = 0-3) x
It is configured to calculate the correlation between the _n (n = 0, 1, 2, ...) Data stream and the four 1-bit coefficients a _i (i = 0 to 3). In this explanation example, the data and the coefficient have positive values.

Processor 10 includes a gated full add logic cell array 12 arranged in 4 rows and 4 columns. Each cell is indicated by reference numeral 14, and the subscript of each cell indicates the position of the row and column. For example, cell 14 _ij is the cell in the i-th row and the j-th column. The processor further includes five half-addition logic cells 16, which also subscript to indicate row and column locations.

2 and 3, each logic cell 14 is configured to compute a gated full add logic function as follows.

y ← y '(ax) c' (1.1) c ← y'.c '+ y' (ax) + c '(ax) (1.2) [where y'and y are the cumulative sum bits of the input and output, respectively] , C'and c are input and output carry bits respectively, a is an input 1-bit coefficient, x is an input data bit, -subscripts for bit digits and number of words are omitted for clarity.

Each logic cell 14 is configured to receive the input data bit x and the input cumulative sum bit y'from the immediately adjacent cell. Further configured to receive the input coefficient bit a and the input carry bit c from the cell to the immediate right, the cell operates the logical functions of equations (1.1) and (1.2) to produce the output cumulative sum bit y and the carry. Generate bits c and. These output bits correspond to the sum of the product of a and x plus c'and y '. The carry output bit a and the coefficient output bit c are output to the cell on the left side via the respective clock excitation latches 18a and 18c. The data output bit x and the cumulative sum output bit y are routed through one clock excitation latch 18x if x and two clock excitation latches 1 if y.
It is output via 8 _y1 and 18 _y2 .

As shown in FIG. 3, each half-addition cell 16 receives the carry and cumulative sum input bits c'and y'from the cells to the right and immediately above.
Respectively received. The cell adds these to generate carry and cumulative sum output bits c and y, which are output to the cell to the immediate left and directly below via clock excitation latches 20c, _20y1 and _20y2 . The half addition cell 16 operates the following logical function.

y ← y′c ′ (2.1) cy ′ c ′ (2.2) Each term in the formula has the same meaning as above.

Each of the latches 18, 20 is excited by one clock 22 (not shown in FIG. 1) that controls the timing of all cells 14 of array 12 and half adder 16. Clock 22
Generates non-overlapping two-phase signals, each latch 18
Or 20 consists of two half latches in series. On the first phase clock pulse, each of the second half-latch outputs a latch bit and each of the first half-latch inputs a new latch bit. On the second phase clock pulse, each of the first half-latch transfers the latch bit to its own second half-latch. Thus, consecutive bits are clocked in each latch during consecutive clock cycles. Although cells 14 and 16 have all latches at their cell outputs, such as 18a, they may be placed at the cell inputs or may be split by half latches at the inputs and outputs, respectively, to maintain similar array operation. It
It is also known to use half latches instead of each full latch, which is a variant of the embodiment described. The operation of such a latch is well known in the bit-level systolic array industry and is shown in FIGS. 10 and 11 of reference 1 and will not be described further herein.

The clock control effect of the latches 18 and 20 is the coefficient bit a
And carry bit c successively calculated, one cell per clock cycle along the rows of the array, as indicated by arrows 24 and 26. The data bit x moves by one cell every clock cycle. Although the coefficient and data bits pass through the array 12 unchanged, each newly calculated carry bit is calculated one bit above one level, which is calculated one clock cycle later by the cell 14 or 16 to the left. Will be input.

Each of the newly calculated output cumulative sum bits y becomes the input y'of the cell 14 or 16 immediately below after two clock cycles. Other bits are one latch 18a, 18c, 18x or 20c
This is because each of these bits passes through two latches 18 _y1 and 18 _y2 or 20 _y1 and 20 _y2 while only passing.

The processor 10 includes four logic cells 14 ₁₂ only five that is fully connected to the adjacent cells, 14 _11, 14 _22, 14 ₂₁ and 16 _24. Cell 14 _{00-14 03,} 16 _14, and 16 ₂₅ y 'input O
Is set to C 'input cell 14 _{00-14 30} is set to O. Cell 14 _{03-14 33} has a coefficient i.e. a output unconnected, cell 14 _03, 16 _14, 16 _25, and 16 ₃₅ have the c output unconnected. X output of the cell 14 _{30-14 33} is not connected. The cell 14 _{00-14 03} of the first row has x input, data bits in parallel as will be described later, from the input, word serial, is supplied to the processor 10 in a bit zigzag. Cell 14 _{00-14 30} in the first column with a input supplied by a coefficient processor 10. The output from the processor 10 is obtained from the y output of the cell 14 _{30-14 35} of the last row.

In the actual design of processor 10, redundant cell connections and corresponding latches may be omitted. However, it would be advantageous to have as few logic cell types as possible. If the redundancy is minimized, it is only necessary to incorporate two types of cells in the processor 10. Furthermore, the use of a gated full adder 14 with a and / or x inputs set to O instead of half adder 16 results in less redundancy but requires the use of only one type of cell. Therefore, there is an advantage that the integrated circuit can be easily manufactured by a design technique using a computer, for example. As described further below. In this complement operation, it is more advantageous to construct a rectangular array of gated full adder cells than to leave a space on the upper left side as in the processor 10 of FIG.

Next, the operation of the processor 10 will be described with reference to FIGS. Processor 10 is configured to perform a correlation operation defined by the following equation.

[Where Y _n is a continuous correlation result word, and coefficients a _i and x _{n + 1} are
Indicates a general data word in the range x _{n to} x _{n + N-1} ].

According to FIGS. 4, 5 and 6, single-bit coefficient words a _{0 to} a
The stream 40 of ₃ is transferred leftward in the processor 10. Each coefficient is entered in its respective correlation row. The data stream 42 moves downward within the processor 10 and the result stream 44 is the processor as shown in FIGS.
Exit below 10. FIG. 4 shows the processor 10 immediately before the first clock cycle of operation, and FIGS.
The bit positions of the data and the result in the 11th cycle and the 14th cycle are shown. 4 to 6 graphically show the timing of the data and coefficient flows and the accumulation of the results.

Successive bit positions that extend above or to the right of processor 10 indicate progressively slower data inputs, result outputs or coefficient inputs. The diagonal rising edges 40 ', 42' and 44 'of the coefficient, data and result streams 40-44 represent time zigzag bit inputs to the processor 10. The data word x _{n + i} is input to the processor 10 in word serial, bit parallel and cumulative time zigzag. Therefore, the bit ▲ x ⁰ ₀ ▼ ~
▲ x ³ ₀ ▼ is entered in cell 14 _{00-14 03} of the first row is accompanied with delay of one clock cycle between adjacent cells. Thus the input to the cell _{14 0n (n = 1~3) ▲} x n 0 ▼ input to the cell 14 ₀₀ ▲ x ^{₀ 0} ▼ to delayed by n clock cycles.

The logic function of formula (1), after one clock cycle from Figure 4, i.e., cell 14 ₀₀ clock cycles 1 receives an input ▲ x ⁰ ₀ ▼ and a _0. As a result, this cell is the product a ₀
Calculate x ⁰ ₀ and add to it the carry and sum input bits, c'and y '. These are always 0. Therefore, the corresponding cumulative sum output y is a ₀ ▲ x ⁰ ₀ ▼ and cell 14 ₀₁
The carry output c to will be zero. Clock cycle 3,
In 5 and 7, cells 14 _{10 to} 14 ₃₀ have data input ▲ x
⁰ ₁ ▼, ▲ x ⁰ ₂ ▼ and ▲ x ⁰ ₃ ▼ are received, and a ₁ , a ₂ and
Multiply each a ₃ . The corresponding carry inputs are all 0, but each cell 14 _n0 (n = 1 to 3) uses the cumulative sum output calculated by the cell 14 _{(n-1) 0} immediately above two cycles as the cumulative sum input. To receive. The two cycle delay is provided by the respective latches 18 _y1 and 18 _y2 . Therefore, cell 14 ₁₀ receives a ₀ ▲ x ⁰ ₀ ▼ from cell 14 ₀₀ in cycle 3 in synchronization with the input of multiplicand a ₁ and ▲ x ⁰ ₁ ▼, Generate the y and c outputs consisting of the least significant bit (lsb) and the higher order bit (hob). Carry bit c moves to cell 14 ₁₁ in cycle 4, the cumulative sum output bits y moves to cell 14 ₂₀ in cycle 5. Cell 14 ₂₀ in cycle 5 Y and c are generated as lsb and hob of. c moves to cell 14 ₂₁ in cycle 6, y moves to cell 14 ₃₀ in cycle 7. This is synchronized with the inputs of the multiplicand a3 and ▲ x ⁰ ₃ ▼. Therefore the y and c outputs of cell 14 _{30 in} cycle 7 are Lsb and hob. The cumulative sum output of cell 14 _{30 in} cycle 7 is given by:

Expression (4) is equivalent to the following expression.

Equation (5) is the l of Y ₀ , which is the first correlation term of the series Y _n (n = 0,1 ...).
sb. Therefore, the cells 14 _{00 to} 14 ₃₀ in the rightmost column generate lsb ▲ y ⁰ ₀ ▼ of Y ₀ after 7 clock cycles from FIG.
Since there are two latches in series with the cumulative sum output, ▲ y ⁰ ₀
▼ is sent out from the latch 18 _y2 of the cell 14 ₃₀ after 8 clock cycles from this figure.

Next, consider the cells 14 _{01 to} 14 _{31 in} the second column. In cycle 2, cell ₁₄₀₁ inputs c'and y'input 0 by ▲ x ¹ ₀ ▼ and a
₀ Receive with multiplicand input. Therefore, the cell generates a carry output 0 for the cell ₁₄₀₂ on the left side, and the cell immediately below
Generate y output a ₀ ▲ x ¹ ₀ ▼ for 14 ₁₁ . Cycle 4,
In cells 6 and 8, cells 14 ₁₁ , 14 ₂₁ and 14 ₃₁ are respectively a ₁ / ▲ x ¹ ₁ ▼, a ₂
/ ▲ x ¹ ₂ ▼ and a ₃ / ▲ x ¹ ₃ ▼ are received. Therefore, the y output of the second latch 18 _y2 of cell 14 _{31 in} cycle 9 is given by:

That is ▲ y ¹ ₀ ▼ is the bit of the next-higher-order digit of Y ₀ , and is transmitted from cells 14 _{01 to} 14 ₃₁ in the second column in cycle 9 or lsb ▲ y ⁰ ₀ from the cells in the first column. It is sent after one clock cycle of ▼.

(Y ¹ ₀ ) The carry bit generated during formation is transferred to the cells 14 _{02 to} 14 ₃₂ in the third column according to the following equation. Cycle 3,
cell 14 ₀₂ : c '= 0 (8.1) By the same analysis, ▲ y ² in cycle 10 and cycle 11
₀ ▼ and ▲ y ³ ₀ ▼ occur from the cells in the third and fourth columns,
It will be appreciated that at the same time the carry bit is transferred to the left as described above.

The c'and y'inputs to the cells in the first row are all always 0. The maximum value of the product obtained by multiplying an arbitrary 4-bit number by a ₀ (equal to 1 or 0) has the same number of 4-bit length. Thus c output of the first row of the last cell 14 ₀₃ is always zero. The c output of the last cell 14 ₁₃ of the second row may be non-zero because it is obtained by adding two 4-bit numbers. Half add cell 16 ₁₄ is configured to transfer this carry bit to the third row of the array. It is necessary to use two carry bits because the third and fourth rows add three and four 4-bit numbers, respectively, which can be added to 6 bits respectively. Generally, the Nth correlation row (N = 1,2,3 or 4) has log ₂ to add carry bits that travel horizontally.
N half adder needs to be incorporated. However, log ₂ N may be rounded to an integer if necessary. This effect is shown in FIG. In FIG. 6, the bits of the fourth and fifth digits, that is, ▲ y ⁴ _n ▼ or ▲ y ⁵ _n ▼ (n = 0,1,2 ...) are the fifth column and the fifth column, each consisting of a half adder. Calculated by 6 columns.
A single clock control latch may be used in place of the half adders 16 ₁₄ and 16 ₂₅ to reduce the size of the circuit. These latches have the function of independently providing a delay when the input sum and the output carry are not connected. Therefore, in general, the Nth correlation row is the log ₂ (N-1) half adder [where N = 2,3, ...].
Would require. In cycles 12 and 13, the final two bits ▲ y ⁴ ₀ ▼ and ▲ y ⁵ ₀ ▼ are generated from the half-added cells 16 ₃₄ and 16 _{35 in} the last row of the fourth and fifth columns, respectively.

From the above analysis, it can be seen that the bit ^p y ^p ₀ of the Y0 occurs from the p th column of the cell after (p + 8) cycles from FIG. [However, p = 0 to 5]. By expanding this analysis, it can be easily proved that the p-th bit {circle around (y) ^p _n }} of Yn (general correlation result) is generated from the cell in the p-th column after (n + p + 8) cycles from FIG. Therefore, the continuous correlation result Y _n is generated from the processor 10 in word serial and bit parallel with a waiting time of 8 clock cycles. That is, it takes 8 cycles from inputting the corresponding data bit to obtaining the result bit.

The embodiment of the invention described with reference to FIGS. 1 to 6 is a processor that uses moving single bit coefficients. This type of processor is suitable when it is desirable to occasionally swap coefficients to compute various correlations. However, if a constant correlation is always required, then each cell will have a stationary and possibly pre-programmed coefficient respectively. In this case, inter-cell connections and latches for coefficient transfer would be unnecessary.

Referring again to FIG. 4, it will be appreciated that there is a small number of spurious terms preceding the output of the correct computation result from processor 10. In particular, cell 14 ₃₀ will calculate the relationship between a ₃ and Δx ⁰ ₀ 4 cycles after the illustrated cycle, which is a meaningless result. It is necessary to ignore the result from cell 14 ₃₀ during the first 7 cycles of the operation, ignore the result from cell 14 ₃₁ during the first 8 cycles, and so on. For this purpose, if necessary, means may be provided, which in each case are arranged to suppress the output during a suitable number of cycles. However, in practice, the processor 10 performs operations over a very large number of cycles, typically more than 10 ⁶ .

Therefore, it does not matter if there are some meaningless results of the first short series out of the millions of results. This only corresponds to the circuit setting time known in the digital arithmetic circuit industry.

As a modification of the method of ignoring the initial result, the coefficient input corresponding to the unnecessary term may be set to 0 as shown in FIG. To do this, the coefficient a _{n in the nth} row of the processor 10
It is necessary to input 2n 0s (n = 0 to 3) before inputting. In other words, the number of 0's required before inputting the coefficient increases by 2 each time the line is lowered in the processor.
Therefore, do not enter 0 in the first line. It also shows how to exchange coefficient sets without introducing unnecessary terms. coefficient
In order to exchange a _{0 to} a ₃ for the coefficients b _{0 to} b ₃ , two clock cycles after the a _n-1 of the (n-1) th row is exchanged with b _n-1 , the _nth row is replaced. Swap the input of a _n into b _n . FIG. 4 shows the case where the coefficient is exchanged from 0 to a _{0 to} a ₃ .

Next, referring to FIG. FIG. 7 is a schematic diagram of another processor 50 of the present invention, wherein the preceding parts are designated by the same reference numerals. It incorporates a processor 10 with auxiliary means to accommodate more complex calculations. Cell 14 in the last row
_{30-16 35} has a cumulative sum output 30, this output is connected to 11 bit clock excited full adder 54 through a programmable clock excitation delay unit 52. Data output 28 of the last row are connected to the data output line 56 _{0-56 3.}
The adder 54 has one bit adder cell 58 _{0-58 10} separate eleven, one of which is shown in more detail in Figure 8. Each summing cell 58 has first and second sum inputs 60a, 60b, a carry input 62, a carry output 64 and a sum input 66. Japanese input 60
a, 60b and carry input 62 are clocked respectively 1
Bit latch 68 _a, which is 68 _b, 68 _c in series. The carry bit is transferred to the left along the adder 54, for example, from the addition cell 58 _n to the addition cell 58 _{n + 1} (n = 0 to 10). Summing cell 58 _n receives and generates the bit of the n th digit and has a first input connected to receive the output from array cell 14 _3n (n = 0 to 3) or 16 _3n (n = 4 or 5). With 60a. The first input of the adder cell 58 _{6-58 10} is set to 0. Therefore, the processor 10 provides the least significant 6-digit first input to the 11-bit adder 54.

The second input 60b of the summing cells 58 _{0 to} 58 ₁₀ is the input line 70 _{0 to} 7
0 to ₁₀ respectively. The adder output 66 is connected to the output line 72 _{0-72 10} each. Delay unit 52 is similarly configured to delay the signal from each of the cells in the last row of processor 10 by a programmable number of clock cycles. Unit 52 includes, for example, a 1-bit clock excitation latch in series for each output of the array, the number of serial latches being variable depending on the desired delay.

Processor 10, delay unit 52, and all latches of adder 54 are synchronously excited by the same two-phase clock (not shown).

The processor 50 performs the following operations. Since the correlation is an addition operation, it is possible to divide the operation into sub-computations and rejoin them later if the correct timing and bit digits can be given. The delay unit 52 provides accurate timing and the 11 bit long adder 54 provides bit digit adjustment. This will be described later in each case. Processor 50 is configured to be used with a similar group of clocks all excited by the same two-phase clock.

If necessary correlation comprising a single bit coefficients a ₀ ~a ₁₁ of 12, using the three processors 50. Data is introduced into the first processor is transferred to the second processor via the data output lines 56 ₀ to 56 ₃ passes through the first processor.
The data stream is bit parallel, bit zigzag and word serial as described above. Similarly, the second
The data output of the processor becomes the input of the third processor. The first processor operates with the coefficients a _{0 to} a ₃ , the second processor operates with the coefficients a _{4 to} a ₇ , and the three processors operate with the coefficients a _{8 to} a ₁₁ . The delay unit 52 of the three processors has a first
The output of the processor is delayed by 14 clock cycles, the output from the second processor is delayed by 7 clock cycles, and the output from the third processor is set to delay 0. The second inputs 60b of the first processor adder 54 are all set to 0 and their output lines 72 _{0 to} 72 ₁₀ are line 70 _0.
~ 70 ₁₀ via the second input of the second processor adder 54, respectively
It is connected to 60b. Similarly, the second processor adder 5
The output lines 72 ₀ to 72 ₁₀ 4 is connected to the input line 70 _{0-70 10} of the third processor adder, the output line gives the desired correlation result.

It can be verified as follows that such an arrangement of three processors 50 provides the desired twelve coefficient calculations. Again first
With reference to the figures, the processor 10 requires 8 clock cycles to produce one result, ie two cycles for each row. A similar processor with 12 rows would require 24 cycles to produce one result. Dividing the latter processor into three 4-row processors that receive the same data sequentially, the first processor gives the result after 8 cycles, the second processor gives the result after 16 cycles and the third processor after 24 cycles. . Therefore, there is a relative delay of 8 cycles between the outputs of adjacent processors. In addition, each 11-bit adder 54 has a clock control latch, so one clock cycle is required to perform one addition. The effect of adder 54 is to reduce the relative delay by one clock cycle per stage. Therefore, each of the processor delay units 52 must introduce a number of clock cycle delays equal to the product of the number of subsequent processors and seven. Therefore, the delay units 52 of the first and second processors need to provide delays of 14 clock cycles and 7 clock cycles, respectively. More generally, the delay unit of the nth processor in a chain of N processors, each having M rows, has a delay of (2M-1) (N-n) clock cycles [where n = 1 to N]. Is set to have.

For three processors 50 each providing a 6-bit output, the maximum value of the sum input is 8 bits. This is an adder
3 bits less than the width of 54. Thus, longer processor chains can be accommodated.

Also, multi-bit coefficients may be stored by multiple processors 50. For example, for a 3-bit coefficient, three processors 50 are used. First processor is ms for each coefficient
b (most significant bit) is received, the second processor receives the bit of the next uppermost digit, and the third processor receives lsb
Receive (least significant bit). Therefore, the coefficient set for each processor is a respective bit slice of the multi-bit coefficient set. The data stream is synchronously fed to all three processors in parallel, symmetrically with the serial data stream arrangement. The third processor produces outputs of bit digits 0-5, the second processor produces outputs of 1-6, and the first processor produces outputs of 2-7. This is because these processors multiply the coefficient bits in digits 0, 1 and 2, respectively. To correct for different bit digit, the first processor adder output lines 72 ₀ to 72 ₉ are respectively connected to the adder input line 70 _{1-70 10} of the second processor. The output line 72 ₁₀ of the first processor is unconnected and the input line 70 ₀ of the second processor is connected to 0. A similar connection is made between the adder output of the second processor and the adder input of the third processor to perform the add shift of the bit digit. This causes the outputs of the first and second processors to have a two-step and one-step bit digit shift with respect to the output of the third processor, respectively. As a result, for example, the output of the first or rightmost column of the first processor is added to the outputs from the second and third columns of the second and third processors, respectively. However, referring again to FIG. 5, there is a relative delay of one clock cycle between the outputs of adjacent columns of processor 10. A similar delay exists, for example, between the output of the second column of the second processor and the output of the first column of the first processor, since the data is supplied synchronously to all three processors. On the other hand, the output of the first processor is delayed by one cycle in the output adder 54, and the output of the second processor is delayed by another cycle in the adder of the second processor. Therefore, both processors produce an appropriate delay to correct the timing of the addition to match the output of the third processor.

Therefore, the delay units 52 of all three processors are set to delay 0.

The maximum value obtained by adding three numbers of 6 bits, 7 bits and 8 bits has a length of 9 bits, which is the third value.
Easily housed within 11 bits of the processor output adder.

Also, while the processor 10 described above is only suitable for 4-bit data, it may be necessary to use data words wider than 4 bits. Multiple processors 50 may be used, although wider arrays may be used. 8
Two processors 50 are used for bit data words. The upper 4 digits are supplied to the first processor and the lower 4
The digit bits are provided to the second processor. The adder output lines 72 _{0 to} 72 ₆ of the first processor are connected to the adder input lines 70 ₄ to 70 ₁₀ of the second processor, and the first output line 7
2 _{7 to} 72 ₁₀ are not connected and the second input lines 70 ₀ to 70 ₃ are 0
Is set to As a result, a 4-stage relative shift of bit digits is performed. The adjustment of the relative delay follows the data input timing. If data for all eight bits is input with a one-bit time zigzag between adjacent bits, then only an adjustment to the relative delay of one clock cycle introduced by the first processor adder is required. In this case, the second processor delay unit 52 is set to give a delay of one cycle. However, if bit zigzags are present only in each 4-bit word portion and the inputs to both processors are synchronous, the output of the first processor will require a 4-bit delay. To obtain this, the first processor delay unit 52 is set to provide a delay of 3 cycles and the second processor delay is set to zero. As a modification of this, by providing an input data delay, a structure having an equivalent output delay effect can be obtained.

As a variant to the use of the delay unit 52, a similar delay unit is connected in series with the second inputs 70 ₀ to 70 ₁₀ of the adder 54,
Alternatively, it may be arranged in series with the adder outputs 72 _{0 to} 72 ₁₀ . The number of delay clock cycles required depends on the position of the delay unit.

In this configuration, the second processor provides the output of the sum of the 10-bit and 6-bit words. It has a maximum value of 11 bits. Therefore, in this example, the full width output adder
54 is needed. A larger output adder (4N + 3) bit width would be required, at least in the final processor, when it was necessary to perform an operation involving a 4N-bit wide data word. However, each individual logic cell array need only have the cells 14 and 16 shown in FIGS. This shows the advantage of stage-by-stage accumulation with an output adder such as 54. Each logical cell array has four processors 10.
It need only be configured to accommodate a limited amount of word growth such as. Larger operations are separately accumulated using the output adder.

From the above description, data word length extension, multi-bit coefficient use and correlation length extension are all
It will be appreciated that this can be obtained by using a suitable number of processors such as Technically, combinatorial processor
The first output adder 54 at 50 is not needed. However, in designing a digital arithmetic circuit, it is convenient to standardize in this case to one building block each including an output adder.

FIG. 9 is a schematic explanatory diagram of another processor 90 of the present invention. This is a processor equivalent to the processor 50 of FIGS. 7 and 8 with bypass means added, and the equivalent parts are designated by the same reference numerals. Many line connections are shown as buses to avoid overcomplicating the figure. Processor 90 includes processor 50. The input data bus 92 is connected to both the processor 50 and the first multiplexer 96, the latter having two clock excitation delay latches 94a,
It is connected through a bank of 94b. The data output from processor 50 enters multiplexer 96 via bus 98. The multiplexer 96 has a data output bus 100. The multiplexer 96 determines whether the signal at the control input 102 is 0 or 1
Output bus 100 to bus 92 or 98, depending on

The resulting input bus 104 is connected to both the output adder 54 and the second multiplexer 106, to the latter via a bank of two clock excitation delay latches 108a, 108b. The second multiplexer 106 is also connected to the adder output bus 110 and the resulting output bus 112. The result output bus 112 is either the result input bus 104 or the result output bus 1 depending on whether the signal at the control input 114 is 0 or 1.
Connected to 12.

The processor 90 of FIG. 9 operates as follows. It is configured as part of a chain of similar processors, two adjacent processors are shown by dashed lines 116 and 118. Multiplexers 96 and 106 when processor 50 is fault-free
A control input signal of logic 1 is supplied to and the operating mode is the same as above. However, if the processor 50 fails, a logic 0 control input is provided to the multiplexers 96, 106 and the input data and results are bypassed from the processor 50 via the latch banks 94a, 94b, 108a and 108b. Each latch bank provides a one cycle delay for each line of the corresponding bus. The individual latches (not shown) are equivalent to the latches and are excited with the same clock used by the processor 50.

Therefore, the faulty processor 50 is bypassed through the latch bank which introduces a two clock cycle delay in the data and result streams. Therefore, the data stream and the resulting stream experience equal delays and remain synchronized as before. Most importantly, each of the bypass buses is divided by latch banks into three relatively short sections. If desired, additional bypass latches may be inserted for further subdivision. The advantage is that each section of the bypass bus is short enough to switch at least at the same clock frequency as the processor 50. Processor 50 can be manufactured using current integrated circuit technology and can operate at high clock frequencies above 20 MHz. The reason why it can operate at a high clock frequency is
This is because, for example, the connection between the logic cells 14 and 16 in FIG. 1 exists only between adjacent cells. However, the length of the bypass bus is inevitably delayed significantly, and the RC
The time constant becomes large. Such a time constant limits the maximum frequency of the serial processor chain to an undesirably low value. Therefore, if the bypass bus is not subdivided into fast switchable sections, bypassing the faulty processor will cause a sharp drop in maximum clock frequency. If the frequency decreases below the frequency of clock 22 in FIGS. 2 and 3, the serial chain will not work even if one processor is bypassed. Therefore, by using the bypass bus subdivided into fast switchable sections by the clock excitation latch, it is possible to construct a fault tolerant processor without adversely affecting the operating speed.

A typical fault tolerant processor chain is, for example, five processors in series for operations that require four processors.
It incorporates 90. Therefore, any one failed or unnecessary processor can be bypassed. Additional processors may be added when greater fault tolerance is required. The conventional processor as described in Reference 1 cannot use such a configuration that obtains a fault tolerance range without reducing the operation speed. The reason is that according to the invention, the data and the result pass through the processor 10 or the chain processor 90 in the same direction. Bypass latches delay the data stream and the result stream equally and no relative delay is introduced between them. Thus, the bypassing of a failed processor maintains the relative timing of the data and result streams from the preceding processor to the subsequent processor in the chain. The processor described in reference 1 is designed so that the data and the result move countercurrently. In such a chained device, the central processor receives data from one adjacent processor and results from the other adjacent processor. When bypassing one of these adjacent processors with a latched bus, either the data stream or the result stream is delayed at the central processor, but not both.
Therefore, the calculation timing is destroyed and meaningless results occur. As a result, the structure of fast fault tolerant processor chains cannot be obtained by using prior art countercurrent architectures. In order to obtain such a structure, it is necessary to use the processor of the present invention that is configured to produce a unidirectional data stream and resulting stream. This is an important advantage of the present invention. Currently, integrated circuit technology is moving to wafer scale integration, where a fast fault tolerant architecture is essential. Without some fault tolerance, wafer scale circuit efficiency is substantially zero. Because one wafer with hundreds of devices
This is because the operation of the entire wafer is invalidated when one defective element occurs.

Now referring to FIG. In FIG. 10, elements equivalent to those in FIG. 2 are designated by the same reference numerals with 200 added. This is a modified gated full adder logic cell 214 suitable for use in the processor 10, 50 or 90. Only cell 214 and cell 14
The only difference is that cell 214 has two data output latches 218 _x1 and 218 _x2 and only one result output latch 218 _y . Cell 214 is used in a processor (not shown) with exactly the same interconnections as cell 14 of FIG. In the processor incorporating the logic cell 214, the result is 2
Move at twice the speed. Coefficient input to the processor is performed in the reverse order of FIGS. For example, the correlation coefficient a ₀ ~
a ₃ is not cells 14 _{00 to} 14 _{30 as} shown in FIG. 4, but cells 14 _{30 to} 41.
Input to _{00 respectively} . It will be appreciated by analyzing the operation of the processor as before that the correlation calculation can be derived from the flow diagram of the coefficient input to the processor incorporating cell 214. This analysis is the same as above and will not be described here. The method of exchanging coefficient sets is slightly different. That is,
In FIG. 4, a two clock cycle delay is introduced for the exchange of coefficient sets between adjacent rows, whereas in FIG. 10 a one clock cycle delay is introduced. To compensate for the slower data flow and faster result flow, arrays of processors 50, 90 incorporating cells 214 require adjustment of result accumulation timing as compared to the previous array. The necessary adjustments will be clear to the person skilled in the art of digital electronics and will not be described here.

The processor of the present invention is configured to operate with two's complement data and / or coefficients. The embodiments described so far use a 4-bit data stream. If this were two's complement, then it would be necessary to duplicate the sign bit or most significant bit until each input data word had the same width as the output result. Therefore, 6 bits of input data would be required. More specifically, 2 with bit abcd
A four-bit data word in one's complement form is designated aaabcd. Processor 10 does not receive a 6-bit input. Instead of the 4 × 4 gated full adder array and 5 half adders of FIG. 1, a 4 × 6 gated full adder array is used with the interconnections of FIG. 4 such arrays
Similar to the processor 50 that operates all positive data in bits, two complement data code bits extended to 6 bits are operated in 4 bits. Generally, the shape of the required array is rectangular, and the number of cells in each row is equal to the bit width of the output result from the last row.

Further, the complement data may be stored in a multiple processor configured as shown in FIGS. 7, 8 and 9. It is necessary to provide a sign extension for the result supplied to one output adder equivalent to adder 54, and for the one byte input data or the most significant byte divided into multiple bytes for separate processing. . In particular, the result containing the sign bit entering the output adder must be sign extended to the full width of the overall result. The total result is obtained from the final output adder of the set processor.

This complement factor may also be used in the processor of the present invention.
For single-bit coefficients, the multiplication is done by 0 or 1 and the latter is negative. The result is completely negative because 0 gives no positive contribution. Therefore, the calculation is equivalent to the case of all positive coefficients. For multi-bit coefficients, only the top-level processor contains negative coefficients and the result is completely negative. This complement of this result is used by known gate control means to sign extend to the full width of the overall result before it is input to the final output adder.

The principle of the digital arithmetic circuit for this complement is well known and will not be described in detail here.

A multiple processor, similar to processor 50, incorporates a rectangular array of gated full add cells, each containing a number of cells in each row equal to the bit width of each result.
This complement data can be used. If the input data is split into individual bytes for separate processing, the most significant bit of the output result of the processor receiving the most significant byte will be the most significant result, ie the least significant equivalent of adder 54 of FIG. The sign is extended to the full width of the result output from the high-order output adder.

Although an embodiment of the invention has been described with respect to correlation, it can also be used for convolution. This is described in Reference Document 1, for example, and is calculated as follows. The convolution operation is defined by the following equation.

The correlation calculation is defined by the following equation.

From the equation (9), the fifth convolution result Y ₄ of the 4-point calculation (N = 4) is given as follows.

Y ₄ (convolution) = A ₀ X ₄ + A ₁ X ₃ + A ₂ X ₂ + A ₃ X ₁ (11) From the equation (10), the second correlation result Y ₁ of the 4-point calculation is given as follows.

Y ₁ (correlation) = A ₀ X ₁ + A ₁ X ₂ + A ₂ X ₃ + A ₃ X ₄ (12) The order of the right side of the equation (12) is reversed and B _i = A _3-i , i = 0 to
Substituting 3, Y ₁ (correlation) = B ₀ X ₄ + B ₁ X ₃ + B ₂ X ₂ + B ₃ X ₁ (13).

Equations (11) and (13) are equivalent, indicating that convolution and correlation are equivalent mathematical operations. Convolution of data with a set of coefficients is equivalent to correlation of the same data with the same coefficients in reverse order. For a given coefficient set A ₀ -A _k , the processor of the present invention performs a convolutional operation or a correlation operation depending on whether the coefficient word A ₀ is input starting from the first row or the last row. The reverse is used for a processor incorporating cell 214 of FIG. There is a slight difference that the first few terms of the convolution result series are not in the corresponding correlation series. For example, equation (10) becomes (9)
Y ₀ to Y ₂ cannot be generated. However, for practical purposes this is not important for digital arithmetic circuits, which are used to produce a very large number of results, so some results may be added or missing at the beginning of the millions of classes, for example. May ignore this as well.

[Brief description of drawings]

FIG. 1 is a schematic illustration of a processor of the present invention configured to perform a correlation operation, and FIGS. 2 and 3 are detailed views of the gated full adder and half adder cells of the processor of FIG. 1, respectively. FIGS. 4, 5, and 6 are explanatory views showing the timings of the data flow and the result in each clock cycle in the processor of FIG. 1, and FIG. 7 constitutes a processor array for a large computer. FIG. 8 is a schematic explanatory view of a processor of the present invention including the processor of FIG. 1 together with output delay means and solution accumulation means for the purpose of FIG. FIG. 9 is a schematic explanatory diagram of the processor of FIG. 7 with a bypass connection necessary for constructing a fault tolerant processor array, and FIG. 10 is a modification of the gated full adder cell used in the processor of FIG. FIG. 10 ... Processor, 12 ... Array, 14 ... Logic cell, 16
…… Half addition cell, 18,20 …… Latch, 22 …… Clock, 5
2 ... Delay unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Lichyard Anthony Evans United Kingdom, Hereford Oshcher H.A.R.8.1.1 J.J.A.G.A., Redberg, Codeineton, New Craft (No house number) (72) Inventor John Graham McWurter England, Worcestershire D'Abriille Earl 14/4 Pies, Wells, Albarn, Moorlands 27

Claims (8)

[Claims] 1. A digital processor for performing correlation and convolution operation of a bit parallel, word serial, bit zigzag M-bit word data stream and N single-bit coefficients, comprising: (a) a processor having N rows and M columns. (B) Each logic cell inputs (i) data bit, carry bit and cumulative sum bit, (ii) outputs data bit, and (iii) input data bit and cell of each row. (C) interconnection line of cells, which is configured to generate an output cumulative sum bit and an output carry bit corresponding to a product of corresponding coefficient bits, an input cumulative sum, and a total sum of input carry bits. Are configured to transmit bits through rows and columns, the lines including clock excitation delay means for storing and transmitting the bits. The cell interconnect lines and the delay means are such that the cumulative sum bits and the data bits are transmitted at a rate such that one rate is twice the other rate in a single direction down the columns of the array. And a carry bit is configured to be transmitted faster along the rows of the array than both the cumulative sum bit and the data bit in the direction of increasing the weight of the data bit. Prossessa. 2. An additional cell interconnection line configured to transmit coefficient bits along a row of the array at a transmission rate and a transmission direction of a carry bit and a clock excitation delay means. A processor according to claim 1. 3. A programmable clock excitation delay means configured to delay the array output, and a multi-bit clock excited full adder configured to add the delayed array output to a second summing input. The processor according to claim 1 or 2. 4. A bypass connection for input data and a second summing input, the connection being subdivided by a clock excitation latch.
Processor according to paragraph. 5. Processor according to claim 3 or 4, characterized in that the width of the full adder is sufficient to accommodate the relative difference of the bit digits between the inputs. 6. Processor according to claim 5, characterized in that the width of the full adder is sufficient to accommodate the relative difference of the bit digits of M bits. 7. A log ₂ n half adder on the extension of the nth row of logic cells, wherein n is from 1 to N and log ₂ n is rounded to an integer if necessary. The processor according to any one of the first to sixth terms. 8. A log ₂ (n- on the extension of the nth row of the logic cell.
1) a half adder, including a connection with delay means between the carry output of the (n-1) th row and the sum input of the appropriate nth row half adder, where n is 2 to N Yes Log ₂ if required
The processor according to any one of claims 1 to 6, wherein (n-1) is rounded to an integer.