JPH08331519A - Video display device - Google Patents

Abstract

PURPOSE: To display C/N onto a display device by detecting the C/N in an input signal so as to reduce image quality in a MUSE decode circuit decoding a high definition television signal subjected to band compression. CONSTITUTION: This device is provided with a frame pulse error detection circuit 10, an accumulation circuit 11, a C/N data conversion circuit 12, a C/N data transfer circuit 13, an on-screen control circuit 14, an on-screen display circuit 15 to control in details a correction for contour correction of a signal processing circuit 4 based on distortion or noise amount in the input signal so as to decrease the deterioration in the image quality. Moreover, the state of the input signal is simply grasped by displaying the C/N onto a screen of the display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device for receiving a high quality television signal.

[0002]

2. Description of the Related Art In recent years, there has been an increasing interest in band compression transmission systems in order to efficiently transmit wideband high-definition television signals within a limited transmission band. For example, as one of the band compression transmission systems, MUSE (Mult) that band-compresses high-definition television (high-definition) signals.
The iple Sub-Nyquist Sampling Encoding method has been proposed by the Japan Broadcasting Corporation (NHK). For details of the contents, refer to Yuichi Ninomiya et al., "High-definition Television Satellite 1-Channel Transmission System (MUSE)" (The IEICE, Technical Report, IE 84-7
2.1984).

A conventional image display device will be described below with reference to the drawings. FIG. 5 is a block diagram of a conventional video display device. FIG. 4 shows a band compression method (hereinafter referred to as MUSE).
2A is a configuration diagram of the transmission signal of FIG.
In FIG. 5, 1 is a MUSE signal input terminal, 2 is a low-pass filter (hereinafter LPF) that limits the band, 3 is an A / D conversion circuit that converts the signal to a digital signal, and 4 is the reverse of band compression performed on the transmission side. A signal processing circuit 5 for performing image quality correction such as processing and contour correction, and D / for converting to an analog signal.
A conversion circuit, 6 LPF for band limitation, 7 high-definition signal output terminal, 8 synchronization detection circuit for detecting synchronization,
Reference numeral 9 is a timing signal generating circuit for generating a timing signal.

The operation of the above configuration will be described below. The MUSE signal input to the MUSE signal input terminal 1 of FIG. 5 is band-limited to 8.1 MHz or less by the LPF 2 and then converted into a 10-bit digital signal by the A / D conversion circuit 3. In the signal processing circuit 4, the digital signal output from the A / D conversion circuit 3 is subjected to inverse conversion such as band compression performed on the transmission side and image quality correction such as contour correction to obtain luminance (Y) / color difference ( P _B , P _R ) or green (G), blue (B), red (R) video signals are output. D
The / A conversion circuit 5 converts the digital video signal output from the signal processing circuit 4 into an analog video signal. LP
F6 band-limits the analog video signal output from the D / A conversion circuit 5, and outputs a high-definition signal (R.G.B, etc.) from the high-definition signal output terminal 7. In the synchronization detection circuit 8, the digital signal output from the A / D conversion circuit 3 is used for 17.5 pairs with a 4 clock width as shown in the frame pulse waveform of FIG.
The clock continues, and the next line inverts and detects the frame pulse (hereinafter FP) that repeats for each field.
The detected FP signal is output at the frame reference phase point. The timing signal generation circuit 9 generates a timing signal required for each circuit based on the FP signal output from the synchronization detection circuit 8.

[0005]

However, in the above-described conventional configuration, when the input signal has a lot of distortion or noise, the image quality is easily deteriorated, and the state of the input signal (C / C
There was a problem that the N value) was unknown.

The present invention solves the above-mentioned problems of the prior art. Even if the input signal has distortion or noise, the deterioration of the image quality is reduced and the image showing the state (C / N value) of the input signal is displayed. It is intended to provide a display device.

[0007]

To achieve this object, the present invention comprises a frame pulse error detection circuit, a cumulative addition circuit, and a C / N data conversion circuit, and is provided with a structure for reducing deterioration of image quality. Is. Alternatively, a horizontal synchronization error detection circuit, a cumulative addition circuit, and a C / N data conversion circuit are provided to reduce the deterioration of image quality. Or
Frame pulse error detection circuit, accumulative addition circuit, C / N data conversion circuit, C / N data transfer circuit, on-screen control circuit, on-screen display circuit provided with a structure for understanding the C / N value of the input signal Is.

[0008]

With this configuration, in the present invention, when the input signal has distortion or noise, the error between the frame pulse signal detected by the frame pulse error detection circuit and the normal level is detected, and the number of detections is increased by the cumulative addition circuit, It is possible to reduce the deterioration of image quality by converting into C / N data by the C / N data conversion circuit and controlling the correction amount of the contour correction of the signal processing circuit. Alternatively, when distortion or noise remains in the input signal, the error between the horizontal sync signal detected by the horizontal sync error detection circuit and the normal level is detected, the number of detections is increased by the cumulative addition circuit, and the C / N data conversion circuit is used. It is intended to reduce the deterioration of image quality by converting into C / N data and controlling the correction amount of the contour correction of the signal processing circuit. Alternatively, when the input signal has distortion or noise, the error between the frame pulse signal detected by the frame pulse error detection circuit and the normal level is detected, the number of detections is increased by the cumulative addition circuit, and the C / N data conversion circuit detects C / N data, the C / N data transfer circuit transfers the C / N data via the bus, the on-screen control circuit converts the C / N data into characters, and the on-screen display circuit displays it on the screen of the display. By displaying the C / N value, it is possible to show the state of the input signal.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a video display device of the present invention.

In FIG. 1, 1 is a MUSE signal input terminal, 2 is an LPF for band limitation, 3 is an A / D conversion circuit for converting into a digital signal, 4 is reverse processing such as band compression performed on the transmission side and A signal processing circuit for performing image quality correction such as contour correction, 5 is a D / A conversion circuit for converting into an analog signal,
6 is an LPF for band limitation, 7 is a high-definition signal output terminal, 8 is a synchronization detection circuit for detecting synchronization, 9 is a timing signal generation circuit for generating a timing signal, and 10 is a frame pulse error detection for detecting a frame pulse error. Circuit, 11 is a cumulative addition circuit for cumulatively adding error data, 1
Reference numeral 2 is a C / N data conversion circuit that converts the cumulatively added error data into C / N data.

The operation of the above configuration will be described below. The MUSE signal input to the MUSE signal input terminal 1 of FIG. 1 is band-limited to 8.1 MHz or less by the LPF 2 and then converted into a 10-bit digital signal by the A / D conversion circuit 3. In the signal processing circuit 4, the digital signal output from the A / D conversion circuit 3 is subjected to inverse conversion such as band compression performed on the transmission side and image quality correction such as contour correction to obtain luminance (Y) / color difference ( P _B , P _R ) or green (G), blue (B), red (R) video signals are output. D
The / A conversion circuit 5 converts the digital video signal output from the signal processing circuit 4 into an analog video signal. LP
F6 band-limits the analog video signal output from the D / A conversion circuit 5, and outputs a high-definition signal (R.G.B, etc.) from the high-definition signal output terminal 7. In the synchronization detection circuit 8, the digital signal output from the A / D conversion circuit 3 is used for 17.5 pairs with a 4 clock width as shown in the frame pulse waveform of FIG.
After the clock continues, the next line is inverted, and the FP is detected repeatedly for each field, and the detected FP signal is output at the frame reference phase point. The timing signal generation circuit 9 generates a timing signal required for each circuit based on the FP signal output from the synchronization detection circuit 8. Further, in the frame pulse error detection circuit 10, the digital signal output from the A / D conversion circuit 3 is used to generate 17.5 pairs of 140 clocks and the next line with a 4-clock width shown in the frame pulse waveform of FIG. A normal level (Hi = 239/25) is applied to the inverted data for 140 clock periods.
6, Low = 16/256 level), and outputs the difference as an error. Furthermore, the cumulative addition circuit 11
The error data output from the frame pulse error detection circuit 10 is cumulatively added, and the C / N data conversion circuit 12 outputs the cumulatively added error data output from the cumulative addition circuit 11 to C / N by a table such as a ROM. Convert to N data. Based on this C / N data, the signal processing circuit 4
The amount of contour correction is controlled.

As described above, according to the present embodiment, the frame pulse error detection circuit, the cumulative addition circuit, and the C / N data conversion circuit are provided, and the contour correction of the signal processing circuit is corrected by the amount of distortion or noise of the input signal. The amount can be controlled finely and the deterioration of the image quality can be reduced.

(Embodiment 2) FIG. 2 is a block diagram of a video display device of the present invention.

In FIG. 2, 1 is a MUSE signal input terminal, 2 is an LPF for band limitation, 3 is an A / D conversion circuit for converting into a digital signal, 4 is reverse processing such as band compression performed on the transmission side and A signal processing circuit for performing image quality correction such as contour correction, 5 is a D / A conversion circuit for converting into an analog signal,
6 is an LPF that limits the band, 7 is a high-definition signal output terminal, 8 is a synchronization detection circuit that detects synchronization, 9 is a timing signal generation circuit that generates a timing signal, and 10 is a horizontal synchronization error detection that detects a horizontal synchronization error. A circuit, 11 is a cumulative addition circuit for cumulatively adding error data, and 12 is a C / N data conversion circuit for converting the cumulatively added error data into C / N data.

The operation of the video display device configured as described above will be described below. After the MUSE signal input to the MUSE signal input terminal 1 of FIG. 2 is band-limited to 8.1 MHz or less by the LPF 2, the A / D conversion circuit 3
To convert to a 10-bit digital signal. In the signal processing circuit 4, the digital signal output from the A / D conversion circuit 3 is subjected to inverse conversion such as band compression performed on the transmission side and image quality correction such as contour correction to obtain luminance (Y) / color difference ( P
_B , P _R ) or green (G), blue (B), red (R) video signals are output. The D / A conversion circuit 5 converts the digital video signal output from the signal processing circuit 4 into an analog video signal. The LPF 6 limits the band of the analog video signal output from the D / A conversion circuit 5, and outputs a high-definition signal (R.G.B, etc.) from the high-definition signal output terminal 7.
Is output. Further, in the synchronization detection circuit 8, the digital signal output from the A / D conversion circuit 3 is used for 17.5 with a 4-clock width as shown in the frame pulse waveform of FIG. 4B.
The pair continues for 16 more clocks, then inverts on the next line,
The detection of FP repeated for each field is performed, and the detected FP signal is output at the frame reference phase point. The timing signal generation circuit 9 generates a timing signal required for each circuit based on the FP signal output from the synchronization detection circuit 8. Further, in the horizontal synchronization error detection circuit 10, from the digital signal output from the A / D conversion circuit 3, Hi level (sample numbers 2, 3, 4, 5) shown in the HD period of FIG.
Normal level (Hi = 192/256, Low =) for low level data (sample numbers 7, 8, 9, and 10)
64/256 level) and outputs the difference as an error. Furthermore, the cumulative addition circuit 11 cumulatively adds the error data output from the horizontal synchronization error detection circuit 10, and the C / N data conversion circuit 12 cumulatively adds the error data.
The cumulatively added error data that is the output of
It is converted into C / N data by a table such as. This, C
The correction amount of the contour correction of the signal processing circuit 4 is controlled by the / N data.

As described above, according to this embodiment, the horizontal synchronization error detection circuit, the cumulative addition circuit, and the C / N data conversion circuit are provided, and the contour correction of the signal processing circuit is corrected by the amount of distortion or noise of the input signal. The amount can be controlled finely and the deterioration of the image quality can be reduced.

(Embodiment 3) FIG. 3 is a block diagram of a video display device of the present invention.

In FIG. 3, 1 is a MUSE signal input terminal, 2 is an LPF for band limitation, 3 is an A / D conversion circuit for converting into a digital signal, 4 is reverse processing such as band compression performed on the transmission side and A signal processing circuit for performing image quality correction such as contour correction, 5 is a D / A conversion circuit for converting into an analog signal,
6 is an LPF for band limitation, 7 is a high-definition signal output terminal, 8 is a synchronization detection circuit for detecting synchronization, 9 is a timing signal generation circuit for generating a timing signal, and 10 is a frame pulse error detection for detecting a frame pulse error. Circuit, 11 is a cumulative addition circuit for cumulatively adding error data, 1
2 is a C / N data conversion circuit for converting the cumulatively added error data into C / N data, 13 is a C / N data transfer circuit for transferring the C / N data via a bus, and 14 is an on-screen display on the display. Is an on-screen control circuit for controlling the display, and 15 is an on-screen display circuit for performing on-screen display on the display.

The operation of the above configuration will be described below. The MUSE signal input to the MUSE signal input terminal 1 of FIG. 3 is band-limited to 8.1 MHz or less by the LPF 2 and then converted into a 10-bit digital signal by the A / D conversion circuit 3. In the signal processing circuit 4, the digital signal output from the A / D conversion circuit 3 is subjected to inverse conversion such as band compression performed on the transmission side and image quality correction such as contour correction to obtain luminance (Y) / color difference ( P _B , P _R ) or green (G), blue (B), red (R) video signals are output. D
The / A conversion circuit 5 converts the digital video signal output from the signal processing circuit 4 into an analog video signal. LP
F6 band-limits the analog video signal output from the D / A conversion circuit 5, and outputs a high-definition signal (R.G.B, etc.) from the high-definition signal output terminal 7. In the synchronization detection circuit 8, the digital signal output from the A / D conversion circuit 3 is used for 17.5 pairs with a 4 clock width as shown in the frame pulse waveform of FIG.
After the clock continues, the next line is inverted, and the FP is detected repeatedly for each field, and the detected FP signal is output at the frame reference phase point. The timing signal generation circuit 9 generates a timing signal required for each circuit based on the FP signal output from the synchronization detection circuit 8. Further, in the frame pulse error detection circuit 10, the digital signal output from the A / D conversion circuit 3 is used to generate 17.5 pairs of 140 clocks and the next line with a 4-clock width shown in the frame pulse waveform of FIG. A normal level (Hi = 239/25) is applied to the inverted data for 140 clock periods.
6, Low = 16/256 level), and outputs the difference as an error. Furthermore, the cumulative addition circuit 11
The error data output from the frame pulse error detection circuit 10 is cumulatively added, and the C / N data conversion circuit 12 outputs the cumulatively added error data output from the cumulative addition circuit 11 to C / N by a table such as a ROM. Convert to N data. Further, the C / N data transfer circuit 13 is
The C / N data output from the / N data conversion circuit 12 is set to 2
Data transfer is performed by a line (clock, data) or three-line (clock, data, busy) bus. The on-screen control circuit 14 reads the C / N data from the 2-line or 3-line bus which is the output of the C / N data transfer circuit 13, and converts the C / N data into characters to be displayed on-screen on the display. The on-screen display circuit 15 displays the C / N data (characters or the like) output from the on-screen control circuit 14 on the on-screen of the display.

As described above, according to this embodiment, the frame pulse error detection circuit, the cumulative addition circuit, the C / N data conversion circuit, the C / N data transfer circuit, the on-screen control circuit, and the on-screen display circuit are provided. C of MUSE signal
By displaying the / N value on the screen of the display, it is possible to grasp the state of the input signal (BS input signal) very easily such as adjustment of the antenna installation and attenuation of rainfall.

[0022]

As described above, according to the present invention, the frame pulse error detection circuit, the cumulative addition circuit, and the C / N data conversion circuit are provided, and the contour correction of the signal processing circuit is performed according to the distortion of the input signal and the amount of noise. The correction amount can be finely controlled, and the deterioration of image quality can be reduced.

Further, a horizontal synchronization error detection circuit, a cumulative addition circuit, and a C / N data conversion circuit are provided, and the correction amount of the contour correction of the signal processing circuit can be finely controlled by the amount of distortion and noise of the input signal, and the image quality is deteriorated. Can be reduced.

Further, a frame pulse error detection circuit, a cumulative addition circuit, a C / N data conversion circuit, a C / N data transfer circuit, an on-screen control circuit and an on-screen display circuit are provided to display the C / N value of the MUSE signal. By displaying it on the screen, it is possible to grasp the state of the input signal (BS input signal) very easily such as adjustment of the antenna installation and attenuation of rainfall.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first video display device of the present invention.

FIG. 2 is a configuration diagram of a second video display device of the present invention.

FIG. 3 is a configuration diagram of a third video display device of the present invention.

FIG. 4 is a block diagram of a transmission signal of band compression (MUSE method)

FIG. 5 is a configuration diagram of a conventional video display device.

[Explanation of symbols]

 1 MUSE signal input terminal 2 low-pass filter 3 A / D conversion circuit 4 signal processing circuit 5 D / A conversion circuit 6 low-pass filter 7 high-definition output signal terminal 8 synchronization detection circuit 9 timing signal generation circuit 10 frame pulse error detection circuit 11 cumulative addition Circuit 12 C / N data conversion circuit 13 C / N data transfer circuit 14 On-screen control circuit 15 On-screen display circuit

Claims (4)

[Claims] 1. A frame pulse error detection circuit for detecting an error from a frame pulse signal and a normal level, a cumulative addition circuit for cumulatively adding outputs of the frame pulse error detection circuit, and an output of the cumulative addition circuit is C / N. An image display device comprising a C / N data conversion circuit for converting into data and detecting C / N data of an input signal. 2. The image quality is optimized according to the amount of distortion and noise of the input signal by controlling the correction amount of image quality adjustment such as contour correction of the signal processing circuit by detecting the C / N data. The video display device according to claim 1. 3. A horizontal synchronization error detection circuit for detecting an error from a horizontal synchronization signal and a normal level, a cumulative addition circuit for cumulatively adding outputs of the horizontal synchronization error detection circuit, and an output of the cumulative addition circuit is C / N. An image display device comprising a C / N data conversion circuit for converting into data and detecting C / N data of an input signal. 4. A frame pulse error detection circuit for detecting an error from a frame pulse signal and a normal level, a cumulative addition circuit for cumulatively adding outputs of the frame pulse error detection circuit, and an output of the cumulative addition circuit is C / N. C / N data conversion circuit for converting data, C / N data transfer circuit for transferring C / N data, on-screen control circuit for converting C / N data, and on-screen display for displaying C / N value An image display device comprising a circuit and displaying C / N data on a screen of a display.