JPH08330948A - Method and equipment for phase deviation clock generation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for generating plural phase shift clocks on an IC chip. SOLUTION: The device is provided with a PLL 150 provided at a first position and to generate a reference clock 170 and reference voltage 172, local clock generation circuits 152, 154 provided at a second position and a first conductor connected with the PLL 150 and the local clock generation circuits and to transmit the reference clock from the PLL 150 to the local clock generation circuit. Furthermore, the device is provided with a second conductor connected with the PLL 150 and the local clock generation circuits and to transmit the reference voltage from the PLL 150 to the local clock generation circuits. The plural phase shift clocks are generated at a second position by using the local clock generation circuits, according to the reference voltage and the reference clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit, and more particularly to a circuit for generating a plurality of phase shift clocks from a phase locked loop circuit (PLL). More specifically, the present invention is a method and apparatus for generating a plurality of phase shift clocks at various local locations on an integrated circuit (IC) chip using a minimum number of signals output from a central PLL. Regarding

[0002]

2. Description of the Related Art Recent miniaturization and advances in assembly technology have made it possible to directly form a PLL circuit on a chip having a logic circuit configuration such as a microprocessor. The use of the built-in PLL circuit (on-board PLL circuit) facilitates the logic design that preferably uses one or a plurality of phase shift clocks. A phase-shifted clock is a clock that has basically the same frequency and is delayed, ie, phase-shifted, in a frequency-dependent manner. By using a phase shift clock, a given type of logic circuit, such as a dynamic CM, in which the relative timing between clocks and the circuit period are important at any operating frequency.
It is possible to simplify the design of the OS logic circuit, the positive feedback amplifier, etc., and improve the performance thereof.

Conventionally, a plurality of phase shift clocks are generated by centrally arranged PLLs, and then on-chip.
A method is used in which the clock is transmitted via a plurality of independent conductors to a local position where the clock is actually used.
However, it is known that there are many problems in the method of transmitting a centrally generated phase shift clock to a local position where the clock is actually required by using a plurality of conductors. There is.

FIG. 1 is a schematic diagram showing a conventional PLL circuit for centrally generating a plurality of phase shift clocks, in which the centrally generated phase shift clocks are traversed across a chip. It is equipped with the conductors necessary for transmission. As shown in FIG. 1, an integrated circuit (IC) chip 100 includes centrally arranged PLLs 102.
Here, as long as the circuits performing the functions related to the PLL are concentrated at a single position on the chip, regardless of whether the position is at the center of the chip or near the periphery of the chip, the "PLL They are centrally located. ” The centrally located PLL 102 generates a plurality of phase-shifted clocks, and some or all of the generated phase-shifted clocks are stored at three local positions 104, 10.
6 and 108 respectively. For convenience of illustration, FIG.
In the PLL 102 shown in (6), six phase shift clocks are generated and output to each of the six conductors 111 to 116. All six conductors 111-116 are provided to local locations 106 that require these conductors. Also, 6
Five of the five conductors 112-115 are further directed to the local location 104 for local use. Furthermore, another 5
One conductor 111-115 is directed to and used at another local location 108. As is clear from the figure,
Prior art methods require multiple conductors to provide a centrally generated phase shift clock to the local location where the clock is needed.

[0005]

When the phase shift clock is centrally generated, a large number of conductors are required to transmit the centrally generated phase shift clock to a local location. However, using a large number of conductors occupies a large amount of space on the chip, and in some cases requires the chip to be large in order to accommodate the large number of conductors according to existing design criteria. In addition, arranging a large number of conductors on the chip complicates the layout and limits the total number of clocks that can be centrally generated. Due to such limitations, the method of using a plurality of phase shift clocks for circuit design has not gained general support. That is, because space, layout, and power are limited, it is impractical to centrally generate more than one phase-shifted clock and transmit those clocks across the chip. Has been considered.

In the prior art method of centrally generating phase shift clocks and transmitting these clocks across the chip, the use of multiple long conductors each for transmitting a high frequency clock would result in Conventional design is susceptible to electromagnetic interference. In addition, the capacitance associated with these long conductors requires higher drive currents in the central PLL, resulting in increased power consumption and the generation of thermal energy that often causes chip failure. It

Further, when the phase shift clocks are centrally generated, there is also a problem that the entire chip must be corrected every time one clock is added or deleted at the local position. For example, in the prior art,
If one of the five clocks is no longer needed at a given local location, then it is necessary to remove the conductors that carry that clock signal from the central PLL to that local location, and possibly even the overall layout. The optimization will have to be redone. If later in the design it becomes necessary to replace one clock line with another, the prior art method uses the conductors used to supply the appropriate clock line to the local location that requires it. I have to rethink the route. Changing any one of the centrally generated clocks has a negative effect on design modularity, resulting in increased design time and cost.

In order to solve the above problems, there is a need for an improved apparatus and method for generating a phase-shifted clock at each local location from as few centrally generated PLL signals as possible. Has been. The improved apparatus and method preferably simplifies the design of the central PLL to generate only the reference clock and the reference signal, and locally generates the phase shift clock from the reference clock and the reference signal on demand. This allows the central PLL
It is possible to reduce the number of conductors extending from to reduce space occupancy on the chip, power consumption, and susceptibility to electromagnetic interference.

[0009]

Means for Solving the Problems and Their Actions / Effects In order to solve at least some of the above problems, the present invention provides
A first apparatus is provided for generating a plurality of phase shift clocks at a local location on an IC chip. A first device of the present invention is a central PL that generates a reference clock and a reference voltage.
L, a local clock generation circuit provided at the local position, and a set of conductors for connecting the central PLL to the local clock generation circuit. The set of conductors includes a first conductor for transmitting the reference clock,
A second conductor for transmitting the reference voltage,
The local clock generation circuit uses the reference clock and the reference voltage to generate the plurality of phase shift clocks at the local position.

The present invention also provides a first method for generating a plurality of phase shift clocks at local locations on an IC chip. The first method comprises the steps of preparing (providing) a central PLL that generates a reference clock and a reference voltage, and preparing a local clock generation circuit at the local location. Further, the first method of the present invention comprises the step of connecting the central PLL and the local clock generation circuit with a pair of conductors. The set of conductors includes a first conductor for transmitting the reference clock and a second conductor for transmitting the reference voltage, and the local clock generation circuit includes the reference clock and the A plurality of phase shift clocks are generated at the local position using a reference voltage.

The present invention further provides a second method for generating a plurality of phase shift clocks at local locations on an IC chip. The second method comprises the steps of preparing a centrally arranged PLL on the IC chip, generating a reference clock and a reference voltage signal using the centrally arranged PLL, and the local portion. Providing a local clock generation circuit at the location. Further, the second method of the present invention comprises the step of connecting the local clock generation circuit to the first set of conductors. The first set of conductors connects the centrally disposed PLL to the local clock generation circuit, and the centrally disposed PLL directs the local clock generation circuit to the reference clock and the reference voltage signal. To transmit. The second method of the present invention further uses the local clock generation circuit to locally generate the plurality of phase shift clocks at the local position in response to the reference clock and the reference voltage signal. It has a process.

The present invention also provides a second apparatus for generating a plurality of phase shift clocks on an IC chip. A second device of the present invention includes a PLL provided at a first position to generate a reference clock and a reference voltage, a local clock generation circuit provided at a second position, the PLL and the local clock generation. A first conductor connected to both the circuit and for transmitting the reference clock from the PLL to the local clock generation circuit. The second device of the present invention further includes a second conductor that is connected to the PLL and the local clock generation circuit and that transmits the reference voltage from the PLL to the local clock generation circuit. , The plurality of phase shift clocks are generated at the second position by using the local clock generation circuit according to the reference voltage and the reference clock.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described based on examples. 2 shows a PLL circuit 150 according to the present invention and local clock generation circuits 152, 1 associated with a plurality of local locations 158, 160, 162, respectively.
FIG. 54 is a schematic view showing an embodiment of the present invention including 54 and 156. The reference voltage 170 and the reference clock 172 generated by the PLL circuit 150 of the present invention are transmitted to respective local positions and used to locally generate a necessary phase shift clock. For example, the reference voltage 170 and the reference clock 172 are respectively the local clock generation circuit 15
2 to locally generate the six phase shift clocks used at the local location 158. Furthermore, the reference voltage 1
70 and the reference clock 172 are the local clock generation circuit 1
Sent to 54 to locally generate the five phase shift clocks used at the local location 160. Compared to the prior art circuit of FIG. 1, the circuit of the present invention reduces the total number of signals to be generated in a centralized manner, so
The structure of the LL 150 is simplified. Furthermore, the central PL
Simplifying the layout by reducing the number of conductors required to connect L150 to each local location, and also if it is necessary to add or remove the phase shift clock at any local location, The change can be locally limited.

FIG. 3 illustrates a reference clock R on conductor 302 in response to an external reference clock CLKX on conductor 306 and a feedback clock CLKFB on conductor 308.
EFCLK and optionally (optionally) conductor 30
4 is a schematic circuit diagram showing a PLL circuit 300 of the present invention for generating the complementary reference clock REFCLKB on the H.4. The PLL 300 circuit is typically designed on-chip, but may be provided as a separate chip, as in the prior art. The PLL circuit 300 uses the feedback clock C as the frequency and phase of the external reference clock CLKX.
Fix to LKFB. Reference clock REFCLK
And the optional reference clock REFCLKB are complementary to the standard type of reference system clocks transmitted to the local location to locally generate the phase shift clock. PLL
Circuit 300 further includes a reference voltage signal VR on conductor 310.
Output EFN. The reference voltage signal VREFN is a reference clock REFCLK and an optional reference clock REFCLK.
Similar to B, it is sent to a local location on the IC chip to locally generate the required phase shift clock at that location.

FIG. 4 is a diagram showing details of the PLL circuit 300 shown in FIG. In FIG. 4, the external reference clock CLKX on conductor 306 is shown. This external reference clock C
The LKX may be generated by a known crystal circuit, for example. Feedback clock C shown in FIG.
LKFB is PLL with external reference clock CLKX.
It is input to the phase frequency detector 312 of the circuit 300. The phase frequency detector 312 compares the frequency and phase of the external reference clock CLKX with the frequency of the feedback clock CLKFB. If the external reference clock CLKX is faster than the feedback clock CLKFB, the phase frequency detector 312 produces an up signal 314,
The signal is output to the charge pump 316 of the PLL circuit 300.
On the other hand, when the external reference clock CLKX is slower than the feedback clock CLKFB, the phase frequency detector 312 generates the down signal 318 and outputs it to the charge pump 316.

The charge pump 316 has an up signal 31.
4 or down signal 318, and outputs control voltage VCTL on conductor 320 in response to the signal. When the up signal 314 is input to the charge pump 316, the control voltage VCTL becomes high. Conversely, when the down signal 318 is input to the charge pump 316, the control voltage VCTL becomes low. This control voltage VCT
L is a voltage controlled oscillator (VCO) 3 of the PLL circuit 300.
22 is input. VCO 322 is implemented, for example, by a desired number of well-known voltage controlled oscillators. The output of voltage controlled oscillator 322 is a reference clock RE on conductor 302.
Input to buffer 324 to generate FCLK and, optionally, reference clock REFCLKB on conductor 304. Reference clocks REFCLK and R
Any one of the EFCLKBs or an inductive clock from any of the EFCLKBs may be connected to the feedback clock CLKFB. The control voltage VCTL output from the charge pump 316 is further input to the unit gain amplifier (unity gain amplifier) 326 of the PLL circuit 300. The unity gain amplifier 326 buffers the control voltage VCTL and outputs the reference voltage signal VREFN on the conductor 310.

In the example shown in FIG. 4, the PLL circuit 300 is
Only one reference voltage signal VREFN is generated, but by using an appropriate buffer associated with the PLL circuit 300, both the reference voltage signal VREFN and the complementary reference voltage signal VREFP are generated centrally and both of them are generated. It is also possible to send the reference voltage signal of 1 to a local position to generate a plurality of phase shift clocks.
Further, the PLL circuit 300 allows the reference clock REFC
A configuration in which LK and REFCLKB are generated centrally and both reference clocks are transmitted to a local position is also possible, but only one reference clock, that is, REFCLK or REFCLK
Only one of B's is generated and its reference clock signal is supplied to the local position, and if necessary, the complementary clock is generated at the local position according to a clock generation method that does not cause a delay in the generated clock signal. The clock may be generated locally.

PLL (eg PLL circuit 300 of FIG. 4)
Alternatively, a frequency divider may be provided. This divider
Often, but not always, the VCO 322
And a buffer / driver 324 to achieve a 50% duty cycle on the system clock.
In this case, the granularity can be improved by configuring the predetermined number of stages to have more phases.

Only one reference voltage signal, eg VRE
If the FN is transmitted from the central PLL to a local location, a complementary reference voltage signal, eg VREFP, must be generated at or near the local location. FIG. 5 is a schematic circuit diagram showing a complementary voltage generation circuit that generates and outputs a complementary voltage signal in response to the input of a given voltage signal. For convenience of illustration, preferably a local position that produces the phase-shifted clock,
Alternatively, a simple inverting amplifier (simp
FIG. 5 shows a le inverting amplifier) 350. The simple inverting amplifier 350 can also be considered as a circuit that outputs a mirror image of an input signal.

As shown in FIG. 5, p-channel device 352 is connected in series with n-channel device 354 and supply voltages Vdd and Vss. The gate of the p-channel device 352 is connected to a node (node) 356, and the node 356 is further connected to the p-channel device 352 and the n-channel device 354. The node 356 is a circuit node to which the complementary reference voltage signal VREFP is output. On the other hand, the gate of the n-channel device 354 has a reference voltage signal VREFN output from the central PLL, for example, the PLL 300 shown in FIG.
Controlled by.

In actual operation, the reference voltage signal VREFN
Goes high, the n-channel device 354 turns on, pulling node 356 toward voltage Vss, causing complementary reference voltage signal VREFP to go low. Conversely, when the reference voltage signal VREFN becomes low, the n-channel device 3
54 is gradually turned off, and the node 356, that is, the complementary reference voltage signal VREFP goes high. As is clear from the above description, the reference voltage signal VREFP is a mirror image of the reference voltage signal VREFN. P-channel device 352 serves as the current source for the circuit shown in FIG.

The circuit of FIG. 5 is a complementary voltage generating circuit, that is,
Only one example of a circuit for locally generating the complementary reference voltage signal VREFP from the supplied reference voltage signal VREFN is shown. As is well known to those skilled in the art, another type of circuit known in the art may be used to generate the complementary voltage from the supplied voltage. Reference voltage signal VREF
If N is transmitted through a long conductor, usually VR
The EFN is coupled to the supply voltage Vss to eliminate transient noise on the VREFN conductor line or Vss line.

It may be desirable to separate the circuit that outputs the reference voltage signal, VREFN and / or VREFP, from the circuit that outputs the reference clock, REFCLK and / or REFCLKB. Separating the two sets of circuits reduces interference that can adversely affect the reference clock output. Figure 6
FIG. 4 is a schematic diagram showing a circuit for separating a circuit for generating a reference voltage signal from a circuit for generating a reference clock.

In contrast to the circuit shown in FIG. 4 which has only one phase frequency detector, the circuit shown in FIG.
Equipped with one phase frequency detector. However, the same external reference clock and feedback clock are both input to the two frequency detectors. One phase frequency detector is used to generate the reference voltage and the other is used to generate the reference clock. Further, the circuit of FIG. 6 includes two charge pump circuits. One charge pump circuit is used to generate a reference voltage, and the other is used to generate a reference clock. The circuit that generates the reference clock is
It comprises the voltage controlled oscillator described above and an optional buffer / driver. The reference voltage may be generated directly from the output of the charge pump circuit regardless of whether or not the buffer circuit is used.

FIG. 7 is a schematic circuit diagram showing a local clock generation circuit used to generate a plurality of phase shift clocks at a local position. As shown in FIG. 7, the open loop phase shift clock generation circuit 400 comprises six variable delay stages 402, 404, 406, 408, 410 and 412. Only the first three delay stages 402, 404, 406 are shown in detail in FIG. The other stages 408, 410, and 412 are also stage 4
02, 404, and 406, but these are simplified for convenience of illustration. Although six variable delay stages are shown in the circuit of FIG. 7, the number of stages for each phase shift clock generation circuit may be increased or decreased as necessary. In the phase shift clock generation circuit 400, the reference voltage signal VRE is placed on the conductors 414 and 416.
FN and VREFP are input respectively. Also, the conductor 4
The reference clock REFCLK is input onto the line 18.

Variable delay stage 402 comprises a p-channel device 420 having a gate connected to a reference voltage signal VREFP on conductor 416. The p-channel device 420 is further connected to the voltage Vdd and the p-channel device 422. As shown in FIG. 7, p-channel device 422 and n-channel device 424
Has a reference clock REFCLK on conductor 418.
It is connected to the. P-channel device 422 and n-channel device 424 are both connected to conductor 426, thereby forming the output of variable delay stage 402. The n-channel device 424 has n
It is connected in series with the channel device 428, and the gate of the n-channel device 428 is connected to the conductor 41.
4 to the reference voltage signal VREFN. The n-channel device 428 is also connected to the voltage Vss. Thus, the variable delay stage 402 has four
It consists of two devices connected in series. That is,
An inverter configured by a p-channel device 420 having a gate controlled by a reference voltage signal VREFP, a p-channel device 422 and an n-channel device 424, the input of which is controlled by a reference clock REFCLK, and the output of which is Is an output of the variable delay stage 402, and an n-channel device 428 having a gate controlled by the reference voltage signal VREFN. Other variable delay stages 404, 406, 408, 410, 412
Is similarly configured. However, the variable delay stage 40
The p-channel and n-channel devices that make up No. 2 and the p-channel and n-channel devices of the subsequent stages are not necessarily the same size. this is,
This is to increase or decrease the delay between the output and the input of the variable delay stage. For example, the fanout associated with a given stage may be reduced if finer granularity is desired. On the other hand, if a coarser grain size is suitable, fanout may be increased.

In operation, the variable delay stage 402
Conductor 4 from the central PLL (eg, PLL 300 in FIG. 4)
It receives the reference clock REFCLK on 18 and outputs a phase-shifted version of the input reference clock on conductor 426. Conductor 42 in Variable Delay Stage 402
The delay between the output clock on 6 and the input clock on conductor 418 depends on the strength of the reference voltage signal VREFN and its dual reference voltage signal VREFP. As the strength of the reference voltage signal VREFP increases, the strength of the dual reference voltage signal VREFN correspondingly decreases. In this case, the current through the device in the variable delay stage 402 is reduced to allow conductor 4 to respond to the input signal on conductor 418.
The delay of the output signal on 26 increases.

Conversely, as the strength of the reference voltage signal VREFP decreases, the strength of the dual reference voltage signal VREFN increases correspondingly. In this case, the current through the device in the variable delay stage 402 will increase and conductor 41 will
The delay of the output signal on conductor 426 relative to the input signal on 8 is reduced. The output of the variable delay stage 402 is given to the next variable delay stage 404 and also output as the derived phase shift clock CLK2B. In the variable delay stage 402, the derived phase-shifted clock CLK2B is not only delayed (ie, phase-shifted) but also the input reference on conductor 418 due to the transcoding action of the inverter composed of devices 422 and 424. The phase is opposite to that of the clock REFCLK.

Similarly, variable delay stage 404 receives derived phase shift clock CLK2B on conductor 426 and, in response to reference voltage signal VREFP on conductor 416 and reference voltage signal VREFN on conductor 414, conductor 43.
The derived phase shift clock CLK3 is output on 0. The derived phase shift clock CLK3 is fed to the variable delay stage 404.
Is delayed from the derived phase shift clock CLK2B. Of course, the derived phase shift clock CLK2B is delayed from the reference clock REFCLK on the conductor 418, as compared to the derived phase shift clock CLK2B.
K3 has a larger degree of phase deviation from the reference clock REFCLK. Variable delay stage 40 that follows
6, 408, 410, and 412 are similarly derived phase shift clocks CLK4B, CLK5, CLK6B, and CLK7.
Occurs.

As is clear from the above description, the central PL
Three signals sent from L (ie reference clock REF
An arbitrary number of phase-shifted clocks are generated at the local position from a reference clock such as CLK, a reference voltage signal such as reference voltage signal VREFN, and a dual reference voltage signal such as reference voltage signal VREFP. As mentioned above, VR
The reference voltage signal such as EFP is VR supplied from the PLL.
When generated from a dual reference voltage signal such as an EFN according to a non-delayed clock generation method at or near a local location, two signals transmitted from the central PLL (eg, a single reference clock signal and a single reference clock signal). It is possible to locally generate a plurality of phase shift clocks at a local position using only the reference voltage signal of the above. It should be noted that due to the action of the inverter in the delay stage, every other phase-shifted clock is out of phase with the supplied reference clock. For example, the phase shift clock CL
K2B, CLK4B, and CLK6B are delayed from the input reference clock REFCLK and have opposite phases. Some applications require the generation of a complete set of phase-shifted clocks, eg both inverted and non-inverted phase-shifted clocks. In such a case, two phase shift clock generation circuits may be used. By inputting the signal REFCLK as the reference clock signal to one circuit and inputting the signal REFCLKB to the other circuit as the reference clock signal, the above-described complete set can be generated.

FIG. 8 shows the reference clock REFCLK of FIG.
And derived phase shift clocks CLK2B, CLK3, CLK
4B is a timing chart showing the relationship with 4B and CLK5. The clock REFCLK shown in FIG. 8 is a reference clock input to the phase shift clock generation circuit 400 shown in FIG. The cycle of the reference clock REFCLK is Tref
Is. The derived phase shift clock CLK2B is phase shifted from the input clock REFCLK by the variable delay time Tfd1. In addition, the derived phase shift clock CLK2B
Is almost the same period Tref as the input clock REFCLK.
have. As described above, the derived phase shift clock CLK2B is not only delayed from the input clock REFCLK but also has the polarity opposite to that of the input clock REFCLK due to the function of the inverter in the variable delay stage 402.

The derived phase shift clock CLK3 further includes
Since it is inverted by the variable delay stage 404, it is delayed from the input reference clock REFCLK, but has the same polarity as the input reference clock REFCLK. The derived phase shift clock CLK3 is delayed from the derived phase shift clock CLK2B by the variable delay time Tfd2. As is clear from the above, the derived phase shift clock CLK3 is equal to the total variable delay time (Tfd1 + Tf).
Delayed from the input reference clock REFCLK by d2).

Similarly, the derived phase shift clock CLK4B
Is a variable delay time T from the derived phase shift clock CLK3.
It is delayed by being phase-shifted by fd3. Further, the derived phase shift clock CLK5 is the derived phase shift clock CLK.
4B is phase-shifted by a variable delay time Tfd4 and delayed.

Since the derived phase shift clocks are delayed one after another by the delay time depending on the frequency, the relative phase difference is kept constant regardless of the operating frequency. Further, since there are a plurality of phase shift clocks at one local position, it becomes possible to generate a higher frequency clock. That is, it is possible to generate a clock having a frequency that is twice, triple, or higher than the frequency of the input clock such as the reference clock REFCLK. To generate such a high frequency clock, the circuit disclosed in the present invention generates a plurality of appropriately phase-shifted clocks and ORs the plurality of clocks.
The synthesis may be performed by a logic gate such as a circuit or a summing circuit such as a summing amplifier. Thus, the ability to locally derive a clock with a higher operating frequency from an input reference clock is another advantage of the present invention.

By using a plurality of clocks, there is also an advantage that a self-timed circuit is not required. FIG. 9 is a schematic circuit diagram showing a positive feedback amplifier circuit 600 used, for example, in the design of a microprocessor. Positive feedback amplifier circuits are another example of a circuit that would benefit from the use of multiple phase shifted clocks. The element 602 shown in FIG. 9 is a storage element that stores data until strobed by the clock CLK1 provided through the conductor 604. For example, a memory array, a latch, a memory cache, or the like can be used as the element 602. When strobed by clock CLK1, element 602 is routed through conductors 606 and 608.
Positive feedback amplifier element 610 for data
Output to. Positive feedback amplifier element 6
10 is then strobed by the clock CLK2 provided via conductor 612 to output the standard output To on conductor 614 and the complementary output Co on conductor 616.

In operation, when clock CLK1 strobes element 602, data is output on conductors 606 and 608, respectively. Conductors 606 and 60
The data output on 8 is amplified by positive feedback amplifier element 610 in response to strobe clock CLK2 on conductor 612. As a result, amplified signals are output on the conductors 614 and 616, respectively. Clock CLK2 must be excited after clock CLK1 to ensure that the output of circuit 600 accurately reflects the data strobed from element 602 by clock CLK1, and also
The minimum delay time between the excitation of clock CLK1 and the excitation of clock CLK2 must be observed.

In the prior art, the clocks CLK1 and CL
K2 was generated from the same clock by a fixed delay element. As a result, the conventional positive feedback amplifier circuit has a problem related to the design using the fixed delay element. For example, they are inflexible with respect to changes in operating frequency, have insufficient time margin between clocks, and are non-modular. On the other hand, as in the present invention, a plurality of phase shift clocks are clocked by the clock CLK.
When used to control 1 and CLK2, in the initial state,
It becomes possible to set a sufficient margin time between the clocks CLK1 and CLK2 and set the circuit of FIG. 9 to operate at its maximum frequency. Phase shift clock C
When it is revealed that the margin time initially set between LK1 and CLK2 is insufficient, the operation clock (for example, when the circuit of FIG. 3 is used, the external reference clock signal CLKX ( By reducing the frequency of (306)), this margin time can be easily lengthened, and as a result, the delay between the phase shift clocks CLK1 and CLK2 can be increased. Alternatively, if multiple phase-shifted clocks have been generated and these are locally available, then clocks CLK1 and CLK
It is not necessary to lower the frequency of the external reference clock in order to increase the margin time between the two. Instead, the circuit can continue to operate at a high operating frequency, and the necessary margin time can be obtained by simply selecting a plurality of phase shift clocks suitable for CLK2 from the available phase shift clocks. .

FIG. 10 uses two phase-shifted clocks generated from the same reference clock at two different local locations to minimize the margin between clocks while arbitrating data transfer and processing. It is a schematic circuit diagram which shows the circuit for doing. As shown in FIG. 10, the first circuit unit 7
00 includes an element 702 and a logic circuit portion 704. The first circuit portion 700 receives input data from the conductor 706 and latches this input data using the phase shift clock CLKA. For example, a register or a memory that internally stores the data strobed by the phase shift clock CLKA may be used as the element 702.

Output data from the element 702 is input to the logic circuit section 704. The logic circuit portion 704 is a circuit that performs a logical operation on the latched data and outputs data DATA-R indicating the result of the logical operation on the conductor 708. The DATA-R is transmitted across the chip, through a long conductor as characterized by the load 712 in FIG. 10 and input to the second circuit portion 714. Conductor 708
When the DATA-R transfer is completed through the R and the RC delay associated with the transfer over this long distance occurs, the signal input to the second circuit portion 714 from the conductor 708 is significantly attenuated. there is a possibility. For example, the RC delay associated with load 712 degrades the transition edge, resulting in a gradual rising and falling slope of the pulse of signal DATA-R.

The element 720 of the second circuit section 714 enhances (emphasizes) the strength of the signal input from the conductor 708, and this is applied to the subsequent logic circuit 722 in the second circuit section 714.
Is a circuit that outputs to. For example, when the voltage level of the signal DATA-R becomes higher than a predetermined level, the element 7
20 outputs a high signal and, conversely, the signal DATA-
When the voltage level of R becomes lower than a predetermined level,
Element 720 may be configured to output a low signal. As a circuit suitable for performing such amplification, for example, a positive feedback amplifier as shown in FIG. 10 can be used.

In the circuit of FIG. 10, D on conductor 708
The ATA-R is strobeed by the phase shift clock CLKB before being input to the logic circuit section 722 for the next processing. As is apparent from the above description, in order for the circuit of FIG. 10 to operate properly, it is necessary to excite the clock CLKA and then the clock CLKB, and preferably, the clock CLKB is activated after an appropriate delay time has elapsed. Need to be excited. Here, the delay time between the excitation of the clock CLKA and the excitation of the clock CLKB is at least a time sufficient for the data on the conductor 706 to pass through the element 702, the logic circuit portion 704, and the long conductor 708. Must. Element 70
If phase shift clocks are used to control 2 and 720, respectively, the clocks CLKA and C
A sufficient margin time is set between the LKB and FIG.
Circuit can be set to operate at its maximum frequency. The load 712 has clocks CLKA and C
When it becomes clear that a margin time longer than that initially set with the LKB is required, an input reference clock (for example, clocks CLKA and CLKB using the circuit of FIG. 3 is used. In the case of generating the clock CL and the clock CL, the frequency of the external reference clock signal CLKX (306) is lowered to easily generate the clock CL.
A necessary margin time can be set between KA and CLKB. Alternatively, when a plurality of phase shift clocks are generated and locally available, the frequency of the external reference clock is lowered to lengthen the margin time between the clocks CLKA and CLKB, as described above. No need. Instead, the required margin time can be obtained by continuing the operation of the circuit at a high operating frequency and simply selecting a phase shift clock suitable for the clock CLKB from the plurality of available phase shift clocks.

Although the present invention has been described based on the preferred embodiments for the purpose of facilitating understanding, it can be implemented in various modes without departing from the scope of the invention described in the claims. There is no end. For example, although the details of the PLL circuit have been described, it will be apparent to those skilled in the art that P
The LL circuit can be configured to include a sub circuit such as a filter. Alternatively, although the voltage controlled oscillator of the present invention uses an inverter for the purpose of generating an appropriate delay depending on the frequency, it is also possible to use other types of circuits. Further, although one local clock generation circuit for generating a plurality of phase shift clocks at one local position is described in detail, a plurality of local clock generation circuits each generating the same number or different number of phase shift clocks are described. The local clock generation circuit of 1 may be provided at one local position. In particular, in some applications, in order to generate two sets of complementary phase shift clocks at one local location,
It is desirable to use two local clock generation circuits.
The scope of the invention is not limited by the above embodiments in any way, but is defined by the scope of the claims.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a conventional PLL circuit that centrally generates a plurality of phase-shifted clocks along with the conductors required to transmit the centrally-generated phase-shifted clocks across a chip.

FIG. 2 is a schematic diagram showing an embodiment of the present invention including a PLL circuit according to the present invention and a local clock generation circuit associated with a local position on an IC chip.

FIG. 3 is a schematic circuit diagram showing a PLL circuit of the present invention that generates a reference clock and optionally its complementary reference clock in response to an external reference clock and a feedback clock.

FIG. 4 is a diagram showing details of the PLL circuit of FIG. 3;

FIG. 5 is a schematic circuit diagram showing a complementary voltage generation circuit that generates and outputs a complementary voltage signal in response to an input of a given voltage signal.

FIG. 6 is a schematic diagram showing a circuit for separating a circuit for generating a reference voltage signal from a circuit for generating a reference clock.

FIG. 7 is a schematic circuit diagram showing a local clock generation circuit used to generate a plurality of phase shift clocks at a local position.

8 is a timing chart showing the relationship between the reference clock shown in FIG. 7 and a plurality of phase shift clocks.

FIG. 9 is a schematic circuit diagram showing a positive feedback amplifier circuit as an example of a type of circuit that has the advantage of using multiple phase shifted clocks during operation.

FIG. 10 shows a circuit for arbitrating data transfer and processing while using two phase shift clocks generated from the same reference clock at two different local positions to minimize the margin time between the clocks. The schematic circuit diagram shown.

[Explanation of symbols]

 100 ... Chip 102 ... PLL 104 ... Local position 106 ... Local position 108 ... Local position 111-116 ... Conductor 150 ... PLL circuit 152 ... Local clock generation circuit 154 ... Local clock generation circuit 158 ... Local position 160 ... Local position 170 ... Reference Voltage 172 ... Reference clock 300 ... PLL circuit 302 ... Conductor 304 ... Conductor 306 ... Conductor 308 ... Conductor 310 ... Conductor 312 ... Phase frequency detector 314 ... Up signal 316 ... Charge pump 318 ... Down signal 320 ... Conductor 322 ... VCO (voltage Controlled oscillator) 324 ... Buffer / driver 326 ... Unit gain amplifier 350 ... Simple inverting amplifier 352 ... P-channel device 354 ... N-channel device 356 ... Node 400 ... Open loop phase shift clock generation circuit 402 ... Variable delay stage 404 ... Variable delay stage 406 ... Variable delay stage 408 ... Variable delay stage 414 ... Conductor 416 ... Conductor 418 ... Conductor 420 ... P-channel device 422 ... P-channel device 424 ... N-channel device 426 ... Conductor 428 ... N-channel device 430 ... Conductor 600 ... Feedback amplifier circuit 602 ... Element 604 ... Conductor 606 ... Conductor 610 ... Feedback amplifier element 612 ... Conductor 614 ... Conductor 616 ... Conductor 700 ... Circuit part 702 ... Element 704 ... Logic circuit part 706 ... Conductor 708 ... Conductor 712 ... Load 714 ... Circuit part 720 ... Element 722 ... Logic circuit part

Claims (18)

[Claims] 1. An apparatus for generating a plurality of phase shift clocks at a local position on an IC chip, comprising: a central PLL generating a reference clock and a reference voltage; and a local clock provided at the local position. A generator circuit and a set of conductors for connecting the central PLL to the local clock generator circuit, a first conductor for transmitting the reference clock and a second conductor for transmitting the reference voltage. A set of conductors comprising a conductor, the plurality of phase shift clocks being generated at the local location by the local clock generation circuit using the reference clock and the reference voltage. And a phase shift clock generator. 2. The phase shift clock generator of claim 1, wherein the central PLL further generates a complementary reference clock, and the set of conductors further includes the complementary reference clock. A phase shift clock generator comprising a third conductor for transmission from a central PLL to the local clock generator. 3. The phase shift clock generation device according to claim 2, further comprising a complementary voltage generation circuit which is arranged near the local position and which generates a complementary reference voltage from the reference voltage. Transfer clock generator. 4. The phase shift clock generating apparatus according to claim 3, wherein the complementary voltage generating circuit includes an inverting amplifier. 5. The phase shift clock generator of claim 2, wherein the central PLL comprises a unity gain amplifier for generating the reference voltage signal. 6. The phase shift clock generator according to claim 2, wherein the local clock generation circuit includes a plurality of delay stages, and an output of each of the plurality of delay stages is a phase shift clock. Phase shift clock generator. 7. The phase shift clock generation device according to claim 6, wherein one of the plurality of delay stages is controlled by a complementary reference voltage which is a complementary signal of the reference voltage. A first p-channel device having a channel device gate, an inverter connected in series with the first p-channel device, the inverter input connected to the reference voltage, and for outputting a phase shift clock An inverter output, and a first n-channel device connected in series with the inverter, the first n-channel device having a first n-channel device gate controlled by the reference voltage. And a phase shift clock generator. 8. A method for generating a plurality of phase shift clocks at a local location on an IC chip, the method comprising: providing a central PLL for generating a reference clock and a reference voltage; and localizing at the local location. A step of preparing a clock generation circuit; and a step of connecting the central PLL and the local clock generation circuit with a set of conductors, the set of conductors being a first for transmitting the reference clock. And a second conductor for transmitting the reference voltage, wherein the plurality of phase shift clocks are generated by the local clock generation circuit using the reference clock and the reference voltage. A phase shift clock generation method characterized by being generated by. 9. The phase-shifted clock generation method according to claim 8, wherein the step of preparing the central PLL further comprises the step of preparing a buffer for generating a complementary reference clock. The method of claim 2, further comprising a third conductor for transmitting the complementary reference clock from the central PLL to the local clock generation circuit. 10. The phase shift clock generation method according to claim 9, further comprising the step of preparing a complementary voltage generation circuit for generating a complementary reference voltage from the reference voltage in the vicinity of the local position. A method for generating a phase shift clock, comprising: 11. The phase shift clock generation method according to claim 10, wherein the complementary voltage generation circuit includes an inverting amplifier. 12. The phase-shifted clock generation method according to claim 9, wherein the step of preparing the central PLL comprises the step of preparing a unity gain amplifier for generating the reference voltage signal. Transfer clock generation method. 13. The method of generating a phase-shifted clock according to claim 9, wherein the step of preparing the local clock generation circuit comprises the step of preparing a plurality of delay stages, each output of which is a phase-shifted clock. A method for generating a phase shift clock, comprising: 14. The phase shift clock generation method according to claim 13, wherein the step of preparing the plurality of delay stages comprises a first reference voltage connected to a complementary reference voltage which is a complementary signal of the reference voltage. providing an inverter having a first p-channel device having a p-channel device gate, an inverter input connected to the reference voltage and an inverter output for outputting a phase shift clock, the first p-channel device Connecting in series with a channel device, and connecting in series with the inverter a first n-channel device having a first n-channel device gate controlled by the reference voltage. Clock generation method. 15. A phase shift clock generation method for generating a plurality of phase shift clocks at a local position on an IC chip, comprising: preparing a centrally arranged PLL on the IC chip; Generating a reference clock and a reference voltage signal using a PLL; preparing a local clock generating circuit at the local position; connecting the centrally arranged PLL to the local clock generating circuit; Connecting a first set of conductors for transmitting the reference clock and the reference voltage signal from the PLL to the local clock generation circuit to the local clock generation circuit; and connecting the reference clock and the reference voltage signal to each other. Accordingly, the step of locally generating the plurality of phase shift clocks at the local position using the local clock generation circuit is included. Phase shift clock generation method for the. 16. The method of generating a phase shift clock according to claim 15, further comprising: using a complementary voltage generating circuit to generate a complementary reference voltage that is substantially a mirror image of the reference voltage. Transmitting the complementary reference voltage to the local clock generating circuit and inputting the complementary reference voltage to the local clock generating circuit. 17. The phase shift clock generation method according to claim 16, wherein the local clock generation circuit receives the reference voltage, the complementary reference voltage, and the reference clock as inputs and outputs the phase shift clock. The phase shift clock has a frequency equal to the frequency of the reference clock, and the delay time of the phase shift clock with respect to the reference clock increases when the strength of the reference voltage increases. On the contrary, the phase shift clock generation method wherein the delay time of the phase shift clock with respect to the reference clock decreases when the intensity of the reference voltage decreases. 18. An apparatus for generating a plurality of phase shift clocks on an IC chip, comprising a PLL provided at a first position for generating a reference clock and a reference voltage, and a second position. A local clock generation circuit provided, connected to the PLL and the local clock generation circuit,
A first conductor for transmitting the reference clock from the PLL to the local clock generation circuit; connected to the PLL and the local clock generation circuit;
A second conductor for transmitting the reference voltage from the PLL to the local clock generation circuit, the plurality of phase shift clocks using the local clock generation circuit, the reference voltage and the reference voltage. A phase shift clock generation device, wherein the phase shift clock generation device is generated at the second position according to a clock.