JPH08328996A - Bus repeater and bus repeating system using the same - Google Patents

Abstract

PURPOSE: To effectively utilize common bus resources. CONSTITUTION: Concerning the bus repeater for which a processor side bus 1 and a non-processor side bus 3 are mutually connected through the bus repeater, this device is provided with a reception holding part for sampling/ holding the bus access signals of the buses 1 and 3, repetition control part for discriminating the necessity of repetition based on the held signals in the reception holding part, and transmission control part for outputting the internal held signals to the bus at the repeating destination according to the discriminated output of the repetition control part. Preferably, this device is connected to an external bus arbiter for arbitrating the respective bus right request signals of the buses 1 and 3. Besides, the first bus repeater for connecting the buses 1 and 3 and a second bus repeater for connecting a duplex processor side bus 4 and the bus 3 and blocking the signal output to the bus 3 are provided and when an external duplex collator detects the non-coincidence of collation between the buses 1 and 4, the second bus repeater stops its repeating operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus repeater and a bus repeater system using the repeater, more particularly 1 or 2
A system in which a processor-side bus to which the above-mentioned bus access device is connected and a non-processor-side bus to which one or more other bus access devices (non-processor-side active devices) are connected are mutually connected via a bus relay device. The present invention relates to the bus repeater and a bus repeater system using the repeater.

In recent years, as microprocessor-applied devices have become more sophisticated and have higher performance, the system configurations have become more complex and diversified such as single processors, multiprocessors, memory interleaved multiprocessors, and duplex processors. On the other hand, since the respective elements connected to the processor side and the non-processor side exchange signals of various purposes and modes through a common bus, the functions required for the bus repeater are complicated and diversified. Turn into. Therefore, it is desired to provide a bus repeater and a bus relay system that efficiently relay the bus signals of such a system.

[0003]

2. Description of the Related Art Conventionally, the bus system has been widely used as a means for realizing high-speed communication between a plurality of elements. By inserting a bus repeater into a bus having a long line length or a bus having a large number of connection elements (load), attenuation of a transmission signal can be suppressed. Such a bus repeater has a function of outputting a signal input from one of the divided buses to the other, and by performing this bidirectionally, logical transparency (unity) of the physically divided bus is achieved. ) Has been realized. On the other hand, the bus arbitrator receives a bus right request signal for each element individually when a large number of elements that issue a bus access are installed, arbitrates the bus right according to a predetermined priority, and outputs the result as a bus right grant signal. Has the function of individually notifying.

In the conventional bus repeater, it is guaranteed that the bus arbiter selects one of the system bus masters so that a bus access collision does not occur.

[0005]

However, in a complicated and diversified system, if the bus right of the system is limited to one, the common bus resource cannot be effectively used. In addition, if the common bus resources are not effectively used, there will naturally be limits to the high functionality and high performance of the system. An object of the present invention is to provide a bus repeater that can effectively utilize common bus resources and a bus relay system using the repeater.

[0006]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the bus repeater of the present invention (1) is a bus repeater in which a processor-side bus connected to one or more bus access elements and a non-processor-side bus connected to another one or more bus access elements are bus repeaters. In the bus repeater of a system connected to each other via a reception holding unit R for sampling and holding bus access signals of a processor side bus and a non-processor side bus, and determination of necessity of relay based on a holding signal of the reception holding unit And a transmission control unit that outputs an internal hold signal to the relay destination bus according to the determination output of the relay control unit.

The bus relay system of the present invention (13) is 1
Alternatively, a processor-side bus to which two or more bus access elements are connected, a non-processor-side bus to which another one or two or more bus access elements are connected, and a redundant processor-side bus to which a plurality of other bus access elements are connected are In a bus relay system of a duplex system in which serial connections are made via first and second bus repeaters, a first bus repeater connecting a processor side bus and a non-processor side bus, a dual processor side bus and a non-processor A second bus repeater that connects the two side buses and is prevented from outputting a signal to the non-processor side bus, and the second bus repeater has an external duplication collator as the processor side bus and the duplication processor side bus. The relay operation is stopped by detecting the collation mismatch between them.

[0008]

In the bus repeater of the invention (1), the reception holding unit R samples and holds the bus access signals of the processor side bus and the non-processor side bus. The relay control unit determines whether relay is necessary or not based on the signal held by the reception holding unit R. Then, the transmission control unit D outputs an internal hold signal to the relay destination bus according to the determination output of the relay control unit.

According to the present invention (1), since there are three stages of reception holding, relay determination, and transmission control, these can be effectively processed even if the bus accesses of bus → and bus → compete. Preferably, the sampling hold signal is sequentially shift-transferred by clock signals having different phases, and in parallel with this, the necessity of relay is determined, and the output control of the relay destination transmission control unit is performed. In this way, relay control of the bus → and the bus → can be realized at high speed and with high reliability.

Further preferably, the relay control unit does not relay the closed bus access signal of the processor side bus or the non-processor side bus. Therefore, the common bus resources of the system can be divided into two to make effective use of them. Further preferably, the relay control unit relays and outputs the bus access signal in which the processor-side bus is closed to the non-processor-side bus by setting the forced relay. For example, in the case of performing in-circuit emulation using ICE, even if the bus access signal of the processor side bus is closed, if it can be monitored by the non-processor side bus, the operation of the entire system can be grasped, convenient. This relay function is very effective in this case.

Preferably, the relay control unit relays (bus snoops) the memory write access signal in which the non-processor side bus is closed to the processor side bus depending on the setting. A closed memory write access of the non-processor side bus means modification of the memory contents, which is an important concern for the processor side bus access device. This relay function is very effective in this case.

Further, preferably, when the closed bus access of the processor side bus or the non-processor side bus and the relay output to the processor side bus or the non-processor side bus compete, the relay control section holds the relay output. At the same time, it waits for the end of the closed bus access and shifts to the relay output operation. Therefore, collision of bus access can be effectively avoided, and common bus resources can be effectively utilized.

Preferably, the relay controller holds the relay output to the processor side bus or to the non-processor side bus when the relay outputs to the processor side bus and the non-processor side bus compete with each other. Alternatively, the retry signal is asserted to the bus master of the non-processor side bus, and the relay output operation is started after the completion of the bus access of the processor side bus or the non-processor side bus. Therefore, collision of bus access can be effectively avoided, and common bus resources can be effectively utilized.

Further, preferably, the relay controller is connected to an external bus arbiter for arbitrating each bus right request signal of the processor side bus and the non-processor side bus, and the relay controller is connected to the processor side bus and the non-processor side bus. The relay request signal is output to the bus arbitrator, and the relay output operation is performed according to the relay permission signal from the bus arbitrator. As described above, the bus repeater of the present invention can effectively avoid bus access collision to some extent even by itself. By the way, considering the meaning of the relay request signal generated by the relay controller determining whether or not the relay is necessary, the relay request signal to the bus is the bus right request signal for the bus, and the relay request signal to the bus is the bus request signal for the bus. It is nothing but a right request signal. Therefore, the relay request signal is output to the bus arbitrator, the bus right is arbitrated together with other bus right request signals, and the relay output operation is performed in accordance with the relay permission signal from the bus arbitrator. .
In this way, conflict between the bus access at the relay destination and the relay output can be avoided in advance, and the relay operation can be performed more smoothly.

Further preferably, the function of the bus arbitrator and the function of the bus repeater are integrally provided. Also preferably, the setting prevents signal output to the one-sided bus. This function is extremely useful when constructing the double matching processor system of FIG. In the figure, each bus access element (CPU) connected to the processor side bus and each bus access element (C connected to the duplex processor side bus
PU) operates in the same way. For this purpose, the first and second bus repeaters must operate in the same way. However, when the bus-> bus access relay signal and the bus-> bus access relay signal overlap, the system will be seriously adversely affected if a slight timing shift or some abnormality occurs on the duplex processor side. Therefore, signal output to the non-processor side bus of the second bus repeater is blocked. Even in this case, it does not affect the operation of the remaining components.

Further, preferably, forced relay can be set for each bus access element connected to the processor side bus. In this way, it is possible to focus on any specific bus access element and monitor its entire operation, which is effective in the system development and maintenance stages. Further, preferably, the relay control unit has a function of changing the level of a predetermined relay output signal according to the setting and outputting the signal. This function is very useful when testing the matching function of the dual matching device of FIG.

In the figure, when the duplex system is operating normally, the bus and bus signals are the same. However, just because the duplicated collator does not output the collation non-match signal does not mean that the duplicated collator is functioning normally. Therefore, the relay control unit of the second bus repeater of this example outputs the signal to the bus by changing the level of the predetermined relay output signal (level inversion or level fixing) according to the setting among the signals relayed to the bus →. Let If the duplicated collator is normal, a collation mismatch is output. If the setting is changed, the verification function for all bus access signals can be confirmed. It is obvious that even if the above-mentioned test (pseudo-normality test) is performed while the system is operating, it does not affect the operation of the bus and the bus.

In the bus relay system of the present invention (13), the first bus relay device connects the processor side bus and the non-processor side bus. The second bus repeater connects the dual processor side bus and the non-processor side bus and blocks the signal output to the non-processor side bus. That is, a duplicated collation system is configured as a whole. Then, the second bus repeater stops the relay operation when the external duplication collator detects a collation mismatch between the processor side bus and the duplication processor side bus.

If the duplicated collator detects a mismatch, it is considered that there is an abnormality on the bus side and an abnormality on the bus side.
When the bus side is abnormal, an abnormal signal circulates to the bus side via the second bus repeater and adversely affects the bus side. If the bus side is abnormal, it is better to disconnect the bus side from the system. Therefore, in this example, the relay operation of the second bus repeater is stopped. In this way, the bus side is completely separated from the bus side, and the respective states can be saved.

[0020]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. Further, in this embodiment, an LSI chip that integrally includes a bus arbiter (bus arbiter) and a bus repeater is called a bus repeater (CBC).

FIG. 2 is a block diagram of an example in which the bus repeater of the embodiment is applied to a single processor system. In the figure, 10 is a processor, 20 is a non-processor, MPU is a microprocessor unit, CCM is a cache controller memory, MAC. Is a memory controller, MEM
Is a memory, CBC is a bus repeater, BIC is a system bus interface, SCU is a system controller, MB
C is a maintenance bus controller, TRC is a bus tracer trace controller, TRM is a trace memory, is an internal bus (M bus) of the processor 10, is an external bus (W bus), and is a system bus (S bus).

Since one MPU 0 exists in the processor 10 of this example, it is called a single processor system. The MPU0 on the processor 10 side is connected to the M bus via CCM0. Therefore, MPU0 (C
A bus right request is generated by CM0). On the other hand, MPUB and MPUS (nonprocessor active element) on the nonprocessor 20 side are connected to the W bus via the BIC and SCU, respectively. The TRC is not an active element, but has a function of requesting the bus right of the W bus when it is necessary to temporarily stop the bus access when storing the bus access information of the W bus in the TRM. Therefore, on the W bus, BIC,
A bus right conflict occurs between SCU and TRC. Furthermore,
When these perform bus access, depending on the address space of the bus access, the bus → and / or the bus →
A relay request to is also generated. The example CBC0 arbitrates contention in all of these cases effectively and quickly.

Although not shown, the MPU 0 is connected to the MPU 0 side.
A so-called non-interleaved multiprocessor system in which CMPs 1 to 3 are newly provided and CCMs 1 to 3 are connected to the MPUs 1 to 3 is also conceivable. FIG. 3 shows the details of the connection in the CBC single processor configuration of the embodiment. FIG. 4 is a block diagram of an example in which the bus repeater according to the embodiment is applied to an interleaved multiprocessor system. In the figure, 10 is a master processor, 20 is a non-processor, 30 is a dual matching processor, and MAT is a dual processor. Collator,
, Is an internal bus (M bus) of the master processor 10,
Is an outer bus (W bus), and is an inner bus (M bus) of the duplex processor 30.

Since the master processor 10 of this example has four MPUs 0 to 3, it is called a multiprocessor system. Further, the MPUs 0 to 3 share the MEMs 0 and 1 via the two CCMs 0 to 3, respectively, and have a structure in which they are tightly coupled to each other (memory interleave). On the other hand, the MPUs 0 to 3 of the duplex processor 30 perform the same processes and operations as the MPUs 0 to 3 of the master processor 10, respectively. Therefore, CBC (←) and CBC (→) are CBC respectively
(0), functions as CBC (1), but CBC
Relay output signals of (←) and CBC (→) to the W bus are always blocked. Therefore, it has no influence on the W bus (system operation). In this state, MAT0
Checks the bus access operation of the M bus,
The MAT1 performs a collation check of the bus access operation of the M bus.

Although not shown, a memory non-interleaved configuration is provided between MPUs 0 to 3 and MPUs 2 and 3 are also provided.
A so-called non-interleaved multiprocessor system in which the M bus is provided on the M bus side is also conceivable. FIG. 5 shows the details of the connection of the CBC (0) and CBC (1) of the embodiment in the interleaved multiprocessor configuration. Each CBC of Examples
The chips have the same structure, and change to CBC (0), (1), (←), (→) of various functions by external setting. For example, mode setting signal MODE0 = L * MODE1
= L (Fig. 3), CB in single processor configuration
It becomes C (0). In addition, MODE0 = L * MODE1 = H
In the case of (Fig. 5), CBC in multiprocessor configuration
(0) and CBC (1). Further, when the one-way relay setting signal DIRC = H, CBC (←), CBC
It becomes (→).

Each CBC operates in the following five modes depending on the terminal (working) setting and the register setting. C in Table 1
The relationship between the setting of BC and the operation mode is shown.

[0027]

[Table 1]

However, / represents inversion logic, and x represents no care. The memory interleave signal / ILEV specifies presence / absence of the memory interleave configuration. A single processor is always treated as non-interleaved. The arbitration master signal / BAMM specifies which of the CBCs is the arbitration master and which is the arbitration slave. / BAMM = L is the arbitration master CBC (O), and / BAMM = H is the arbitration slave CBC (1). The compulsory relay signal NCHK indicates whether or not the M bus or the closed bus access is compulsorily relayed to the W bus side. Originally, it is not necessary to relay the processor side bus or the closed bus access to the non-processor side bus. However, in-circuit emulation may be performed using ICE, for example, during system debugging, and in this case, the forced relay function is useful.

Mode (1) is "non-interleaved" *
It is a "forced relay", and there is a forced relay from bus to bus even if the bus access is closed on the M bus. In this case, the bus right is limited to one, and CBC (0) arbitrates the bus right together with the bus. Mode (2) is "non-interleaved" * "non-forced relay", and two bus rights can be generated. CBC (0) arbitrates for the bus within the bus and separately for the bus within the bus.

Mode (3) is "interleave" * "avitation master" * "forced relay". Even if the bus access is closed by bus, there is forced relay to bus → to bus or to bus →. Therefore, the bus right is limited to one, and the arbitration master CBC (0) is
The bus right is arbitrated together with the bus. Mode (4)
"Interleave" * "Abitration Master" *
It is "non-forced relay". Aviation Master CBC
(0) arbitrates between buses for bus, and arbitrates for buses separately within the bus.

The mode (5) is "interleave" * "aviration slave". The arbitration slave CBC (1) first independently performs arbitration within the bus, and outputs an arbitration request signal to CBC (0). Next, the feedback signal of the arbitration result from the CBC (1) is received, and the bus right of the bus is granted according to the feedback signal. FIG. 6 is a functional block diagram of the bus repeater according to the embodiment.
Is a bus repeater (CBC), 101 and 102 are 3-state type bus drivers (D), 103 and 104 are also bus receivers (R), 105 is an internal bus reception holding unit, 1
Reference numeral 06 is an outer bus reception holding unit, 107 is an inner bus relay determination unit, 108 is an outer bus relay determination unit, 109 is a relay request collision detection unit, 110 is an inner bus transmission control unit, 111 is an outer bus transmission control unit, and 112 is Retry response control unit, 200
Is a bus arbiter (bus arbitrator).

The receiving and holding units 105 and 106 are respectively M buses,
Receives and holds the bus access signal of the W bus. The relay determination units 107 and 108 determine the position of the bus master and the position of the bus slave (element controlled by the bus master) based on the bus access signals of the reception holding units 105 and 106. The position of the bus master is determined by detecting the bus start signal BS. When MBS is detected, the processor side is the bus master, and when WBS is detected, the non-processor side is the bus master. The position of the bus slave is determined from the contents of the address signal MAD [0:31] when BS is asserted (energized).

FIG. 7 is a diagram for explaining the address space of the bus slave of the embodiment. The address space has a memory space and a control space, and these types are identified by a bus access type signal BAT [2: 0]. BAT [2:
0] = [000] indicates data access (memory space access), [100] indicates instruction access, [010] indicates interrupt response access, and [110] indicates control space access.

FIG. 7A shows a memory space,
When MAD [0: 7] <FF and outside the IM window, it points to the outer memory space, and IMLA ≦ MAD [0:11]
<IMUA indicates the inside of the IM window (inner memory space), and MAD [0: 7] ≧ IBMA indicates the inner memory space. FIG. 7B shows the control space. When MAD [0: 7] <FF, it indicates the control space outside the processor board (S bus), and MAD [0: 7] = F.
F, MAD [8: 9] = no care, MAD [10: 1
5] <ICBA indicates the outer control space (inside each chip of BIC, SCU, TRC) in the processor board, and MAD [0: 7] = FF, MAD [8: 9] = no care, MAD [ 10:15] ≧ ICBA indicates the inner control space (M bus /).

FIG. 7C shows the CBC control space, where MAD [0: 7] = FF and MAD [10:15] =.
[110011], MAD [23] = 0, and the others are CBC (0) when not cared, and under the same conditions, MAD [23]
When = 1, it means CBC (1). The determination of the bus slave position will be specifically described with reference to the configuration of FIG. When MAD refers to the inner memory space, the IM window, or the inner control space, it is determined to be the processor side (M bus), and the MAD is the outer memory space and outside the IM window, the outer control space,
Non-processor side (W bus) for interrupt response access
Judge. If MAD points to the CBC control space and MAD [23] = 0, it is determined to be CBC (0).
The same applies to the configuration of FIG. However, even when it is determined to be the processor side, it is determined to be the M bus side when MAD [23] = 0 and the M bus side when MAD [23] = 1.

The relay determination units 107 and 108 determine whether or not the relay of the bus access signal is necessary based on the CBC mode setting and the positional relationship between the bus master and the bus slave. Table 2 shows a list of judgments as to whether or not relay is necessary.

[0037]

[Table 2]

However, ◯: Relay is present Δ: Relay is performed in the case of memory space write access, and others are not relayed ☆: CBC (0) relays only MAD [23] = 0 access CBC (1) MAD Relaying only access of [23] = 1 means x: no relaying, respectively. Bus master =
M, bus slave = M or C {= CBC (O) / CBC
In the case of (1)}, the access is M bus / closed access or M bus / → CBC (O) / CBC (1) access, and the relay destination is the W bus. In the case of a single processor, it relays unconditionally, but in the case of a multiprocessor, it relays only when forced relay is specified.

When the bus master = M and the bus slave = W, the access is M bus / → W bus and the relay destination is the W bus. Bus master = W, bus slave = W
In the case of, the W bus is a closed access, and the relay destination is the M bus /. However, in the case of the memory space write access, the relay is performed, and the others are not relayed. By relaying the closed memory write access on the non-processor side to the processor side (bus snoop), memory management by the processor side is enabled.

When the bus master = W and the bus slave = M, the access is W bus → M bus /, and the relay destination is M bus /. In the case of a single processor or a non-interleaved multiprocessor, it relays unconditionally, but in the case of an interleaved multiprocessor, MAD
When [23] = 0, relay to M bus, and MAD [23]
When = 1, relay to M bus.

Bus master = W, bus slave = C {CB
In the case of C (O) / CBC (1)}, W bus → CBC
(O) / CBC (1) access, and the relay destination is the M bus /. However, this is not relayed. Table 3 shows the signals to be relayed for bus access and the relay directions.

[0042]

[Table 3]

Bus start signal BS, data start signal DS, bus access type signal BAT, read / write signal RW, data 32 byte block transfer signal BL3
2, the data 16-byte block transfer signal BL16 and the like are bus master access signals. The address / data signal AD and these parity signals ADP are time-divisionally transferred on the same bus. The data complete signal DC, the bus error signal BERR, the retry signal RETRY, etc. are signals which the bus slave returns to the bus master. Table 4-
Table 6 shows the relay condition and relay timing of each signal.

[0044]

[Table 4]

[0045]

[Table 5]

[0046]

[Table 6]

When the address space for bus access satisfies the conditions of bus M → W and bus W → M, the relay determination units 107, 108 relay request signal HREQ-M2W from inside to outside,
The relay request signal HREQ-W2M from outside to inside is output. Therefore, depending on the mode of bus access, contention with the bus right request signal occurs on the M bus and W bus.
The mode of bus access and its contention control in the multiprocessor mode and when no forced relay is specified will be described below. (1) Since the relay request signal is not generated between the closed access of the M bus (no relay) and the closed access of the W bus (no relay), no conflict occurs. (2) In the case of closed access of the M bus (without relay) and relay of W bus → M bus, the contents of the W bus address cycle are held and the completion of the access of the M bus is waited. Then, the content held in the W bus is output to the M bus for one cycle, and the transition from the next cycle to the relay operation is performed. Output from the W bus to the M bus is performed on condition that HACK-W2M is asserted. (3) In the case of closed access of W bus (no relay) and relay of M bus → W bus, it is the reverse of (2) above. Output from the M bus to the W bus is performed on condition that HACK-M2W is asserted. (4) In the case of M bus → W bus relay and W bus → M bus relay, both HREQ-M2W and HREQ-W2M occur. In this case, the content of the W bus address cycle is retained, and the relay request collision detection unit 109 activates the inner bus transmission control unit 110 and the retry response control unit 112 to autonomously retry the bus master of the M bus. Ends access by asserting response. After the access to the M bus is completed, the content held in the W bus is output to the M bus for one cycle, and the transition from the next cycle to the relay operation is performed. Bus arbiter 200 is C of M bus that returned a retry
The bus right is given to the CM preferentially after the relay is completed.

However, when the MCM CCM asserts IBWS (EM block copyback request), a retry is asserted to the W bus bus master, and the MCM CCM access is relayed with priority. EM (effe
The block copyback request is one mode of copyback cache operation, and is generated when a flag indicating that the content of the cache memory has been updated is detected. (5) In the case of M bus closed access (no relay) and W bus closed memory write access to M bus (bus snoop), the contents of the W bus address cycle are retained and the M bus Wait for access to end. After that, M
The content held in the W bus is output to the bus for one cycle, and the relay operation starts from the next cycle.

In FIG. 6, the outer bus transmission control unit 1
When 11 is designated as one-way relay (DIRC = 1), the bus driver 102 remains deenergized (to output high impedance). That is, CBC (←), CBC in FIG.
It becomes (→). Others function similarly to CBC (0) and CBC (1). Also, although not shown, MAT0 / 1 detected CBC (←) / CBC due to detection of a mismatch.
The function of (→) can be stopped. In this case, the bus driver 101 has an output high impedance.

FIG. 8 is a block diagram of the hardware configuration of the bus repeater of the embodiment, and shows each functional block of FIG. 6 from the viewpoint of the hardware configuration. In the figure, 121 is an inner bus input retiming unit, 122 is an outer bus input retiming unit, 123 is an inner bus output selection retiming unit, 124 is an outer bus output selection retiming unit, and 125.
Is a register interface unit, 126 is a register unit, 1
27 is a relay controller. The relay controller 127 is shown in FIG.
Relay determination units 107, 108 and relay request collision detection unit 10
9 etc. are included.

In the CBC of the embodiment, CLK1, which has different phases,
The pipeline operation using CLK2 realizes a high-speed and highly reliable relay operation. CLK2 is 3φ / 4 more than CLK1 as shown in the timing chart described later.
(However, φ is one cycle) The phase is delayed. Looking at this conversely, CLK2 leads the phase of CLK1 by φ / 4.

The signal on the bus changes in synchronization with CLK1. The inner bus input retiming unit 121 samples and holds the signal on the M bus in a first register (not shown) with CLK2, and further holds its output in a second register (not shown) with CLK1. The output M of the first register is input to the relay controller 127, where it is sampled and held by CLK1. The output M of the second register is for register access in the CBC and is input to the register interface unit 125 as it is. The relay control unit 127 performs the above-described processing such as relay determination and collision detection in synchronization with CLK1. The signal M → W to be output (relayed) to the W bus side is selected in synchronization with CLK2. At the same time, the outer bus transmission control unit 111 causes the CLK2
The bus driver 102 is energized by. Then, the selected signal M → W is selectively latched by the outer bus output selection retiming unit 124 by CLK1 immediately after CLK2. This becomes a relay output on the W bus via the bus driver 102. In this embodiment, the bus bus driver 102
Bus start signal B on W bus
The rising / falling part of S etc. appears without fail. W
The same applies to the case of relaying from bus to M bus.

The register section 126 includes a plurality of register groups for holding various setting information and control information, and constitutes a CBC control space. The register unit 126 receives control data from the M bus or W bus via the register interface unit 125 and sends back a necessary register response signal. The CBC of the present embodiment can operate in various modes according to various register setting information of the register unit 126. For example, by setting the register of the register unit 126, it is possible to set only the CCM having a specific processor ID as the target of forced relay.

Here, the notification of the processor ID will be described. CBC recognizes bus master, M bus, W
Notify the bus master (CCM0-3, non-processor) to the bus side. Table 7 shows the relationship between PID, NM and bus master.

[0055]

[Table 7]

For example, PID = [LL] * (/ NM) = H
CCM0 is the bus master in the case of, and the non-processor side is the bus master in the case of / NM = L regardless of the PID. When the CBC is performing the relay operation of M → W and W → M, both M and W send the same PID and NM, but M
If there is a bus master in W and W, and each performs a closed access, NM (however, PID
Are the same in both directions) but different. CBC is each bus right grant signal / MHACK [0: 3] and / WHACK on M side and W side
[S, B, T] are constantly monitored individually, and the processor ID [PID, MN] is generated based on them. However, as the PID, both the M and W sides send out the PID generated on the M side. Table 8 shows the correspondence between MHACK, PID and MNM, and Table 9 shows the correspondence between WHACK and WNM.

[0057]

[Table 8]

[0058]

[Table 9]

Returning to the main subject, the register section 126 is provided with a chip control register CCSR (not shown), part of which is a compulsory relay target processor ID designation field MPID [24:25], ID which can be externally read / written. It has a designated validity instruction field IDEN [26], a forced relay designation field NCHK [27], and the like. MPID
At [24:25], the processor I to be forced to relay is
Specify D. IDEN [26] = 0 invalidates the processor ID designation when the forced relay is designated (that is, all the processors are targets of the forced relay). When IDEN [26] = 1, only the processors designated by MPID [24:25] are designated for forced relay when forced relay is designated. NCHK
= O is a normal relay designation (that is, whether relay is necessary or not is determined by the relay determination unit 10).
7, 108 relay necessity determination), and NCHK = 1
Is a forced relay designation.

As described above, the relay control unit 127, if "external forced relay designation" = 1, NCHK = 1, IDEN = 1 and the bus right grant signal HREQ = 1 of the designated processor ID are satisfied, only the designated processor Performs forced relay control of. Also, "External compulsory relay designation" = 1, NCHK =
When 1, IDEN = 0, forced relay control of all processors is performed unconditionally. In addition, "External compulsory relay designation" is NC
This is a signal that determines whether forced relay control by HK is enabled or disabled. It is valid when the external setting terminals MODE0 = L * MODE1 = H, and when OPMD = 0, “external forced relay designation” = 0 and OPMD When = 1, “external forced relay designation” is set to 1.

Further, the CBC of this embodiment has a register unit 12
It is possible to fix or invert the signal level relayed to the processor side bus in various ways by the register setting information of 6. This function (quasi-normal relay test function) is effective in checking whether or not the matching check function of MAT0, 1 in the configuration of FIG. 4 works normally. For example, M
Focusing on AT0, it performs a collation check for bus access on the M bus. Therefore, I would like to confirm the matching inspection function of MAT0. In this case, the following setting / control is performed for CBC (←).

The register unit 126 has six MAT function test control registers MTCR0-5 (not shown).
A setting field TSTG [2] of a test execution instruction signal capable of being externally read / written in part of MTCR0
9]. If bit "1" is written to this TSTG [29], only the CBC (←) designated for one relay will have an abnormal bus access according to the fault instructions in the following fields at the first relay from the non-processor side to the processor side. Perform relay operation. It should be noted that the CBC for which bidirectional relay is designated
(0) performs normal bus access regardless of the following abnormal indications in the fields. In addition, CBC (←) has an abnormal non-processor side → after the relay to the processor side, the field settings of all registers MTCR0 to 5 are cleared, and the relay from the second non-processor side to the processor side is normally relayed. I do. However, when MAT0 inputs a detection signal of mismatching of matching to CBC (←), this causes CBC
It is also possible to stop all the functions of (←) and fix the output to the processor side bus to high impedance.

As a setting field for which an abnormality can be designated,
BS [30], DC [31] in MTCR0, and BAT [0: 2], R / W [3] in MTCR1,
AP [4: 7], BC [8:15], BL [16: 1
7], LOC [18], DS [19], MPID [2
0:21], NM [22], RTRY [23], BER
R [24], BEM [25:27], DP [28: 3
1], and address signal abnormality instructions A [0:31], A [0:31] in MTCR2, 3 and MTCR4.
5 data signal abnormality instruction D [0:31], D
[0:31] and so on.

The BS, DS and DC signals are normally relayed when the instruction = 0 and not relayed (fixed to the HIGH level) when the instruction = 1. Regarding the remaining signals, when the instruction = 0, the normal relay is performed, and when the instruction = 1, the signal inversion relay is performed. When the write operation on the non-processor side is relayed to the processor side, the address signal,
Although both data signals are subject to inversion relay, when relaying the read operation from the non-processor side to the processor side,
Since the data signal of the data cycle is generated on the processor side, it is not the target of the inversion relay. The above is CBC
The same applies to (→).

FIG. 9 is a block diagram of a bus arbiter of the embodiment. In the figure, 201 is an inner bus right request auxiliary signal arbitration unit, 202 is an inner bus right request signal arbitration unit, 203 is an outer bus right request signal arbitration unit, and 204 is Arbitration unit between multiple buses (I
LEVA) and 205 are internal bus right permission signal generation units (MA
CKG), 206 is an outside bus right permission signal generator (WAC)
KG) and 207 are inside bus retry monitoring units (MRTY).
G) and 208 are outside bus retry monitoring units (WRTY)
G) and 209 are arbitration request signal generation units (ILR) between a plurality of buses.
QG) and 210 are selectors (SEL).

The inner bus right request auxiliary signal arbitration unit 201 includes an auxiliary signal arbitration unit (IBWSA) and a priority control unit (IBWS).
P) and. The auxiliary signal arbitration unit IBWSA inputs the auxiliary signal (EM write back request signal in this example) IBWS
Arbitration of [3: 0] is performed, and an arbitration result signal IB [3: 0].
Is output. The priority of the auxiliary signal IBWS [3: 0] is given by the priority signal IP [1: 0]. Table 10 shows the contents of the arbitration result signal IB [3: 0]. Table 11 shows the priority order of IBWS (that is, CCM).

[0067]

[Table 10]

[0068]

[Table 11]

The priority order of CCMs 0 to 3 depends on the content of the priority signal IP. That is, IP = [0
0] for CCMO, [01] for CCM1,
CCM2 for [10], CCM3 for [11]
Is the highest priority, respectively. The priority control unit IBWSP sets the arbitration result signal IB [3: 0] of the auxiliary signal arbitration unit IBWSA to CL.
The next priority signal IP [1: 0] is determined based on the signal IBOUT [3: 0] which is sampled at K1 and internally held. The priority signal IP [1: 0] is determined by rotation priority control (round robin). FIG. 10 shows the state transition control of the priority control unit IBWSP. Table 12 shows a description of each state.

[0070]

[Table 12]

Initially, CCM0 is generated by the reset signal RST.
-Idle (that is, IP = [00], IBOUT = [0
000]) and CCM0 (that is, IBWS
0) is the highest priority. In this state, for example, IBWS0 =
Assuming that 1 and IBWS2 = 1 are asserted at the same time,
IBWS0 = 1 is selected, and the arbitration result signal IB [0] =
[0001] is output. Therefore, in the next CLK1, I
BOUT [3: 0] = [0001] and the state is CC
M0-act (IP = [01], IBOUT = [000
1]). In this state, CCM1 has the highest priority, and the CCMO selected immediately before is turned to the lowest.

In the state of CCM0-act, CCM1 has the highest priority, but IBWS1 = 0 at this point,
IBWS2 = 1 is selected and IB [2] = [0100]
Is output. Therefore, in the next CLK1, IBOUT =
[0100], and the state is CCM2-act (IP =
[11], IBOUT = [0100]). In this state, CCM3 has the highest priority, and CCM2 selected immediately before is turned to the lowest. Furthermore, in this example, IBW
When S2 = 0, IB = default [0000] is output, which causes CCM3-idle (IP = [1
1], IBOUT = [0000]).

In the above round robin method, the selected CCM is set to the lowest rank, but the present invention is not limited to this. For example, each time some IBWS is selected, the priority signal IP is simply [00] → [01] → [10] → [11].
→ A method of turning [00] may be used. The inner bus right request signal arbitration unit 202 includes a bus right request arbitration unit MREQA and a priority control unit MREQP. Bus right request arbitration unit MRE
QA is an input bus right request signal (hold request) H
Bus arbitration for REQ [3: 0] and relay request signal HREQ-W2M is performed, and arbitration result signals RS [3: 0] and RS-W2M are output. Bus right request signal HREQ
The priority for [3: 0] is the priority signal R
It is given by P [1: 0]. Table 13 shows arbitration result signal RS
[3: 0] shows the contents of RS-W2M. Table 14 shows the priority control of the bus right request arbitration unit MREQA.

[0074]

[Table 13]

[0075]

[Table 14]

The priority of CCM alone is the lowest. Priority signal RP when multiple CCMs compete
It is determined by [1: 0]. Priority signal RP
The relationship between the priority order of [1: 0] and CCMs 0 to 3 is the same as in Table 11. However, when the bus access of the CCM is completed by the retry, the HREQ of the CCM is waited and the HREQs of other CCMs are not accepted. C receiving a retry
The CM negates HREQ to release the bus right, secures the bus right again, and performs the same bus access (retry). HREQ-W2M is always given a higher priority than retry. However, when the CCM asserts IBWS, in order to prioritize the EM block write back request, the HREQ of the CCM that asserted the IBWS is waited for, and the HREQ and HREQ-W2M of other CCMs are not accepted. Note that the IBWSA has already been selected as one IBWSA. Therefore, when a plurality of CCMs assert IBWS, the HR of the CCM selected by the IBWSA is selected.
Give priority to EQ.

The bus right request arbitration unit MREQA has HREQ.
The signal and the HACK signal are constantly monitored, and the bus permission signal HACK of the arbitration result is held until the element that has acquired the bus right negates the HREQ, and the HREQ and IBWS of other CCMs are not accepted. Table 15
Shows the relationship between the forced relay designation and HREQ-W2M.

[0078]

[Table 15]

In the case of forced relay, HR is set inside MREQA.
The input of EQ-W2M is invalid. In forced relay, since the M bus and W bus are integrated and arbitrated, HREQ-W2M occurs only while the M bus is open. Therefore, it is not necessary for the bus arbiter 200 to hold the M bus for the purpose of HREQ-W2M. In case of non-forced relay, arbitration is performed separately for M bus and W bus, so HREQ-W
A 2M input is valid.

The priority control unit MREQP receives the arbitration result signal RS.
The next priority is determined based on [3: 0], and the priority signal RP [1: 0] is output. FIG. 11 shows the state transition control of the priority control unit MREQP. In state CCM0, CCM0 has the highest priority when RP = [00], in state CCM1 RP = [01] has CCM1 the highest priority, in state CCM2 RP = [10] has CCM2 the highest priority, and in state CCM3 RP = [11] Therefore, CCM3 has the highest priority. The state transition conditions are as follows.

COND0 = (/ IB [0]) * (/ RTY [0]) *
RS [0] * HACK [0] COND1 = (/ IB [1]) * (/ RTY [1]) *
RS [1] * HACK [1] COND2 = (/ IB [2]) * (/ RTY [2]) *
RS [2] * HACK [2] COND3 = (/ IB [3]) * (/ RTY [3]) *
RS [3] * HACK [3] However, / represents inversion logic and * represents logical product. (/ IB
Since there is a condition of [n]) * (/ RTY [n]), R
If the CCM notified by S [3: 0] asserts IBWS, or if it is a retry, the priority is not updated.

First, the reset signal RST causes the state CC.
In M0. Perform COND0 in state CCM0 (ie
(HACK0 is given to CCM0) and state CCM1 is entered, and CCM0 given HACK0 is turned to the lowest. Similarly, when COND2 is performed in the state CCM1, the state transitions to the state CCM3, and when COND3 is performed in the state CCM3, the state transitions to the CCM0.

The outer bus right request signal arbitration unit 203 is composed of a bus right request arbitration unit WREQA and a priority control unit WREQP. The bus right request arbitration unit WREQA receives an input bus right request signal (hold request) HREQ-B, HRE.
Q-S, HREQ-T and relay request signal HREQ-M2
W (= master side), HREQ-SLV (= slave side HREQ-M2W) is arbitrated, and an arbitration result signal RS-
B, RS-S, RS-T, RS-M2W, RS-SLV
Is output. Table 16 shows the contents of the arbitration result signal RS.
Table 17 shows WREQA priority control.

[0084]

[Table 16]

[0085]

[Table 17]

The TRC request HREQ-T is given the highest priority. Next, bus snoop relay (master side) = HREQ-M
2W * SNOOP-M and bus snoop relay (slave side) = HREQ-SLV * SNOOP-S are given priority in order. Priorities are BIC bus busy signal BB
It depends on the contents of SY. If the BIC lists BBSY = 1, then HREQ-B is prioritized. In this case, HEREQ-S, relay request (master side) = HREQ-M
2W * (/ SNOOP-S) and relay request (slave side) = HREQ-SLV * (/ SNOOP-S) are invalid.

If the BIC does not list BBSY = 1, then the relay request (master side) = HREQ-M2W and the relay request (slave side) = HREQ-SLV are given priority in order. Next, priority is given to HREQ-B and HREQ-S. HR
When the EQ-B and the HREQ-S compete with each other, it is determined by the priority signal RP [0] based on the rotation priority control. If there is another retry, the hold request for the element is waited for, and no other hold request is accepted. Table 18 shows an outline of priority control on the W bus side. Table 19 shows the relationship between the forced relay designation and HREQ-M2W.

[0088]

[Table 18]

[0089]

[Table 19]

In case of forced relay, HR is set inside WREQA.
The input of EQ-M2W is invalid. In the forced relay, since the M bus and the W bus are integrated and arbitrated, the HREQ-M2W is generated only while the W bus is open. Therefore, it is not necessary for the bus arbiter 200 to hold the W bus because of the HREQ-M2W. In the case of non-forced relay, HREQ-M
Input of 2W is valid.

The priority control unit WREQP determines the next priority order based on the outputs RS-B and RS-S of the bus right request arbitration unit WREQA, and determines the 1-bit priority signal RP.
Outputs [0]. FIG. 12 shows the state transition control of the priority control unit WREQP. In the state BIC, BI with RP = [0]
C has priority, and in the status SCU, RP = [1] and SCU has priority. The conditions for state transition are as follows.

COND-B = (/ BBSY) * (/ RTY-B) * R
S-B * HACK-B COND-S = (/ RTY-S) * RS-S * HACK
-Do not update priority if SBIC asserts BBSY or if selected element B or S is a retry. Initially, the reset signal RST causes the state BI.
C. Perform COND-B in state BIC (ie B
HACK-B is given to the IC) and the state SCU is entered. If COND-S is performed in the status SCU, the status BIC
Transitions to.

The plural-bus arbitration unit 204 arbitrates between the M bus of the arbitration master CBC (0) and the M bus of the arbitration slave CBC (1) and the W bus, and outputs a hold acknowledge output enable signal for each of them. O
WN-ACKE, FAR-ACKE, W-ACKE are output. The plural-bus arbitration unit 204 can set a plurality of types of operation modes by the work setting and register setting signals. Table 20 shows the relationship between the mode setting input and the operation mode.

[0094]

[Table 20]

-Denotes not to care, ∘ indicates arbitration target, and x indicates non-arbitration target. In the case of "non-interleaved", the processor side expansion chip bus is one of the own system M buses, and there is no other system M bus. Further, in the case of “non-forced relay”, since the processor side (M bus) and the non-processor side (W bus) are individually arbitrated, the multi-bus arbitration unit 204 does not need arbitration. In this case, the HACK output permission signal OWN-ACKE = 1 (fixed) for the local M bus and the HACK output permission signal W-ACK for the W bus
E = 1 (fixed). In the case of "non-interleaved" and "forced relay", the own system M bus and non-processor side W
Arbitrate by integrating with the bus. In this case, the arbitration request input signal FAR-IB from the arbitration slave CBC (1) (however, it does not exist in non-interleave)
[6: 4] is inhibited in the inter-bus arbitration unit 204.

In the case of "interleave", the processor side expansion chip bus includes the own system M bus and the other system M bus. Furthermore, in the case of "non-forced relay", its own system M bus and other system M
Arbitration is performed together with the bus, and arbitration is independently performed for the non-processor side W bus. HA of W bus in this case
The CK output permission signal W-ACKE = 1 (fixed). Along with this, each input RS-B, RS-S, RS-T for the W bus sent from the bus right request arbitration unit WREQA
Bus busy BBSY and retry waiting display input RTY
-B and RTY-S are inhibited inside the plural bus arbitration unit 204. In the case of “interleave” and “forced relay”, the self-system M bus, the other-system M bus and the non-processor side W bus are integrated and arbitrated. Table 21 shows an outline of the priority control of the inter-bus arbitration unit 204.

[0097]

[Table 21]

The TRC of the W bus is always the highest priority. CC
M's EM write back request has priority over TRC. Own CCM
And the other system CCM compete with each other, the bus right is alternately granted to the own system and the other system. The BIC bus busy request has priority over the CCM EM write back request. Retry has priority over the BIC bus busy request. The normal hold request is the lowest.

FIG. 13 shows the state transition when the normal requests conflict with each other. When a plurality of hold requests conflict with each other, first, the M bus and the W bus are equally arbitrated, and further, the own system and the other system of the M bus are evenly arbitrated. State P0 is prioritized in the order of own system M bus → other system M bus → W bus, state P
In 1, the order of other system M bus → own system M bus → W bus, state P2
In the order, W bus → own M bus → other system M bus, and in state P3, W bus → other system M bus → own system M bus. Also F
AR-RQ is a hold request FAR- of another system CCM.
When IB [6: 4] is accepted, OWN-RQ accepts the hold request OWN-IB [6: 4] of own CCM, and WBUS-RQ accepts the hold request HREQB / HREQS of BIC or SCU. It occurs in each case. However, TRC hold request HREQT, CCM EM writeback IBWS [3:
0], BIC bus busy BBSY, and retry RETRY of each element, no state transition is performed. Table 2
2 shows detailed priority control of the inter-bus arbitration unit 204.

[0100]

[Table 22]

Inner bus right permission signal generator (MACKG)
205 outputs a hold acknowledge signal HACOO [3: 0] for CCM [3: 0]. ACKO [n] = act [n] * (idle * hack
-Enb + ACKI [n]), where n = 0 to 3. Also, act [n] indicates that the CCM [n] request has been selected as a result of the arbitration.

Act [n] = RS [n] * HREQ [n] Further, idle indicates a state in which the bus right is released. idle = (/ ACKI [0]) * (/ ACKI
[1]) * (/ ACKI [2]) * (/ ACKI
[3]) * ACKI-W2M * NEGATEI However, ACKI is a feedback input of the hold acknowledge. The hack-enb is a signal in which OWN-ACKE or FAR-ACKE is selected by mode setting. Table 23 shows the truth table.

[0103]

[Table 23]

Further, the inner bus right permission signal generation unit 205 outputs M
→ Output the W relay permission signal ACKO-W2M. ACKO-W2M = act-W2M * (idle + AC
KI-W2M) However, act-W2M indicates that the relay request is selected as a result of the arbitration. act-W2M = RS-W2M * HREQ-W2M The outer bus right permission signal generator (WACKG) 206 is BI.
Hold acknowledge signal ACK of C, SCU, TRC
It outputs OB, ACKO-S, ACKO-T and relay permission signal ACKO-M2W.

ACKO-B = act-B * (idle * hack-e
nb + ACKI-B) ACKO-S = act-S * (idle * hack-e
nb + ACKI-S) ACKO-T = act-T * (idle * hack-e
nb + ACKI-T) ACKO-M2W = act-M2W * (idle + AC
KI-M2W) where idle = (/ ACKI-B) + (/ ACKI-
S) + (/ ACKI-T) + (/ ACKI-M2W) +
(/ NEGATEI) In the case of TRC mode, act-B = 0 act-S = 0 act-T = TRC2SCU * HREQ-T act-M2W = 0 hack-enb = 1 CBC mode, in the case of arbitration master , Act-B = RS-B * HREQ-B act-S = RS-S * HREQ-S act-T = RS-T * HREQ-T act-M2W = RS-M2W * HREQ-M2W hack-enb = W -ACKE CBC mode, in the case of an arbitration slave, act-B = RS-B * HREQ-B act-S = RS-S * HREQ-S act-T = RS-T * HREQ-T act-M2W = HACK -I * HREQ-M2W hack-enb = 0.

Inner bus retry monitoring unit (MRTYG) 2
07 monitors the retry request of the slave element of the M bus, and outputs the retry waiting display flag RTY [3: 0]. This flag indicates the bus master element (CCM0 to CCM3 in this example) for which a retry request is made or the bus master element that asserted the bus lock notification signal MLOC. However, when the CCM asserts IBWS to perform the EM write-back, it always has priority over other hold requests, so the flag is not set when a retry request is made to the EM write-back CCM. On the other hand, when the CCM waiting for retry asserts IBWS and performs EM write back, it is not a retry access and therefore the flag is not reset.

The retry request is recognized according to the specifications of the extended chip bus, and in this example, MDC is asserted when MDC is asserted.
If RETRY is asserted, it means that there is a retry request. MRETRY is not monitored when MDC is negated. When MRETRY and the bus error MBERR are asserted at the same time, the bus error is prioritized, and therefore no retry request is issued. FIG. 14 shows the state transition control of the inner bus retry monitoring unit (MRTYG) 207. Table 2
4 shows the contents of the state of MRTYG.

[0108]

[Table 24]

The conditions for state transition are as follows. SET-0 = DCandRTY * HACK [0] * (/
IB [0]) SET-1 = DCandRTY * HACK [1] * (/
IB [1]) SET-2 = DCandRTY * HACK [2] * (/
IB [2]) SET-3 = DCandRTY * HACK [3] * (/
IB [3]) However, DCandRTY = MDC * MRETRY * (/
MBERR) CLR-0 = HACK [0] * (/ IB [0]) CLR-1 = HACK [1] * (/ IB [1]) CLR-2 = HACK [2] * (/ IB [2]) CLR-3 = HACK [3] * (/ IB [3]) LOC-0 = MLOC * HACK [0] LOC-1 = MLOC * HACK [1] LOC-2 = MLOC * HACK [2] LOC-3 = MLOC * HACK [3] XHACK-0 = / HACK [0] XHACK-1 = / HACK [1] XHACK-2 = / HACK [2] XHACK-3 = / HACK [3] XMLOC = / MLOC Outside bus retry monitoring The unit (WRTYG) 208 monitors the retry request of the slave element of the W bus and outputs the retry waiting display flags RTY-B and RTY-S. This flag displays the bus master element for which a retry request has been made, and detects the completion of retry access and resets it. Even if the TRC acquires the bus right, it does not become the bus master, so there is no retry waiting state of the TRC.
However, when BIC asserts BBSY, it is always SC
Since it has priority over the U hold request, BBSY
The flag is not set when a retry request is made to the asserted BIC. On the other hand, BIC that is waiting for retry is BBS
When Y is asserted for bus access, the flag is not reset because it is not a retry access.

Similarly, the retry request is recognized according to the specifications of the extended chip bus, and in this example, if WRETRY is asserted when WDC is asserted, it is determined that there is a retry request. WRETRY is not monitored during WDC negation. If WRETRY and WBERR are asserted at the same time, the bus error has priority, so no retry request is issued. FIG. 15 shows state transition control of the outer bus retry monitoring unit (WRTYG) 208. Table 2
5 shows the contents of the WRTYG state.

[0111]

[Table 25]

The conditions for state transition are as follows. SET-B = DCandRTY * HACK-B * (/ B
BSY) SET-S = DCandRTY * HACK-S CLR-B = HACK-B * (/ BBSY) CLR-S = HACK-S However, DCandRTY = WDC * WRETRY * (/
WBERR) XHACK-B = / HACK-B XHACK-S = / HACK-S Plural bus arbitration request signal generation unit (ILROG) 209
Is an arbitration request signal OWN- between the M bus arbitration master CBC (0) and the arbitration slave CBC (1) in the case of the interleaved multiprocessor configuration.
Generate IB [6: 4]. The connection between CBC (0) and (1) is shown in FIG. Table 26 shows the contents of the CBC arbitration request signal OWN-IB [6: 4].

[0113]

[Table 26]

FIG. 16 is a timing chart of the relay write operation of the embodiment. The write bus access signal of the relay source is relayed to the relay destination with a delay of two clocks (CLK1).
When the relay destination returns the data complete signal DC, this is relayed to the relay source. The relay source ends the bus access by receiving the DC. The relay destination is relayed until the bus access of the relay source is completed.

FIG. 17 is a timing chart of the relay read operation of the embodiment. The relay source read bus access signal is relayed to the relay destination. The relay destination is the read data D and D
When C is returned, this is relayed to the relay source. DC is the relay source
The bus access is ended by reception. The relay destination is relayed until the bus access of the relay source is completed. FIG. 18 is a timing chart of the non-relay write operation of the embodiment. The closed write bus access on the bus operation side is completed in 3 clocks. However, in the case of forced relay designation, this is relayed to the non-operating side.

FIG. 19 is a timing chart of the non-relay read operation of the embodiment. The closed read bus access on the bus operation side is completed in 3 clocks. However, in the case of forced relay designation, this is relayed to the non-operating side. FIG. 20 is a timing chart of the bus snoop operation (without forced relay contention) according to the embodiment. The closed block write bus access of the relay source (W bus) is completed in 6 clocks. This is relayed to the relay destination (M bus) with a delay of 2 clocks.

FIG. 21 is a timing chart of the bus snoop operation (non-forced relay conflict avoidance) of the embodiment. Memory write access relay destination (M bus) of the relay source (W bus)
There is a conflict between relay (bus snoop operation) to the bus) and closed access (no relay) at the relay destination (M bus).
In this case, hold the contents of the W bus address cycle,
Wait for the end of M bus access. After the access to the M bus is completed, the contents held in the W bus are output to the M bus for one cycle, DC is asserted, and the relay operation is completed.

FIG. 22 simultaneously processes the closed access of the outer bus and the closed access of the inner bus of the embodiment (progress).
It is a timing chart when doing. There is no conflict between the inner bus and the outer bus, and each performs arbitrarily closed read / write access. FIG. 23 is a timing chart when the closed access of the outer bus and the relay from the inner side to the outer side compete with each other. In this case, the contents of the address cycle of the M bus are retained and the completion of the W bus access is waited for.
After the access to the W bus is completed, the contents held in the M bus are output to the W bus for one cycle, and the transition from the next cycle to the relay operation is performed.

FIG. 24 is a timing chart in the case where the relay from inside to outside and the relay from inside to outside compete with each other, the relay device terminates the inside access, and relays from outside to inside. In this case W
The contents of the address cycle of the bus are held, and the CBC autonomously asserts RETRY to the bus master of the M bus to terminate the access. After the access to the M bus is completed, the content held in the W bus is output to the M bus for one cycle, and the transition from the next cycle to the relay operation is performed.

In the above embodiment, the bus repeater (CBC) which integrally includes the bus arbiter (bus arbiter) and the remaining part of the bus repeater has been described, but the present invention is not limited to this. The bus arbiter and the rest of the bus repeater may be configured as separate LSI chips. Further, it is obvious that the LSI chip may be constructed by taking out the respective characteristic portions as claimed in the present application from the portion of the bus arbiter or the rest of the bus repeater.

In the above embodiment, an example of application to the double collation processor system is shown, but the present invention is not limited to this. The bus repeater (CBC) of the embodiment is also applicable to a duplex system having a duplex processor operating as a working processor / spare processor. Although the preferred embodiments of the present invention have been described above, it goes without saying that various changes in configuration, control and combination can be made without departing from the spirit of the present invention.

[0122]

As described above, according to the present invention (1),
Since it has three stages of reception holding, relay judgment, and transmission control,
Even if bus → and bus → bus access conflicts, these can be processed effectively. Therefore, the common bus resources of the system can be effectively utilized.

Further, according to the present invention (13), the bus repeater designated for one-way relay stops the relay operation when the external duplexing verifying device detects the mismatching of the matching, so that the adverse effect caused in the system is minimized. Can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of an example in which the bus repeater of the embodiment is applied to a single processor system.

FIG. 3 is a diagram showing details of connection in a single processor configuration of the CBC of the embodiment.

FIG. 4 is a block diagram of an example in which the bus repeater of the embodiment is applied to an interleaved multiprocessor system.

FIG. 5 is a diagram showing details of connections in the interleaved multiprocessor configuration of the CBC of the embodiment.

FIG. 6 is a functional block diagram of a bus repeater according to an embodiment.

FIG. 7 is a diagram illustrating an address space of a bus slave according to the embodiment.

FIG. 8 is a block diagram of a hardware configuration of a bus repeater according to an embodiment.

FIG. 9 is a block diagram of a bus arbiter according to an embodiment.

FIG. 10 is a diagram showing state transition control of a priority control unit IBWSP.

FIG. 11 is a diagram showing state transition control of a priority control unit MREQP.

FIG. 12 is a diagram showing state transition control of a priority control unit WREQP.

FIG. 13 is a diagram showing state transition control of an inter-bus arbitration unit ILEVA.

FIG. 14 is an inside bus retry monitoring unit MRTYG.
It is a figure which shows the state transition control of.

FIG. 15 is an outside bus retry monitoring unit WRTYG.
It is a figure which shows the state transition control of.

FIG. 16 is a timing chart of the relay write operation of the embodiment.

FIG. 17 is a timing chart of the relay read operation of the embodiment.

FIG. 18 is a timing chart of a non-relay write operation of the embodiment.

FIG. 19 is a timing chart of a non-relay read operation according to the embodiment.

FIG. 20 is a timing chart of the bus snoop operation (without forced relay contention) of the embodiment.

FIG. 21 is a timing chart of the bus snoop operation (non-forced relay conflict avoidance) according to the embodiment.

FIG. 22 is a timing chart when the closed access of the outer bus and the closed access of the inner bus of the embodiment are simultaneously processed.

FIG. 23 is a timing chart when the closed access of the outer bus and the relay from the inner side to the outer side compete with each other.

FIG. 24 is a timing chart in the case where an outside → inside relay and an inside → outside relay compete with each other, the relay device terminates the inside access, and the outside → inside relay is performed.

[Explanation of symbols]

 MPU Microprocessor Unit CCM Cache Controller / Memory MAC Memory Controller MEM Memory CBC Bus Repeater BIC System Bus Interface SCU System Controller MBC Maintenance Bus Controller TRC Bus Tracer TRM Trace Memory MAT Double Matching Unit, M Bus W Bus S Bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Niwa 3-28-1, Joto, Oyama-shi, Tochigi Prefecture Fujitsu Digital Technology Limited (72) Inventor Kazuo Nagahori 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Incorporated (72) Inventor Yasuhiro Ishikawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Eiji Ishikawa 1-1-6, Uchiyuki-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (13)

[Claims] 1. A system in which a processor-side bus connected to one or more bus access elements and a non-processor-side bus connected to another one or more bus access elements are mutually connected via a bus repeater. In the above bus repeater, a reception holding unit for sampling and holding bus access signals of a processor side bus and a non-processor side bus, a relay control unit for judging necessity of relay based on a signal held by the reception holding unit, and a relay control And a transmission control unit that outputs an internal hold signal to a relay destination bus according to a determination output of the unit. 2. The sampling hold signal is sequentially shifted and transferred by clock signals having different phases, and in parallel with this, the necessity of relay is determined and the output control of the relay destination transmission control unit is performed. Item 1. Bus repeater. 3. The bus repeater according to claim 1, wherein the relay control unit does not relay a closed bus access signal of the processor side bus or the non-processor side bus. 4. The bus repeater according to claim 3, wherein the relay control unit relays a closed bus access signal of the processor-side bus to the non-processor-side bus by setting forced relay. 5. The bus repeater according to claim 3, wherein the relay control unit relays a closed memory write access signal of the non-processor side bus to the processor side bus by setting. 6. The relay control unit holds the relay output when the closed bus access of the processor side bus or the non-processor side bus conflicts with the relay output to the processor side bus or the non-processor side bus. 4. The bus repeater according to claim 3, wherein the bus repeater shifts to a relay output operation after completion of the closed bus access. 7. The relay control unit holds the relay output to the processor side bus or the non-processor side bus when the relay outputs to the processor side bus and the non-processor side bus compete with each other, and holds the processor side bus or the non-processor side bus. While asserting the retry signal to the bus master of the processor side bus,
4. The bus repeater according to claim 3, wherein the bus repeater shifts to a relay output operation after completion of bus access of the processor side bus or the non-processor side bus. 8. The relay control unit is connected to an external bus arbiter for arbitrating bus right request signals of the processor-side bus and the non-processor-side bus, and the relay control unit relays request to the processor-side bus and the non-processor-side bus 2. The bus repeater according to claim 1, wherein the signal is output to the bus arbitrator, and the relay output operation is performed according to the relay permission signal from the bus arbitrator. 9. The bus repeater according to claim 8, wherein the function of the bus arbitrator and the function of the bus repeater are integrally provided. 10. The bus repeater according to claim 1, wherein a signal output to one side bus is blocked by setting. 11. The bus repeater according to claim 4, wherein forced relay can be set for each bus access element connected to the processor side bus. 12. The bus repeater according to claim 1, wherein the relay controller has a function of changing a level of a predetermined relay output signal according to a setting and outputting the signal. 13. A duplex system in which a processor side bus to which one or more bus access elements are connected, a non-processor side bus to which another one or two or more bus access elements are connected, and a plurality of other bus access elements are connected. In a bus relay system of a duplex system in which a processor-side bus is connected in series via first and second bus relays, a first bus relay that connects a processor-side bus and a non-processor-side bus, and a duplexer A second bus repeater that connects the processor-side bus and the non-processor-side bus and blocks the signal output to the non-processor-side bus; and the second bus repeater has an external duplication checker on the processor side. A bus relay method characterized by stopping relay operation upon detection of a mismatch between the bus and the bus on the duplex processor side.