JPH08328966A - Non-volatile memory protector - Google Patents

Abstract

PURPOSE: To prevent erroneous write to an EEPROM by insulating the EEPROM and an interface means by cutting off a path for supplying power to the interface means when a voltage drop or supply stop is detected. CONSTITUTION: When a voltage supplied through a power supply terminal 7a of a power unit 2a is lowered rather than the operation guarantee voltage of a microprocessor unit 1 or power supply is stopped, the power supply voltage of a cable I/F power supply control circuit 16 is lowered rather than a threshold value and a relay 14 is turned to an OFF state. Thus, the power supply terminal 7a of the power unit 2a and a cable I/F power supply terminal 17 are disconnected and the supply of power to be turned from a microprocessor unit 13 through a cable I/F (interface means) 8a into the microprocessor unit 1 is prevented. Thus, the erroneous write to a non-volatile memory caused by the power supply round from an external device can be prevented at the microprocessor unit in a power source off state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor which is connected to another microprocessor unit or the like and is in a power-off state, via a cable from another microprocessor unit which is in a power-on state due to different power supply paths. The present invention relates to a non-volatile memory protection device that prevents erroneous writing to a non-volatile memory due to power supply of the above.

[0002]

2. Description of the Related Art FIG. 5 shows, for example, JP-A-63-221446.
FIG. 4 is a block diagram showing a configuration of a conventional non-volatile memory protection device disclosed in Japanese Patent Publication No. JP-A-2004-242242, in which 4 is a microprocessor (hereinafter abbreviated as CPU), 6 is a non-volatile memory (hereinafter abbreviated as EEPROM), 9 is an address bus connecting the CPU 4 and the EEPROM 6, 30 is a CP
A controller 31 that outputs a valid command when it receives a predetermined command sequence from U4, and 31 is a power supply protection circuit.

Such a conventional non-volatile memory protection device is
To protect the memory contents of the EEPROM 6, the EEPROM is used when the power supply in the microprocessor unit is turned on / off.
6 is provided with a power supply protection circuit 31 for preventing erroneous writing to data.

Next, the operation will be described. When the power supply in the microprocessor unit is turned on / off, a power supply reset signal (an inverted signal of RST) transmitted from a power supply device (not shown) and a memory save signal (SAV) from the CPU 4 (SAV
The power supply protection circuit 31 is configured to generate a protection signal (inverted signal of NVSAVE) by NAND output with the inverted signal of E *). The power supply protection circuit 31 normally applies a voltage (NVPWR) to the EEPROM 6. It is derived from the power supply + V. When powering down the power supply,
The power supply protection circuit 31 automatically applies a protection signal (inversion signal of NVSAVE) to the EEPROM 6 to prevent erroneous writing in the EEPROM 6 due to noise.

Another conventional non-volatile memory protection device is disclosed in Japanese Patent Application Laid-Open No. 4-274539, which is used when a CPU in a microprocessor unit runs out of control.
Some include an erroneous write prevention circuit for EPROM.

In such a conventional non-volatile memory protection device, an erroneous write prevention circuit using a logic IC specifies a predetermined address when the CPU in the microprocessor unit writes to the EEPROM and the data corresponding to the predetermined address has a predetermined value. At the same time, the EEPROM is controlled to the write enable state only when the write request signal is output. As a result, the CPU in the write enable state
EEPRO only when the write request signal is output from
Permission to write to M, EEPR when CPU runs out
Prevents erroneous writing to OM.

[0007]

Since the conventional non-volatile memory protection device is configured as described above, as shown in FIG. 6, two non-volatile memory protection devices connected by a cable via a communication interface (for example, RS422 interface) are connected. In the microprocessor unit, when the microprocessor unit B13 and the power supply device B2b are turned on and the other microprocessor unit A1 and the power supply device A2a are turned off, the power supply terminal 7b → the resistor R1B →
Cable 11 → resistor R1A → power supply terminal 7a → CPU
4 etc. → GND terminal 10a → resistor R2A → cable 11 →
Power is supplied to the printed circuit board A3a of the microprocessor unit A1 via the resistor R2B → GND terminal 10b, and the CPU 4, the peripheral circuit 5, the EEPROM 6, and the IC of the write protection circuit 12 using the IC become the operable voltage, and the write protection circuit. There is a problem that the memory 12 of the EEPROM 12 malfunctions and rewrites the memory contents of the EEPROM 6.

The present invention has been made to solve the above problems, and in a microprocessor in a power-off state, which is connected to another microprocessor unit or the like via a communication interface, a power supply path is provided. Another object of the present invention is to provide a non-volatile memory protection device capable of preventing erroneous writing to the non-volatile memory due to power supply from another microprocessor unit in a power-on state via a cable.

[0009]

According to a first aspect of the present invention, there is provided a nonvolatile memory protection device, which is a power supply monitoring means for detecting that the voltage of the power supply supplied from the power supply means has dropped or the power supply has stopped. And a path disconnecting means for disconnecting a path for supplying power from the power supply means to the interface means when the power supply monitoring means detects a voltage drop or a supply stop and insulating a power supply line between the EEPROM and the interface means. Is.

In the non-volatile memory protection device according to the second aspect of the present invention, the path disconnecting means is turned off when the current flowing through the Zener diode connected to the output terminal of the power supply means is cut by the decrease of the power supply voltage. It includes a relay for disconnecting.

In the non-volatile memory protection device according to the third aspect of the present invention, the power supply means includes a power supply monitoring means configured to output a predetermined signal when the decrease in the power supply voltage is detected, and the path disconnecting means. Includes a relay that turns off when a predetermined signal is received and disconnects the path.

According to another aspect of the non-volatile memory protection device of the present invention, the power supply monitoring means includes means for outputting a predetermined signal when the decrease in the power supply voltage is detected, and the path disconnecting means receives the predetermined signal. It includes a relay that is turned off and disconnects the route.

According to a fifth aspect of the present invention, there is provided a non-volatile memory protection device, comprising a power supply monitoring means for detecting that the voltage of the power supply supplied from the power supply means has dropped or the power supply has stopped, and the power supply monitoring means. Stop means for stopping access to the EEPROM when a voltage drop or supply stop is detected,
After the stop processing of the stop means, the power supply means EEPRO
It is provided with a path cutting means for cutting the path for supplying power to M to insulate the power supply line between the EEPROM and the interface means.

In the non-volatile memory protection device according to the invention of claim 6, the power supply means includes a power supply monitoring means configured to output a predetermined signal in response to a decrease or stop of supply of the power supply voltage, The stopping means includes means for stopping access to the EEPROM when receiving a predetermined signal and outputting another predetermined signal, and the route disconnecting means is turned off when receiving another predetermined signal and disconnects the route. Is included.

[0015]

In the nonvolatile memory protection device according to the present invention, when the power supply monitoring means detects a voltage drop or supply stop, the path disconnecting means disconnects the path for supplying power from the power supply means to the interface means, and the EEPROM. And the interface means. As a result, it is possible to prevent erroneous writing to the EEPROM due to sneak power supply from an external device via the interface means. That is, since it is possible to cut off the excessive power supply from the external device that goes around via the interface means, the built-in EEPROM can be operated at the normal voltage only when the power supply means of the microprocessor unit is in the ON state. .

In the non-volatile memory protection device according to the second aspect of the invention, the relay of the path disconnecting means is turned off when the current flowing through the Zener diode is cut due to the decrease of the power supply voltage, and disconnects the path. As a result, it is possible to prevent the extra power supply from the external device that goes around via the interface means and prevent the erroneous writing to the EEPROM.

In the non-volatile memory protection device according to the third aspect of the present invention, when the relay of the path disconnecting means receives a predetermined signal from the power supply monitoring means included in the power supply means, it turns off and disconnects the path. As a result, it is possible to prevent the extra power supply from the external device that goes around via the interface means and prevent the erroneous writing to the EEPROM.

In the nonvolatile memory protection device according to the fourth aspect of the present invention, when the relay of the path disconnecting means receives the predetermined signal from the power supply monitoring means, it is turned off and disconnects the path. This cuts off the extra power supply from the external device that goes around via the interface means, and the EEPR
Accidental writing to the OM can be prevented.

In the non-volatile memory protection device according to the fifth aspect of the present invention, when the power supply monitoring means detects the voltage drop or the supply stop, the stop means stops the access to the EEPROM,
After the stop processing of the stopping means, the path disconnecting means disconnects the path for supplying the power from the power supply means to the EEPROM to EEP.
Insulate the ROM from the interface means. In this way, by stopping the power supply to the EEPROM, the EEP
Accidental writing to the ROM can be prohibited.

In the nonvolatile memory protection device according to the invention of claim 6, when the stopping means receives the predetermined signal from the power supply monitoring means, it stops the access to the EEPROM and outputs another predetermined signal, and the path disconnecting means. When the relay receives another predetermined signal, it turns off and disconnects the path.
In this way, the relay is turned on / off by the command from the stopping means.
EEP is turned off by cutting off the power supply path to the EEPROM.
By stopping the supply of the ROM power, it is possible to prevent erroneous writing to the EEPROM.

[0021]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a nonvolatile memory protection device according to an embodiment of the present invention.
1 is a microprocessor unit A, 2a is a power supply device A (power supply means) of the microprocessor unit A1,
3a is a printed circuit board on which main constituent elements of the microprocessor unit A1 are provided, 4 is a CPU (stopping means),
5 is a peripheral circuit including an address decoder circuit, 6 is an EEP
ROM (nonvolatile memory), 7a is a power supply terminal of the power supply device A2a, 8a is a cable I / F A (interface means) of the microprocessor unit A1, 9 is an address / data bus of the microprocessor unit A1, and 10a is a microprocessor. GND of unit A1
Terminals, 14 is a relay (path disconnecting means), 15 is a Zener diode (power supply monitoring means), 16 is a cable I / F power supply control circuit, 17 is a cable I / F power supply control circuit 16 cable I / F power supply A terminal, 13 is a microprocessor unit B, 3b is a printed circuit board of the microprocessor unit B13, 8b is a cable I / FB of the microprocessor unit B13, 7b is a power supply terminal for supplying power to the cable I / F B8b, etc. ,
10b is a GND terminal of the microprocessor unit B13.

Next, the operation will be described. The microprocessor unit A1 has a power supply terminal 7 of the power supply device A2a.
Power is supplied to the CPU 4, the peripheral circuit 5 and the EEPROM 6 provided on the printed circuit board 3a via a. Power is supplied to the cable I / F A8a on the printed circuit board 3a through the cable I / F power supply terminal 17 of the cable I / F power supply control circuit 16 including the relay 14 and the Zener diode 15. As a result, the I / F between the microprocessor unit A1 and the microprocessor unit B13 is realized.

When the voltage of the power supply supplied via the power supply terminal 7a of the power supply device A2a becomes lower than the operation guarantee voltage of the microprocessor unit A1 or the supplied power is stopped, the cable I / F power supply is supplied. Similarly, the power supply voltage supplied to the supply control circuit 16 also decreases. Since the voltage across the Zener diode 15 provided on the GND side of the cable I / F power supply control circuit 16 is always kept constant, when the power supply voltage of the cable I / F power supply control circuit 16 falls below a certain threshold value. , Relay 1
The input side current If of No. 4 is cut and the relay 14 is turned off. As a result, the power supply terminal 7 of the power supply device A2a
a and the cable I / F power supply terminal 17 are disconnected, and the power is supplied from the power supply terminal 7b of the microprocessor unit B13, and the power supply terminal 7b → the cable I / F B8
b → cable 11 → cable I / F A8a → cable I / F It is possible to prevent power supply from flowing into the microprocessor unit A1 via the power supply terminal 17. Therefore, the power supply voltage supplied through the power supply terminal 7a of the power supply device A2a is the microprocessor unit A.
Even if the voltage becomes lower than the operation guarantee voltage of 1, the power is not supplied to the EEPROM 6.

As described above, according to this embodiment,
The power is cut off by the cable I / F power supply control circuit 16 that monitors the voltage using the Zener diode 15, so that the I by the sneak power supply voltage from different units is supplied.
It is possible to prevent erroneous writing to the EEPROM 6 due to C malfunction.

Example 2. FIG. 2 is a block diagram showing the configuration of a nonvolatile memory protection device according to another embodiment of the present invention. In the figure, the same parts as those shown in FIG. Omit it. Further, in the figure, reference numeral 18 denotes a power supply stop signal supplied from the power supply device A2a to the relay 14 in the cable I / F power supply control circuit 16.

Next, the operation will be described. Power supply A2
The power supply stop signal 18 is input to the cable I / F power supply control circuit 16 from a. When power is supplied through the power supply terminal 7a of the power supply device A2a, an insignificant signal of the power supply stop signal 18 is input to the cable I / F power supply control circuit 16 to turn on the relay 14 and turn on the power supply device. The power supply terminal 7a of A2a and the cable I / F power supply terminal 17 are connected, and as a result, the power is supplied to the cable I / F.
It is supplied to the cable power supply terminal 17 for A8a.

On the other hand, the power supply terminal 7a of the power supply A2a
Power supply stop signal 1 when the power supply via the
The significant signal 8 is input to the cable I / F power supply control circuit 16 to turn off the relay 14 and disconnect the power supply terminal 7a of the power supply device A2a from the cable I / F power supply terminal 17. As a result, the power is supplied from the power supply terminal 7b of the microprocessor unit B13, and the power supply terminal 7b → the cable I / FB 8b → the cable 11 → the cable I / F A8a → the cable I / F via the power supply terminal 17 is fed into the microprocessor unit A1. It is possible to prevent the sneak-in power supply from reaching.

Therefore, according to this embodiment, the power supply unit A
The power supply stop signal 18 from 2a is input to the cable I / F power supply control circuit 16 to turn on / off the power supply to the cable I / F A8a to cut off the power supply, thereby sneaking in the power supply voltage from different units. I by supply
C It is possible to prevent erroneous writing of the EEPROM 6 which is erroneous.

Example 3. FIG. 3 is a block diagram showing the configuration of a nonvolatile memory protection device according to another embodiment of the present invention. In the figure, the same components as those shown in FIG. Omit it. Further, in the figure, 19 is a power supply monitoring circuit (power supply monitoring means) which monitors the power supply voltage of the power supply device A2a and outputs a low voltage signal 20 to the relay 14 when the power supply voltage drops.

Next, the operation will be described. The power supply monitoring circuit 19 provided on the printed circuit board 3a detects the low voltage signal 2
0 is input to the cable I / F power supply control circuit 16.
When the low voltage signal 20 is a significant signal, the relay 14 is turned off to disconnect the power supply terminal 7a of the power supply device A2a and the cable I / F power supply terminal 17 from the power supply terminal 7b of the microprocessor unit B13. Power supply terminal 7b → Cable I / F B8b → Cable 11 → Cable I / F A8a → Cable I / F Via power supply terminal 17 Microprocessor unit A1
It is possible to prevent the power supply from going inward.

As described above, according to this embodiment, by providing the power supply monitoring circuit 19 on the printed board 3a,
The low voltage signal 20 is supplied to the cable I / F power supply control circuit 16
To turn on / off the power supply to the cable I / F A8a to cut off the power supply, and thereby the EEPRO of the IC malfunction due to the sneak power supply voltage supply from different units
It is possible to prohibit erroneous writing to M6.

Example 4. FIG. 4 is a block diagram showing a configuration of a nonvolatile memory protection device according to another embodiment of the present invention. In the figure, the same components as those shown in FIG. Omit it. Further, in the figure, 22 is an EEPROM power supply control circuit for controlling power supply to the EEPROM 6, 23 is an EEPROM power supply terminal of the EEPROM power supply control circuit 22, and 24 is
Is an EEPROM power supply stop signal for controlling the relay 14 of the EEPROM power supply control circuit 22 and 25 is a power supply stop advance signal transmitted from the power supply device A2a. The stopping means is realized as one function of the CPU 4.

Next, the operation will be described. Power supply A2
When the power supply stop notification signal 25 is input to the CPU 4 from a, the CPU 4 supplies the power supply terminal 23 for supplying power to the EEPROM 6 and the power supply terminal for supplying power to the CPU 4, the peripheral circuit 5 and the cable I / F A 8a. In order to disconnect 7a, the EEPROM power supply stop signal 24 is set to E
Input to the EPROM power supply control circuit 22.

When the power supply stop notice signal 25 from the power supply A2a is an insignificant signal, the CPU 4 outputs the ineffective signal of the EEPROM power supply stop signal 24 to the EEPROM power supply control circuit 22. In this case, the relay 14 of the EEPROM power supply control circuit 22 is controlled to the ON state, and the power supply terminal 7a and the EEPROM power supply terminal 23 are controlled.
Are connected to each other to supply power to the EEPROM 6.

On the other hand, when the power supply stop notice signal 25 from the power supply device A2a is a significant signal, the CPU 4 causes the EEPROM to
6 is stopped and the significant signal of the EEPROM power supply stop signal 24 is set to the EEPROM power supply control circuit 22.
Output to EEPROM power supply control circuit 22
The relay 14 of the EEPROM power supply stop signal 2
The power supply terminal 7a is turned off by receiving the significant signal of 4
And the EEPROM power supply terminal 23 are disconnected. In this way, the power supply stop notice signal 25 from the power supply device A2a
When a significant signal of is input to CPU4, CPU4
EPROM access stop processing is performed, and then EEPRO
By outputting the M power supply stop signal 24 to the EEPROM power supply control circuit 22 and disconnecting the EEPROM power supply terminal 23 from the power supply terminal 7a, the power supply to the CPU 4, the peripheral circuit 5, and the cable I / F A8a is stopped. Then, the power is supplied from the power supply terminal 7b of the microprocessor unit B13 via the cable I / F A8a, and the power supply terminal 7b → the cable I / F B8b → the cable 1
1 → cable I / F A8a → the supply of power to the inside of the microprocessor unit A1 via the power supply terminal 7a can be prevented.

Therefore, according to this embodiment, the EE of the malfunction of the IC due to the sneak-in power supply voltage supply from the different type unit
Incorrect writing to the PROM 6 can be prohibited.

[0037]

As described above, according to the first aspect of the invention, the power supply monitoring means for detecting that the voltage of the power supply supplied from the power supply means has dropped or the power supply has stopped, and the power supply monitoring means. When the means detects the voltage drop or the supply stop, the path for supplying power from the power supply means to the interface means is cut off, and the path cutting means for insulating the power supply line between the EEPROM and the interface means is provided. There is an effect that it is possible to prevent erroneous writing to the EEPROM due to sneak power supply from an external device through the interface means.

According to the second aspect of the present invention, the path disconnecting means is a relay that disconnects the path when the current flowing through the Zener diode connected to the output terminal of the power supply means is cut off due to the decrease of the power supply voltage. Since it is configured to include it, there is an effect that a simple circuit is used and an unnecessary power supply from an external device that goes around via the interface means is cut to prevent erroneous writing to the EEPROM.

According to the third aspect of the invention, the power supply means includes a power supply monitoring means configured to output a predetermined signal when detecting a decrease in the power supply voltage, and the path disconnecting means outputs the predetermined signal. Since the relay is configured to include the relay that is turned off when receiving the signal and cuts off the path, it is possible to prevent an erroneous writing to the EEPROM by cutting an extra power supply from an external device that goes around via the interface means.

According to the fourth aspect of the present invention, the power supply monitoring means includes means for outputting a predetermined signal when detecting a decrease in the power supply voltage, and the path disconnecting means turns off when the predetermined signal is received. Since it is configured to include the disconnecting relay, there is an effect that an extra power supply from an external device that wraps around via the interface means can be cut to prevent erroneous writing to the EEPROM.

According to the fifth aspect of the present invention, the power supply monitoring means for detecting that the voltage of the power supply supplied from the power supply means has dropped or the power supply has stopped, and the power supply monitoring means has dropped or stopped the supply of voltage. And a path for insulating the power supply line between the EEPROM and the interface means by cutting off the path for supplying power from the power supply means to the EEPROM after the stop processing of the stop means. Since the disconnection means is provided, there is an effect that erroneous writing to the EEPROM can be prohibited by stopping the power supply to the EEPROM.

According to the invention of claim 6, the power supply means includes a power supply monitoring means configured to output a predetermined signal in response to a decrease in the power supply voltage or a supply stop, and the stop means is a predetermined one. When a signal is received, it includes means for stopping access to the EEPROM and outputting another predetermined signal, and the path disconnecting means includes a relay for turning off the path when receiving another predetermined signal and disconnecting the path. Therefore, there is an effect that erroneous writing to the EEPROM can be prohibited.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile memory protection device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a nonvolatile memory protection device according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a nonvolatile memory protection device according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a nonvolatile memory protection device according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional nonvolatile memory protection device.

FIG. 6 is a block diagram showing the sneak of power in a microprocessor unit including a conventional nonvolatile memory protection device, which is connected to another microprocessor unit via a communication cable.

[Explanation of symbols]

2a Power supply device A (power supply means), 4 CPU (stop means), 6 EEPROM (nonvolatile memory), 8a
Cable I / F A (interface means), 14
Relay (path disconnecting means), 15 Zener diode (power supply monitoring means), 19 Power supply monitoring circuit (power supply monitoring means).

Claims (6)

[Claims] 1. An interface means for connecting to an external device via a cable, a power supply means for supplying power to at least the nonvolatile memory and the interface means, and a voltage of a power supply supplied from the power supply means is lowered. Power supply monitoring means for detecting that the power supply is stopped or the power supply monitoring means detects a voltage drop or supply stop and disconnects a path for supplying power from the power supply means to the interface means. A non-volatile memory protection device comprising: a path disconnecting means for insulating a power supply line between the interface means. 2. The power supply monitoring means includes a zener diode connected to an output terminal of the power supply means, and the path disconnecting means cuts off a current flowing through the zener diode due to a decrease in the power supply voltage. The nonvolatile memory protection device according to claim 1, further comprising a relay that is turned off and disconnects the path. 3. The power supply means includes the power supply monitoring means configured to output a predetermined signal when the decrease in the power supply voltage is detected, and the path disconnecting means receives the predetermined signal. The nonvolatile memory protection device according to claim 1, further comprising a relay that is turned off and disconnects the path. 4. The power supply monitoring means includes means for outputting a predetermined signal when detecting a decrease in the power supply voltage,
2. The non-volatile memory protection device according to claim 1, wherein the path disconnecting means includes a relay that is turned off when the predetermined signal is received and disconnects the path. 5. An interface means for connecting to an external device via a cable, a power supply means for supplying power to at least the non-volatile memory and the interface means, and a voltage of a power supply supplied from the power supply means is lowered. Alternatively, power supply monitoring means for detecting that power supply is stopped, stop means for stopping access to the non-volatile memory when the power supply monitoring means detects a voltage drop or supply stop, and stop processing of the stop means. A non-volatile memory protection device further comprising: a path disconnecting unit that disconnects a path for supplying power from the power supply unit to the nonvolatile memory to insulate a power supply line between the nonvolatile memory and the interface unit. 6. The power supply means includes the power supply monitoring means configured to output a predetermined signal in response to a drop or stop of supply of the power supply voltage, and the stop means outputs the predetermined signal. When it receives, it includes means for stopping access to the non-volatile memory and outputting another predetermined signal, and the path disconnecting means turns off when receiving the other predetermined signal, and relays for disconnecting the path. The non-volatile memory protection device according to claim 5, further comprising: