JPH08328689A - Time information distribution method and reference time circuit - Google Patents

Abstract

PURPOSE: To match display time of a reference clock circuit and all of lock circuits by sending a specific time as a time start time of a clock circuit to the time circuit so as to distribute simultaneously a start signal to a timer to all the clock circuits. CONSTITUTION: Let a processing start time be A, a time start time be C, a distribution required time be B, and when the time A comes, a control adder means 40 sets the distribution required time B to a start means 60 to start time count. Furthermore, the control adder means 40 sets information to designate a clock circuit for time matching to a selection means 70. Moreover, the control adder means 40 reads the processing start time A from a time count means 50 and the distribution required time B is added to the time A and the resulting time is set to a clock circuit 30. When the distribution required time B elapses, a start signal is generated from the start means 60, the signal is distributed to a clock circuit designated by the selection means 70 via a start signal line. Thus, the start signal distributed via the start signal line 12 starts the time of the clock circuit 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a time of day
The present invention relates to a time information distribution method for distributing time information used as a clock (hereinafter abbreviated as TOD). In the field of transaction of banks and securities companies, accurate transaction time is required to perform trading processing starting from the transaction time, and accurate measurement time is required together with various data measured in the field of measurement processing. It is necessary to start and stop the line exactly at a predetermined time.

In the information processing system, since it is necessary to consistently grasp the processing time and the elapsed time in this way, a time circuit is provided for each software access unit (for example, a computer), and the date and time are provided in the software. Information is provided. However, if multiple computers are installed, such as in a computing center, setting the time individually will cause a large difference in the time displayed between the computers, and the time setting work will require a great deal of effort. become.

Therefore, a reference time circuit for clocking a reference time and a time circuit are connected, and the time is adjusted at an appropriate time (for example, when the power is turned on or when a work is started) (that is, the reference time is obtained from the reference time circuit). It is necessary to distribute and set in the time circuit).

[0004]

2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example, which will be described with reference to this figure. In the following description, the same parts or corresponding parts are designated by the same reference numerals. In FIG. 3, 11 connects the reference time circuit and the time circuit,
Reference numeral 51 denotes a clock pulse line for transmitting a clock pulse from the reference time circuit to the time circuit. Reference numeral 51 denotes an oscillator (in the reference time circuit) connected to the timer by the clock pulse line 11 and oscillating at a constant frequency ( In the reference time circuit, 52 is connected to the OSC 51 via the clock pulse line 11 and is connected to the processor and the time circuit via the data bus. Reference numeral 41 denotes a timer that divides an oscillating frequency and clocks a reference time. 41 is a reference time circuit, is connected to a timer 52 via a data bus, and controls the reference time circuit.
Reference numeral 21 denotes a processor (hereinafter, abbreviated as CPU) which reads a processing start time from the timer 52 and adds a distribution required time to set the timer in the time circuit. Reference numeral 21 denotes a data bus in the reference time circuit. , 20 are OSC51,
CPU 41 and timer 52 connected to data bus 21
And a reference time circuit which is composed of a start circuit 61 and a selection circuit 71 in addition to the data bus 21, the clock pulse line 11, and the time signal line 12 and is connected to the time circuit 30. Is in the time circuit, and is connected to the reference time circuit 20 via the data bus 21 and the clock pulse line 11.
Is a timer which is connected to the time circuit and has a different address for each time circuit, and which can be written from the CPU 41. The time circuit 30 is composed of a timer 81 and displays the time.

Further, the processing start time is read from the timer 52, and the time required for distribution is the time until the data indicating the clock start time is set in the last time circuit. In the conventional time information distribution method, the CPU 41 reads the processing start time from the timer 52, adds the distribution required time to the processing start time to generate the clock start time, and outputs the data indicating the clock start time to the data bus. The address which specifies the writing destination of the data on the data bus is sequentially switched for each time circuit, and the data indicating the clock start time on the data bus 21 is set in the time circuit.

[0006]

Therefore, although the data indicating the clock start time is common to all the time circuits, the time indicated by each time circuit is different because the time to start the clock is different for each time circuit. However, there is a problem that the difference increases as the number of time circuits increases. In order to solve this problem, if the clock pulse is suppressed until data indicating the clock start time is set in all the clock circuits, there is a problem that even the clock circuits that are in operation and that do not require time adjustment cannot be used. there were.

According to the present invention, when time adjustment is performed on a plurality of time circuits, only the necessary time circuits are adjusted without affecting the time circuits that do not require time adjustment, and the time adjustment is performed between the reference time circuit and the time circuit. An object of the present invention is to provide a time information distribution method that does not cause a difference in displayed time.

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, reference numeral 12 is a start signal line that connects the reference time circuit and the time circuit and transmits a start signal from the reference time circuit to the time circuit, and 21 is in the reference time circuit connected to the inside of the time circuit. Data bus, 50
Is a clock means in the reference time circuit, which is connected to the control addition means, the activation means, the selection means and the time circuit via the data bus 21 and which clocks the reference time and generates a clock pulse. Yes, 60 is in the reference time circuit and is connected to the control and addition means, the clocking means 50, the selection means and the time circuit via the data bus 21, and is also directly connected to the selection means for distribution. 70 is a starting means for setting a required time and generating a start signal after the distribution required time elapses.
In the reference time circuit, is connected to the control addition means, the clocking means 50, the activation means 60 and the time circuit via the data bus 21, and is also directly connected to the activation means 60 and the activation signal line. 40 is a selection unit that is connected to the time circuit via 12 and selects the time circuit to which the start signal is distributed.
Is connected to the clock means 50, the activation means 60, the selection means 70, and the time circuit in the reference time circuit via the data bus 21, controls the reference time circuit, and processes from the clock means 50. Control addition means for reading the start time, adding the distribution required time to create the clock start time, and setting the data indicating the clock start time in the time circuit via the data bus 21, 20 is A reference time circuit which is composed of a control addition means 40, a clock means 50, an activation means 60 and a selection means 70 connected to the data bus 21, and which is connected to the time circuit via the data bus 21 and the activation signal line 12. 30 is connected to the reference time circuit 20 via the data bus 21 and the activation signal line 12, and has the clock start time set via the data bus 21 as an initial value.
2 is a time circuit that displays the time by starting the time with a start signal distributed via 2.

[0009]

The principle of the present invention will be described with reference to FIG.
Although the case where the number of time circuits is one is illustrated as an example, the case where there are a plurality of time circuits can be similarly explained by providing the activation signal lines 12 corresponding to the number of time circuits.

The processing start time is A, the clock start time is C, and the distribution required time is B. At time A, the control addition means 40 sets the required distribution time B in the activation means 60 and starts the clocking. In addition, a time circuit (that is, a time circuit for adjusting the time to the selecting means 70 by the control adding means 40)
Information for designating the time circuit of the activation signal destination) is set.

Further, the control addition means 40 reads out the processing start time A from the clock means 50, and the distribution required time B
The data representing the clock start time C generated as a result of addition of is added to the time circuit 30 via the data bus 21. When the distribution required time B elapses, a starting signal is generated from the starting means 60 and distributed to the time circuit designated by the selecting means 70 via the starting signal line 12.

The activation signal distributed via the activation signal line 12 activates the clock of the time circuit 30. Even when there are a plurality of time circuits, the preset data representing the clocking start time C is used as the initial value, and the clocks are simultaneously activated via the activation signal line 12 for all of the plurality of time circuits. It is possible to match the displayed time between the reference time circuit 20 and the time circuit 30.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is an explanatory view of an embodiment of the present invention. In FIG. 2, 52 is in the reference time circuit 20,
It is connected to the OSC 51 by the clock pulse line 11, is connected to the CPU 41 and the time circuit 30 via the data bus 21, and is also connected to the start circuit and the selection circuit, and divides the frequency oscillated by the OSC 51 to set the reference time. Reference numeral 41 is a timer for clocking, and 41 is connected in the reference time circuit 20 to the timer 52 and the time circuit 30 via the data bus 21, and in addition to the starting circuit and the selecting circuit, 20 to read the processing start time A from the timer 52 and add the distribution required time B to the dual port RAM (DP
R) 82, the distribution required time B is set in the start circuit, and further information for designating the distribution destination time circuit of the start signal is set in the selection circuit, and 61 is the reference time circuit 20. CP via data bus 21
U41, a timer 52, a selection circuit, and a time circuit 30, a start circuit that counts down with the required distribution time B as an initial value and generates a start signal when it reaches 0, 71 is a reference time circuit 20 And the CPU 41, the timer 52, and the starting circuit 61 via the data bus 21.
Is a selection circuit that is connected to the time circuit 30 via the start signal line 12 and that distributes the start signal to the designated time circuit.
A reference time circuit, which is composed of a CPU 41 and a timer 52 connected to the data bus 21, and is connected to the time circuit via the data bus 21 and the clock pulse line 11,
In the time circuit 30, is a data bus that connects the dual port RAM (DPR) 82 in the time circuit 30, the timer and the CPU. Reference numeral 81 is a data bus in the time circuit 30. Connected to dual port RAM 82 (DPR) and CPU via bus 31, clock pulse line 1
Reference numeral 82 is a timer that is connected to the reference time circuit 20 via 1 to clock the time, and 82 is in the time circuit 30,
A dual port RAM connected to the data bus 21 and the data bus 31, the clock start time C is written via the data bus 21, and the clock start time C is read via the data bus 31 (hereinafter, Abbreviated as DPR), and 91
Is connected to the timer 81 and the DPR 82 via the data bus 31 in the time circuit 30, and the start signal line 1
CP that is connected to the reference time circuit 20 via 2 and reads the clock start time C from the DPR 82 and sets it in the timer 81
U, 30 is a timer 81 and DPR in addition to it
It is a time circuit composed of 82 and CPU 91 for displaying time.

An embodiment of the present invention will be described below with reference to FIG. The OSC 51 always generates a clock pulse at a constant frequency and clocks the timer 52 and the timer 81. At the processing start time A, the CPU 41 generates the distribution required time B (predetermined),
It is set in the starting circuit 61. Further, the data indicating the time circuit for time adjustment is set in the selection circuit 71, and at the same time, the information indicating the processing start time A is read from the timer 52, and the distribution required time B is added and written in the DPR 82.

When the distribution required time B is set, the start-up circuit 61 starts the countdown by the clock pulse and generates a start-up signal when it reaches 0 (that is, when the distribution is completed). The activation signal is distributed to the time circuit designated as the destination by the selection circuit 71 and interrupts the CPU 91.

The CPU 91 reads the clock start time C from the DPR 82 and sets it in the timer 81. Since the clock pulse is always sent, the timer 81 clocks from the clock start time C as a starting point.

[0017]

As described above, the time obtained by adding the required distribution time B to the processing start time A is calculated as the clock start time C of the time circuit.
As a reference time circuit, since all the time circuits receive the clocking start time C in advance and the start signal to the timer of each time circuit is distributed to all the time circuits at the same time. It is possible to match the displayed time between all the time circuits.

Further, since the distribution required time B can take an optimum value according to the number of time circuits to be set, it largely contributes to efficient time information setting and accuracy improvement of the time information.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory view of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 11 Clock pulse line 12 Start signal line 20 Reference time circuit 21 Data bus 30 Time circuit 31 Data bus 40 Control addition means 41,91 Processor (CPU) 50 Clock means 51 Oscillator (OSC) 52,81 Timer 60 Start means 61 Starting circuit 70 Selection means 71 Selection circuit 82 Dual port RAM (DPR)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Kaizu 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Masatsugu Sato 2-4-19 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Fujitsu Program Giken (72) Inventor Tomohiro Ishiyama 2-4-19 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Program Giken Inc.

Claims (4)

[Claims] 1. A reference time circuit and a plurality of time circuits are connected via a data bus, and the reference time circuit distributes data indicating the clock start time of the plurality of time circuits to the plurality of time circuits. In the time information distribution method, a time exceeding a distribution required time for distributing data indicating a clocking start time to the plurality of time circuits is added to the time information distribution processing start time indicated by the reference time circuit, Generating the clock start time of the time circuit, starting the distribution of the data indicating the clock start time to the plurality of time circuits at the distribution processing start time, and generating the plurality of time at the clock start time. A time information distribution method characterized in that the time displayed by the reference time circuit and the time displayed by the plurality of time circuits are matched by activating the clock of the circuit. 2. A reference time circuit connected to a plurality of time circuits via a data bus and a start signal line, and a clock means connected to the control means and the start means for clocking the reference time. Connected to the starting means and the clocking means, controlling the clocking means, setting a time exceeding the distribution required time for distributing the data indicating the clocking start time in the starting means, and performing the distribution processing. To the start time, a time that exceeds the distribution required time for distributing the data indicating the clock start time is added to generate the clock start time, and the data indicating the clock start time is generated via the data bus. A control means for setting the plurality of time circuits, a clock signal connected to the clock means and the control means, and a start signal after a lapse of time exceeding a distribution required time for distributing the data indicating the clock start time. Occurrence and clocking of the plurality of time circuits And starting data for the clock start time at an initial value at the clock start time and simultaneously starting clocks of the plurality of time circuits. A reference time circuit, characterized in that the times shown are coincident with the times shown by the plurality of time circuits. 3. An arbitrary time is generated as a time exceeding a time required to distribute the data indicating the clock start time and set in the starting means, and in addition to the processing start time, the clock start time is indicated. 3. The standard according to claim 2, further comprising control addition means for generating data, wherein the data indicating the clock start time can be generated according to the number of time circuits connected and set in the plurality of time circuits. Time circuit. 4. A selecting unit for selecting a distribution destination time circuit of data indicating the clock start time, and by distributing the activation signal to the distribution destination time circuit, the time circuit is specified and the clock circuit is identified. 3. The reference time circuit according to claim 2, wherein the hour start time can be set.