JPH08327396A - Device for detecting amount of displacement - Google Patents

Abstract

PURPOSE: To automatically obtain an optimum addition/subtraction pulses by converting a relative travel distance detected as a pulse train with a specific resolution and frequency into a pulse train signal which is reduced to an optimum frequency according to the relative travel speed and acceleration between two objects. CONSTITUTION: A next period time Ti+1 for outputting number of pulses ΔNi corresponding to a relative travel distance detected in a periodical time Ti is predicted from a relative travel distance and an acceleration at the time Ti when the relative travel distance is detected and a previous period time Ti-1 , an optimum period time Tp of a discharged pulse is obtained by the predicted period time Ti+1 and the number of pulses ΔNi , and a reduction rate M of a frequency (N×f) of a clock pulse CKI for interpolation is automatically determined to an optimum value from the optimum period time Tp ,thus outputting a clock pulse CKP, namely an addition/subtraction pulse which is reduced to an optimum period time width, namely frequency, for the relative travel distance detected at each period time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in a digital scale system for detecting the position and relative movement amount of, for example, a machine tool or an industrial machine, or a moving table such as a precision measuring and angle measuring device. Regarding the device.

[0002]

2. Description of the Related Art As a digital scale system for detecting a relative movement amount of a moving table of a machine tool or an industrial machine, a magnetic scale to which magnetic recording technology is applied and an optical scale using optical technology are well known. Has been. These digital scale systems are calibrated by a magnetic or optical method and are configured to generate a signal with a reproduction wavelength λ, but the reproduction wavelength λ of the magnetic scale has a relatively large value. , For example 0.2m
m is selected.

Therefore, as a displacement amount detecting device for detecting the displacement amount of a moving table or the like with high resolution, the relative movement amount of the scale and the detection head is taken out as a phase modulation signal, this phase amount is discriminated, and the movement direction is determined. A so-called phase detection type displacement amount detection device, which is configured to output a high-resolution pulse corresponding to the above, has been widely used.

By the way, as a phase detection type displacement amount detecting device, as described in Japanese Patent Publication No. 50-25818 or Japanese Patent Publication No. 50-28032, the amount of phase displacement is determined by the period of this phase modulation signal. Since it can be detected as a change in time, it is detected using a clock pulse that is N times the carrier frequency f of this phase modulation signal, and the reproduction wavelength λ
It is configured so that it can be detected with a resolution of 1 / N.
Therefore, although it has the feature that an arbitrary resolution can be realized very easily by simply setting the frequency of this clock pulse, that is, the value of N, if the resolution is to be increased, the clock is inevitably increased. The pulse frequency N × f must be selected high, resulting in a high output pulse frequency.

For example, the frequency of the interpolation clock pulse CKI when a reproduction wavelength λ of 0.2 mm is used and a carrier frequency of 50 kHz is used to detect a resolution of 1 μm in consideration of the response speed of the system. Is 10
When it is output as it is, the frequency is too high and it is difficult to interface with the connected device, or there is a problem that it cannot be connected.Therefore, the function to reduce the output pulse frequency and output it is required. It was

FIG. 6 is a block diagram showing an example of a conventional displacement amount detecting device. This displacement amount detecting device is a detection head such as a magnetic head 12a, which is designed to move relative to a scale such as a magnetic scale 11. Scale part 1 composed of 12b, scale 11 and detection heads 12a, 1
2b, a phase detection circuit unit 2 that outputs a phase modulation signal according to the relative movement amount, and a resolution R (λ
/ N) and an interpolation circuit unit 3 for generating an addition pulse Up and a subtraction pulse Down according to the moving direction, and the output circuit Up or D
A function for selecting the down frequency and control signals SL0 to SL2 for selection are supplied.

An example of this phase detection circuit section 2 is shown in FIG.
In this example of FIG. 7, a magnetic scale 11 on which a magnetic scale is recorded so that a signal of a reproduction wavelength λ is obtained is used as a scale, and a supersaturated core type magnetic head 12a is used as a detection head.
12b is used.

In FIG. 7, the frequency 20 is f / 2.
Shows an excitation signal input terminal to which the rectangular wave excitation signal EX is supplied. The excitation signal EX supplied to the excitation signal input terminal 20 is supplied to the low-pass filter 26, and a sine obtained at the output side of the low-pass filter 26. The wave signal is supplied to the two-channel magnetic heads 12a and 12b as the excitation signal ex via the excitation amplifier 27.

This excitation signal ex can be expressed as ex = sin (ωt / 2) (1).

The output signal e of the one magnetic head 12a
₁ is supplied to the addition amplifier 23 via the preamplifier 21a, and the output signal e ₂ of the other magnetic head 12b is supplied to the addition amplifier 23 via the preamplifier 21b and the 90 ° phase shifter 22. The output signal of the addition amplifier 23 is supplied to the phase modulation signal output terminal 28 via the bandpass filter 24 and the waveform shaping circuit 25.

In this case, the magnetic heads 12a and 12b are electrically connected to the reproducing wavelength λ of the magnetic scale 11 by 90 degrees.
Since the output signals having a phase difference of ° are obtained, the output signals e ₁ and e ₂ from the preamplifiers 21a and 21b are balanced modulation signals having twice the frequency of the excitation signal ex. And can be expressed as the following equation.

E ₁ = sinωt × cos (2πX / λ) (2) e ₂ = sinωt × sin (2πX / λ) (3) where ω = 2πf and X are positions within the wavelength λ (Absolute position).

By the way, the output signal e of the preamplifier 21b
_After the phase of the carrier is shifted by 90 ° by the 90 ° phase shifter 22, ₂ is added by the adding amplifier 23 and the harmonic component is removed by the bandpass filter 24. The phase modulation signal e _p shown by the equation is obtained. e _p = sin (ωt + 2πX / λ) (4)

This phase-modulated signal e _p has a waveform shaping circuit 2
After being shaped into a rectangular wave by 5, the phase modulation signal output terminal 28
Is guided to the interpolation circuit section 3 via. Since this example is a phase detection type system, the phase modulation signal S converted into a rectangular wave can be expressed as follows if only its phase is focused.

S = sin (ωt + 2πX / λ) (5)

That is, the phase modulation signal S is a rectangular wave signal whose phase changes due to the relative movement of the scale 11 and the magnetic heads 12a and 12b, and its phase amount (2πX /
λ) changes by 2π (= 360 °) for each movement amount λ.

The interpolation circuit section 3 uses a clock pulse having a frequency N times as high as the carrier frequency f of the phase-modulated signal to add pulse U having a resolution of 1 / N of the reproduction wavelength λ.
p and the subtraction pulse Down are output. As described above, the basic principle is to interpolate the phase change amount φ (T) for each cycle time of the phase modulation signal into one cycle time of this phase modulation signal. The number of clock pulses having a frequency of N × f is detected.

Needless to say, the phase change amount φ (T) of the phase modulation signal at rest is zero, and the cycle time at that time is one cycle time T (1 / f of the carrier frequency f of the phase modulation signal. ), And is equal to the number of clock pulses of frequency N × f interpolated in one cycle time of the phase modulation signal at rest. Hereinafter, this pulse number is referred to as a reference pulse number N. Therefore, the phase change amount φ (T) can be detected as a difference ΔN between the number of clock pulses counted in this cycle time and the reference pulse number N.

Here, the rise of the phase modulation signal (or
The fall time shall be used as a reference to measure the cycle time,
This time is t_i-1(I = 1 to n), next time from this time
Tick t _iCycle time to_iIf (i = 1 to n),
This cycle time T_iThe number N of clock pulses interpolated into_i
Changes according to the relative movement of the scale and the magnetic head,
The relative movement amount is ΔN_iIf so, N_i= N + ΔN_iIt can be expressed as (6). Where ΔN_iIs positive or negative
An integer whose sign is in the direction of movement and whose absolute value is minutes.
Output pulse Up in the adding direction in units of resolution R (λ / N)
Corresponds to the number of output pulses Down in the subtraction direction
It

By the way, the frequency of the add / subtract pulse is N × f.
As described above, the reproduction wavelength λ of the scale is 0.2 m, though it depends on the number of divisions N and the carrier frequency f.
applied to the m-system and the carrier frequency f is 50 kHz.
To achieve a resolution of 1 μm as 10 MHz
Since it becomes an extremely high frequency and it becomes very difficult to interface with the connected equipment, a circuit for reducing the frequency of the addition / subtraction pulse was added in the actual interpolation circuit.

A conventional example of the interpolation circuit section 3 is shown in FIG.
Next, an example of the conventional interpolation circuit section 3 will be described with reference to FIG. In FIG. 8, reference numeral 28a denotes a phase modulation signal input terminal to which the phase modulation signal S obtained at the phase modulation signal output terminal 28 of the phase detection circuit unit 2 is supplied, and the phase to be supplied to this phase modulation signal input terminal 28a. The modulated signal S is supplied to the cycle time measuring circuit 33 via the synchronous differentiating circuit 32.

Further, in FIG. 8, reference numeral 31 denotes a timing signal generating circuit, and this timing signal generating circuit 31 is a circuit for generating various timing signals in synchronization with the phase modulation signal S, for example, an interpolation clock pulse C of 10 MHz.
KI, an excitation signal EX of, for example, 25 kHz to the excitation signal input terminal 20 of the phase detection circuit unit 2, a cycle time measurement circuit 33
To generate a clear pulse CL for initialization and a preset pulse PR to an add / subtract counter 37 described later. 20a
Is an excitation signal output terminal for supplying the excitation signal EX to the excitation signal input terminal 20 of the phase detection circuit section 2.

In this case, the phase differentiating signal S and the interpolating clock pulse CKI are supplied to the synchronous differentiating circuit 32, and the rising (falling) time t of the phase modulating signal S.
_The differential pulse D _p synchronized with _i-1 is obtained, and this differential pulse D
_p is supplied to the cycle time measuring circuit 33 and the timing signal generating circuit 31.

In the cycle time measuring circuit 33, the number N _{i of} clock pulses CKI interpolated in the cycle time T _i until the time ti at which the next differential pulse D _p is supplied.
To measure. In this case, the cycle time measuring circuit 33
If an N-ary counter is used as the counter and reset by the clear pulse CL before the counting, the output data N (T _i ) of the period time measuring circuit 33, that is, the N-ary counter at the time t _i, is the pulse N _i. The following values are taken according to the magnitude of the reference pulse number N of.

N (T _i ) = ΔN _i (7) (where N _i ≧ N) N (T _i ) = N−ΔN _i (8) (where N _i <N)

Here, the cycle time T _i extends, that is, N
_If the moving direction when _i ≧ N is defined as the addition direction, this equation (7) expresses the number of pulses in the addition direction in the form of the antilogarithm ΔN _i , and the equation (8) expresses the form of the complement (N−ΔN _i ). Represents the number of pulses in the subtraction direction, and this output data N (T _i ) is transferred to the addition / subtraction counter 37 by the preset pulse PR before counting the next cycle time T _{i + 1} . The output data N (T _i ) of the cycle time measuring circuit 33 is supplied to the control circuit 34.

The control circuit 34 sets the relative movement amount detected at the cycle time T _i , that is, the number of addition pulses and the number of subtraction pulses corresponding to the expressions (7) and (8) to the next cycle time T _{i + 1} . and outputs the control signal PE and subtraction command signal U / D for outputting in correspondence correctly in the moving direction, the control signal PE is not equal .DELTA.N _i is "0", i.e., movement in the periodic time T _i It is a signal that is set when it occurs, and the addition / subtraction command signal U / D is output data N
A signal for adding the addition / subtraction counter 37 when (T _i ) is a complement, that is, N _i <N, and for subtracting the addition / subtraction counter 37 when the output data N (T _i ) is a true number, that is, N _i > N Is.

Reference numeral 38 denotes a clock pulse reduction circuit, which generates a clock pulse CKP for reducing the addition / subtraction pulse of frequency N × f to the optimum frequency for the interface with the connected equipment. This clock pulse reduction circuit 38
Is composed of a reduction circuit that reduces the interpolation clock pulse CKI to generate, for example, eight types of clock pulses having different frequencies, and a selection circuit that selects one clock pulse from these eight types of clock pulse groups. In this example, three selection signals SL0, SL1, SL2
, A clock pulse CKP having a frequency reduced from this clock pulse group to 1 / M (M is a predetermined natural number)
Is selected and the clock pulse CKP is supplied to the respective input sides of the one and the other AND gate circuits 35 and 36.

In this case, the frequency (N / M) × f of the clock pulse CKP is eight kinds of frequencies prepared in advance by the user in consideration of the characteristics of the equipment to be connected and the required response speed. It was selected from.

The control signal PE from the control circuit 34 is supplied to the respective input sides of the one and the other AND gate circuits 35 and 36, and the addition / subtraction command signal U / D from the control circuit 34 is supplied to the one AND gate. The signal is supplied to the input side of the circuit 35, and the inverted signal of the addition / subtraction command signal U / D is supplied to the input side of the other AND gate circuit 36.

The one and the other AND gate circuit 35.
And 36 are connected to the subtraction and addition input terminals of the addition / subtraction counter 37, respectively, and the addition pulse Up and the subtraction pulse Down are externally output from the output terminals of the one and the other AND gate circuits 35 and 36, respectively. Make it output.

In this case, when both the control signal PE and the addition / subtraction command signal U / D are set, this clock pulse CKP is supplied to the subtraction input terminal of the addition / subtraction counter 37 by opening one AND gate circuit 35. At the same time, it is output as an addition pulse Up.

When the control signal PE is set and the addition / subtraction command signal U / D is reset, this clock pulse CKP opens the other AND gate circuit 36 and supplies it to the addition input terminal of the addition / subtraction counter 37. At the same time, it is output to the outside as a subtraction pulse Down.

That is, when the output data N (T _i ) of the cycle time measuring circuit 33 is a complement, the addition / subtraction counter 37 is added, and when the output data N (T _i ) is a true number, the addition / subtraction counter 37 is added. Is controlled so that a carry-down or carry-up pulse OF is generated, the control circuit 34 is reset, and one and the other AND gate circuits 35 and 36 are closed. The number of pulses output to the outside is determined by the period time T _i.
Relative movement amount detected in, that is, N-adic counter 33
Corresponding to the output data N (T _i ) of the clock pulse CKP whose frequency is this clock pulse CKP, that is, the interpolation clock pulse C
KI frequency N × f reduced to 1 / M (N /
M) × f.

[0035]

In the conventional displacement amount detecting apparatus, the number of addition / subtraction pulses corresponding to the moving direction detected as a pulse train having the same clock rate as the interpolation clock pulse CKI of the frequency N × f is reduced. Therefore, a clock pulse reduction circuit including a reduction circuit and a selection circuit that selects one clock pulse from a clock pulse group of a plurality of frequencies output from the reduction circuit is provided.
The configuration is such that the user is left to select the optimum reduction rate M according to the characteristics of the connected device.

Therefore, in order to facilitate the connection, it is desirable to increase the reduction rate M and design the frequency of the clock pulse as low as possible. However, if the frequency of the clock pulse is lowered too much, the processing is performed during this cycle time. Since the number of pulses that can be generated is limited, the response speed decreases. On the contrary, if the frequency of this clock pulse is selected to be high in order to avoid the reduction of the response speed, there is a disadvantage that it cannot be used or malfunction due to the limitation of the response frequency of the connected equipment.

Further, there is an inconvenience that the user is forced to perform an extra work for setting the optimum frequency in consideration of the characteristics of the equipment to be connected.

Further, since the number of selectable clock pulse frequencies is finite, it is necessary to select a frequency resulting from a compromise in consideration of the response frequency of the connected equipment.
For example, when it is applied to a production process or the like, there is a disadvantage that the tact time is increased.

Further, if the number of selectable frequencies is increased in order to improve this inconvenience, not only the reduction circuit becomes complicated, but also the number of control signals is increased due to the selection, which is a circuit. In addition to the increase in the number of terminals when proceeding with the development of the LSI, there is a disadvantage that not only the downsizing of the device becomes difficult but the cost also rises because the switch circuit becomes large because of the switching.

An object of the present invention is to automatically obtain an optimum addition / subtraction pulse (clock pulse) in view of the above point and to prevent the user from performing extra work.

[0041]

DISCLOSURE OF THE INVENTION The displacement amount detecting device of the present invention takes out the relative movement amount between two objects as a phase modulation signal of a carrier frequency f, and the relative movement amount is a frequency N × N times the carrier frequency f. After discriminating using the clock pulse of f and detecting the relative movement amount between these two objects with the resolution of 1 / N unit of the reproduction wavelength λ from the scale, it is output as a pulse signal of two systems according to the movement direction. In the displacement amount detecting device described above, the relative movement amount detected as a pulse train having a resolution of 1 / N of the reproduction wavelength λ and having a frequency of N × f is used as a relative movement speed between the two objects. The signal is converted into a pulse train signal whose frequency is reduced to an optimum frequency according to the acceleration and then output.

[0042]

According to the present invention, the next cycle time T _{i + 1} for outputting the pulse number ΔN _i corresponding to the relative movement amount detected at the cycle time T _i is set to the cycle time T when the relative movement amount is detected. _i and the relative movement amount and acceleration at the previous cycle time T _i−1, and the predicted cycle time T
The optimum cycle time T _p of the emitted pulse is obtained by using _{i + 1} and this pulse number ΔN _i, and the reduction rate M of the frequency N × f of the interpolation clock pulse CKI is calculated from this optimum cycle time T _p.
Is automatically and optimally determined, so that the addition / subtraction pulse reduced to the optimum cycle time width, that is, the frequency, can be output with respect to the relative movement amount detected in each cycle time.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the displacement amount detecting device of the present invention will be described below with reference to the drawings. In this example, in the displacement amount detecting device as shown in FIG. 6, the interpolating circuit portion is constructed as shown in FIG. Therefore, also in this example, the scale unit 1 and the phase detection circuit unit 2 are configured as shown in FIG.

The interpolation circuit section of FIG. 1 according to the present embodiment will be described below. In FIG. 1, parts corresponding to those of FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted. Also in this example, the phase modulation signal S obtained at the phase modulation signal output terminal 28 of the phase detection circuit unit 2 is supplied to the phase modulation signal input terminal 28a.
Through the synchronous differentiating circuit 32, and the cycle time measuring circuit 3
Supply 3

The timing signal generation circuit 31 is a circuit for generating various timing signals in synchronization with the phase modulation signal S, for example, an interpolation clock pulse CKI of 10 MHz,
For example, 2 to the excitation signal input terminal 20 of the phase detection circuit unit 2.
Excitation signal EX of 5 kHz, clear pulse CL for initialization to cycle time measuring circuit 33, and addition / subtraction counter 3 described later.
7 to generate a preset pulse PR.

In this case, in the synchronous differentiating circuit 32,
The phase modulation signal S and the interpolation clock pulse CKI are supplied, and the phase modulation signal S rises (or falls).
The differential pulse D _p synchronized with the time t _i-1 is obtained, and the differential pulse D _p is supplied to the cycle time measuring circuit 33 and the timing signal generating circuit 31.

In the cycle time measuring circuit 33, the number N _{i of the} clock pulses CKI interpolated in the cycle time T _i until the time t _i when the next differential pulse D _p is supplied.
To measure. In this case, the cycle time measuring circuit 33
If an N-ary counter is used as the counter and reset by the clear pulse CL before the counting, the output data N (T _i ) of the cycle time measuring circuit 33, that is, the N-ary counter at time t _i, is the number N of pulses. Depending on the magnitude of the reference pulse number N of _i , it takes a value as shown in equations (7) and (8).

In this case, the cycle time T _i extends, that is, N
_If the moving direction when _i ≧ N is defined as the addition direction, this equation (7) expresses the number of pulses in the addition direction in the form of the antilogarithm ΔN _i , and the equation (8) expresses the form of the complement (N−ΔN _i ). Represents the number of pulses in the subtraction direction, and this output data N (T _i ) is transferred to the addition / subtraction counter 37 by the preset pulse PR before counting the next cycle time T _{i + 1} . The output data N (T _i ) of the cycle time measuring circuit 33 is supplied to the control circuit 34.

The control circuit 34 sets the relative movement amount detected at the cycle time T _i , that is, the number of addition pulses and the number of subtraction pulses corresponding to the expressions (7) and (8) to the next cycle time T _{i + 1} . It outputs a control signal PE and an addition / subtraction command signal U / D that are output in correct correspondence to the moving direction. This control signal PE moves when ΔN _i is not “0”, that is, at the cycle time T _i . Is a signal which is set when the output data N is output.
When (T _i ) is a complement, that is, N _i <N, the addition / subtraction counter 37 is added, and when the output data N (T _i ) is a true number, that is, N _i > N, the addition / subtraction counter 37 is subtracted. It is a signal.

Reference numeral 40 denotes a clock pulse reduction circuit, and in this example, the clock pulse reduction circuit 40.
Is generated to reduce the clock pulse CKP to an optimum frequency according to the moving speed and the acceleration. Instead of the conventional control signals SL0 to SL2 for frequency selection, preset data from the reduction rate calculation circuit 41 is used. An arbitrary reduction rate is automatically set by M (T).

FIG. 2 shows the clock pulse reduction circuit 40.
2 shows an example in which two 4-bit preset counters 40a and 40b are used to obtain an arbitrary reduction rate in the range of 1 to 256.

That is, to the preset terminals L of the counters 40a and 40b, the OR signal of the preset signal PR from the preset signal input terminal 40d and the output pulse CKP from the counter 40b is added via the OR gate circuit 40c. 8-bit data M (T) is added to the preset data input terminals A to D of the counters 40a and 40b, and the counters 40a and 40b output the counter 40b at the start of counting the next cycle time. Each time the pulse CKP is generated, the value of the data M (T) is preset and the interpolation clock pulse CKI from the clock pulse input terminal 40e is counted to obtain the maximum count value 255.
The output pulse CKP is generated at the time of reaching.

Therefore, this preset data M (T)
Is configured so that a value of 0 to (M-1) can be selected for each cycle time, a clock pulse reduction circuit having an arbitrary reduction rate of 1 to 256 for each cycle time can be realized. it can. That is, the reduction circuit 40 reduces the frequency N × f of the interpolation clock pulse CKI to (N × f / 1).
It is possible to generate the clock pulse CKP reduced to an arbitrary frequency of (N × f / 256).

Further, the reduction rate calculation circuit 41 determines that the cycle time T
_The number of pulses Δ corresponding to the amount of relative movement detected at _i
The next cycle time T _{i + 1} for discharging N _i is predicted, and the optimum cycle time T _p of the discharged pulse is obtained from the predicted cycle time T _{i + 1} and the number of pulses ΔN _i to be discharged. The optimum reduction rate M (T _i ) of the interpolation clock pulse CKI of the frequency N × f is determined from the optimum cycle time T _p .

The optimum reduction rate M (T _i ) is obtained as an integer value which satisfies the following equation. T _p × | ΔN _i | <T _{i + 1} ‥‥‥‥ (9) M (T _i ) / (N × f) <T _p ‥‥‥‥ (10)

[0056] Incidentally, the next period time T _{i + 1} is the period time T _i the amount of movement reaches the time t _i which is detected, the movement amount in the periodic time T _i-1 before the movement amount is detected Δx
_{from i} and Δx ₋₁ , the velocity V _{i at} each cycle time,
It is desirable to determine V _i-1 and set it in consideration of this speed.

Here, the amount of movement and the speed at each cycle time are obtained as follows. x _i = ΔN _i × R (11) x _i-1 = ΔN _i-1 × R (12) V _i-1 = f × λ × ΔN _i-1 / N _i-1 (13) V _i = f × λ × ΔN _i / N _i (14) where R = λ / N and λ are reproduction wavelengths

[0058] Also, determine the acceleration alpha _i in period time T _i from the speed change Delta] v _i in the period time T _i-1 and T _i, it is desirable to predict in view of the acceleration.

Here, Δv _i = V _i −V _i−1 (15) α _i = Δv _i / T _i = (V _i −V _i-1 ) / T _i ··· (16) = f ² × λ × (ΔN _i / N _i −ΔN _i-1 / N _i-1 ) × N / N _i (17)

The amount of movement at the cycle time T _i and the cycle time T _i-1 is a known value, but the next cycle time T _{i + 1}
Is unknown, and it may not always be possible to infer it only from the extension of the past history. For example, it may move in the opposite direction in the next cycle time. Therefore, the predicted value T
_It is desirable to consider the worst value (minimum value) of _{i + 1} in advance, and take care to avoid problems such as ending the pulse within the predicted value T _{i + 1} without releasing the pulse.

Further, the maximum acceleration α _max and the maximum velocity V _max allowed as the displacement amount detecting device are limited, the next cycle time T _{i + 1} is predicted in consideration of these specified values, and the runaway occurs. It is desirable that the system malfunction can be detected.

FIG. 3A shows the concept of applying this rule concerning the prediction of the next cycle time T _{i + 1} when moving in the adding direction. For convenience of explanation, the prediction is performed. The velocity and cycle time are underlined, and V _{i + 1} , T
_It is expressed as _{i + 1} .

[0063] At time t _i, the displacement amount in the displacement amount [Delta] x _i-1 and the velocity V _i-1 cycle time T _i of the periodic time T _i-1 [Delta] x _i and the speed V _i are known, further the speed with the acceleration alpha _i is determined at periodic time T _i. Therefore, in the next cycle time T _{i + 1} , it is expected that the same acceleration α _i as in the cycle time T _i will be applied and the speed V _{i + 1} will be reached.

However, both speed and acceleration are positive.
The cycle time is the movement in the extending direction.
In the opposite direction, that is, the cycle time becomes shorter
When a movement in the direction occurs, this expected speed V_{i + 1}Or
Cycle time predicted value calculated fromT _{i + 1} Then emit a pulse
Will run out of time.

Here, the maximum acceleration allowed in the system
α_maxFrom the maximum speed change Δv _maxSpeed in the opposite direction
Is assumed to changePredicted value T _{i + 1} Is the worst value (minimum
Value), this predicted speed V_{i + 1}The following formula
Worst speed V shown in_{i + 1}From this speed to
Predicted value T_{i + 1}Ask for. V_{i + 1}= V_i+ Δv_i-Δv_max(18)

FIG. 3B shows the concept of prediction when moving in the subtracting direction. In this case, moving in the reverse direction is a direction in which the cycle time becomes longer, and the cycle time T
worst value of the predicted value T _{i + 1} in the _{i + 1} (minimum), as shown in the following equation, maximum acceleration, i.e., the maximum velocity change Δv
_It can be predicted as moving at the _maximum in the same direction as in the cycle time T _i .

V _{i + 1} = V _i + Δv _max (19)

However, this equation (18) and equation (19)
Shows the concept of correction, and the same symbols are used, but the cycle time T changes depending on changes in the moving direction and speed.
_i is different, and the absolute value of the speed is also different.

By the way, in the present example, the displacement amount detecting device is
Maximum acceleration α_max, Maximum speed V _maxStipulates
Therefore, the actual acceleration and
_max, Maximum speed V_maxBy comparing with
Detecting that the moving speed exceeds the allowable speed of the output device,
Can be output as an alarm signal ALM
It

FIG. 4 shows an example of the reduction rate calculation circuit 41.
The next cycle predicted according to the rules above
Interval T_{i + 1}Optimal reduction rate M (T_i) To the table
Stored in the ROM 41c as a data, and the cycle time T_i-1as well as
Cycle time T_iNumber of pulses corresponding to_iAnd N_{i + 1}Use
Next cycle time T_{i + 1}Optimal reduction rate M corresponding to
(T _i) Is configured to refer to. Below, FIG.
An example of the reduction rate calculation circuit 41 will be described with reference to FIG.

Input terminal 4 of one shift register 41a
1e is the output data N of the cycle time measuring circuit 33.
(T _i ) is input, and the output terminal of the one shift register 41a is connected to the input terminal of the other shift register 41b and the lower address terminal AL of the ROM 41c. The other shift register 41
The output terminal of b is connected to the upper address terminal AH of the ROM 41c.

On the other hand, the equal shift registers 41a and 41b
The preset signal PR from the preset signal input terminal 41f is added to the clock input terminal of. Therefore, the period and measurement end of the time T _i, at the time of transfer preset signal PR has occurred the output data N (T _i), the one of the shift register 41a, the output of the periodic time T _i data N (T _i ), that is, the pulse number N _i , and the other shift register 41b holds the data N (T _i-1 ) at the previous cycle time T _i-1 , that is, the pulse number N _{i- 1.} It Therefore, from the ROM 41c, the pulse number N _i-1 is set as the upper address AH, and the pulse number N _i is set as the lower address AH.
The data M (T) of the address to be L is output.

Here, at this address, the optimum reduction rate M corresponding to the next cycle time T _{i + 1} predicted by the above-mentioned rule.
Since the data corresponding to (T _i ) is stored, this output is set in the M _i -adic counter of the clock pulse reduction circuit 40 by the transfer preset signal PR.

[0074] That is, the movement amount N _i in each cycle time T _i
In at the time the measurement has finished holds also moving amount N _i-1 in the previous cycle time T _i-1, using these data to predict the next period time T _{i + 1,} the predicted value From T _{i + 1} , an optimum reduction rate M (T _i ) for emitting a pulse with a pulse number ΔN _i corresponding to the amount of movement detected at the cycle time T _i with an appropriate pulse width T _p can be obtained. Therefore, the output pulse can be emitted with the optimum pulse width according to the moving speed and the acceleration for each cycle time.

Next, the comparison circuit 41d compares the maximum speed V _max defined by the phase detection circuit with the actual speed V at each cycle time to generate the alarm signal ALM. . Here, in the actual comparison, as shown in the equations (13) and (14), the velocity V _i
The clock pulse number N _i to be inserted into the respective period duration T _i
Therefore, the maximum value of the number of clock pulses corresponding to the maximum speed V _max , that is, N _max is compared with the number N _i of clock pulses at each cycle time T _i .

Further, in this example, the comparison circuit 41d is used for the generation of the alarm signal, but the speed and acceleration are the number of clock pulses N interpolated in the cycle time T _i as described above.
Since it can be calculated from _{i, the} maximum velocity V _max and the maximum acceleration α _max allowed in the displacement amount detecting device are N _max and Δ, respectively.
It can correspond to N _max (= N _i −N _i−1 ).

Therefore, the next cycle time T_{i + 1}Predicted value T of
_{i + 1}In the ROM 41c storing _max, ΔN_maxWhen
The number N of clock pulses detected by the actual movement_iWhen
Stores the comparison result of the maximum speed V_maxAnd maximum acceleration
α_maxIs exceeded, that is, the next cycle time T_{i + 1}Prediction of
Value T_{i + 1}In the ROM 41c storing_max, ΔN_ma
xAnd the clock pulse N detected by the actual movement_i
Stores the result of comparison with the maximum speed V_maxAnd maximum acceleration
α_maxExceeds the condition, that is, an alarm signal should be generated
The state of the reduction rate M (T
_i), A pattern that does not conflict with
Reduction rate M (T_i), The highest bit of the bit string
M₇The alarm signal is stored in the
It can also be configured to output as a signal.

The clock pulse CKP obtained at the output side of the clock pulse reduction circuit 40 is supplied to the respective input sides of the one and the other AND gate circuits 35 and 36.

Further, the control signal PE from the control circuit 34 is supplied to the respective input sides of the one and the other AND gate circuits 35 and 36, and the addition / subtraction command signal U / D from the control circuit 34 is supplied to the one AND gate. The signal is supplied to the input side of the gate circuit 35, and the inverted signal of the addition / subtraction command signal U / D is supplied to the input side of the other AND gate circuit 36.

The one and the other AND gate circuit 35
And 36 are connected to the subtraction and subtraction input terminals of the addition / subtraction counter 37, respectively, and the addition pulse Up and the subtraction pulse Down are output to the outside from the output terminals of the one and the other AND gate circuits 35 and 36, respectively. I will do it.

In this case, when both the control signal PE and the addition / subtraction command signal U / D are set, this clock pulse CKP is supplied to the subtraction input terminal of the addition / subtraction counter 37 by opening one AND gate circuit 35. At the same time, it is output as an addition pulse Up.

When the control signal PE is set and the addition / subtraction command signal U / D is reset, this clock pulse CKP opens the other AND gate circuit 36 and supplies it to the addition input terminal of the addition / subtraction counter 37. And outputs it as a subtraction pulse Down to the outside.

That is, the output data of the cycle time measuring circuit 33
N (T_i) Is a complement, the addition / subtraction counter 37 is added.
This output data N (T_i) Is an exact number
Is controlled in the direction of subtracting the addition / subtraction counter 37,
This control is performed by generating a carry-down or carry-up pulse OF.
The circuit 34 is reset and one and the other AND gate circuit is turned on.
Summing pulse Up to the outside until paths 35 and 36 are closed
Alternatively, it is configured to output the subtraction pulse Down.
Therefore, the number of pulses output to the outside depends on the cycle time T _ismell
Detected relative movement amount, that is, the output data of the N-adic counter 33.
Data N (T_i), And its frequency is
It is equal to the lock pulse CKP.

As described above, according to this example, the cycle time T _i
Pulse number ΔN corresponding to the relative movement amount detected in
_The next cycle time T _{i + 1} that outputs _i is predicted by the cycle time T _i at which this relative movement amount is detected and the relative movement amount and acceleration at the previous cycle time T _i−1 , and this prediction is made. The optimum cycle time T _p of the emitted pulse is obtained by using the calculated cycle time T _{i + 1} and the pulse number ΔN _i, and the frequency N of the interpolation clock pulse CKI is calculated from the optimum cycle time T _p.
Since the reduction rate M of × f is automatically and optimally determined, the clock pulse CKP, that is, the addition / subtraction pulse reduced to the optimum cycle time width, that is, the frequency is output with respect to the relative movement amount detected in each cycle time. can do.

Therefore, according to this example, the addition pulse U to the outside
Since the p and the subtraction pulse Down are reduced to the optimum frequency according to the operating speed, acceleration, etc., means and work for optimally selecting the frequency of this pulse according to the characteristics of the connected equipment as in the past. Not only becomes easy for the user to connect to the device, but also malfunctions due to incorrect settings are eliminated, which is advantageous for downsizing and cost reduction of the device, and it can be adapted to the device to which the user is connected. Thus, there is an advantage that not only the trouble of adjusting the frequency of the pulse is not required but also the inconvenience that the frequency is too high to connect is eliminated.

Further, according to the present example, the velocity, acceleration, etc. in the cycle in which the movement amount is detected are calculated from the movement amount in the cycle in which the movement amount is detected and the movement amount in the cycle time immediately before that. Since the next cycle time for emitting the number of pulses corresponding to this detected movement amount is predicted from the speed, acceleration, etc., the continuity related to the cycle time prediction is high, and it can be predicted as a smoothly changing cycle time. As a result, there is an advantage that an output whose pulse width changes smoothly can be obtained with respect to changes in the moving speed and the acceleration.

Further, according to this example, the maximum acceleration and the maximum velocity allowed in the displacement amount detecting system are specified, and the worst value of the predicted next cycle time, that is, the maximum value, which is based on the specified limit value, The predicted cycle time is corrected in the direction in which the cycle time is shortened, and the reduction rate of the output pulse is determined based on this corrected cycle time.Therefore, the predicted cycle time is too short to release the pulse. It is possible to obtain a displacement amount detection device that does not have any problems such as the end, and when a discharge failure at the maximum speed and the maximum acceleration is detected, it can be treated as a malfunction of the system and the reliability of the system can be improved. There are benefits that can be increased.

Although the reduction rate calculation circuit 41 is constructed as shown in FIG. 4 in the above embodiment, the basic operation of the reduction rate calculation circuit 41 is arithmetic operation, and it should be constructed by using a microcomputer. You can When a microcomputer is used as the reduction rate calculation circuit 41, the circuit shown in FIG.
The process may be performed according to the process flow shown in.

That is, in FIG. 5, first, respective velocities and accelerations relative to the scale of the detection head at times t _i-1 and t _i are calculated. Next, it is determined whether the moving direction at this time is the adding direction or the subtracting direction. When the moving direction is the adding direction, it is determined whether the velocity V _i and the acceleration α _i are larger than the maximum velocity V _max and the maximum acceleration α _max , and V _i > V _max or α _i > α _max.
In case of, the alarm signal ALM is set and the process ends.

At this time, V _i ≤V _max and α _i ≤α _max
Then, the speed V _{i + 1} = V _i + Δv _i −V _max at the next cycle time is calculated, the next cycle time T _{i + 1} is calculated from this speed V _{i + 1,} and the next cycle time T is calculated. _The reduction rate M is calculated from _{i + 1} , and the process ends.

When the moving direction is the subtraction direction, it is judged whether the velocity V _i and the acceleration α _i are larger than the maximum velocity V _max and the maximum acceleration α _max , and V _i > V _max or α _i > α.
When it is _max , the alarm signal ALM is set and the process ends.

At this time, V _i ≤V _max and α _i ≤α _max
When the, to calculate the velocity _{V i + 1 = V i +} V max in the next cycle time, the next cycle time T _{i + 1} from the velocity V _{i + 1} is calculated, the next period time T _{i + The} reduction rate M is calculated from ₁ and the process ends. In this example, the reduction rate M obtained in this processing flow is supplied to the clock pulse reduction circuit 40, and the clock pulse reduction rate circuit 40 produces a clock pulse CKP having an optimal frequency reduced according to the reduction rate M. I'll get it.

Further, in the above-mentioned embodiment, an example using a magnetic scale has been described, but it goes without saying that other scales such as an optical scale may be used.

Further, in the above-mentioned embodiment, the phase modulation signal is obtained by using the two detection heads 12a and 12b, but other means, for example, the detected scale signal is multiplied by the sine wave signal and the cosine wave signal to modulate it. Of course, the phase modulation signal may be obtained from this.

Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0096]

According to the present invention, the addition pulse Up to the outside is increased.
Since the subtraction pulse Down is reduced to the optimum frequency according to the operating speed, acceleration, etc., means or work such as optimal selection of the frequency of this pulse is performed in accordance with the characteristics of the connected device as in the past. Not only is it unnecessary for the user to connect to the device, but there is no malfunction due to incorrect settings, which is advantageous for device downsizing and cost reduction. There is an advantage that not only the trouble of adjusting the frequency of the pulse is unnecessary but also the inconvenience that the connection is impossible because the frequency is too high.

Further, according to the present invention, from the movement time in the cycle time when the movement amount is detected and the cycle time immediately before that,
By calculating the velocity, acceleration, etc. at the cycle time at which this movement amount is detected, the next cycle time at which the number of pulses corresponding to this detected movement amount is emitted is predicted from this calculated velocity, acceleration, etc. The cycle time prediction has high continuity and can be predicted as a smoothly changing cycle time, and as a result, there is an advantage that an output having a smoothly changing pulse width with respect to changes in the moving speed and acceleration can be obtained.

Further, according to the present invention, the maximum acceleration and the maximum velocity allowed in the displacement amount detecting system are specified, and based on the specified limit values, the worst value of the predicted next cycle time, that is, The predicted cycle time is corrected in the direction in which the cycle time is shortened, and the reduction rate of the output pulse is determined based on this corrected cycle time.Therefore, the predicted cycle time is too short to release the pulse. It is possible to obtain not only a displacement detection device that does not have a problem such as completion, but also when a discharge failure at the maximum speed and the maximum acceleration is detected, it can be treated as a malfunction of the system and the reliability of the system is improved. There are benefits that can be.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of an interpolation circuit unit used in a displacement amount detecting device of the present invention.

FIG. 2 is a configuration diagram showing an example of a clock pulse reduction circuit.

FIG. 3 is a diagram for explaining the present invention.

FIG. 4 is a configuration diagram showing an example of a reduction rate calculation circuit.

FIG. 5 is a flowchart for explaining an example of a reduction rate calculation.

FIG. 6 is a configuration diagram showing an example of a displacement amount detection device.

FIG. 7 is a configuration diagram showing an example of a phase detection circuit unit.

FIG. 8 is a configuration diagram showing an example of a conventional interpolation circuit unit.

[Explanation of symbols]

 1 Scale Section 2 Phase Detection Circuit Section 3 Interpolation Circuit Section 11 Magnetic Scale 12a, 12b Magnetic Head 21a, 21b Preamplifier 22 90 ° Phase Shifter 23 Addition Amplifier 31 Timing Signal Generation Circuit 32 Synchronous Differentiation Circuit 33 Period Time Measurement Circuit 34 control circuit 35, 36 AND gate circuit 37 adder / subtractor counter 40 clock pulse reduction circuit 40a, 40b counter 40c OR gate circuit 41 reduction rate operation circuit 41a, 41b shift register 41c ROM 41d comparison circuit

Claims (6)

[Claims] 1. A relative movement amount between two objects is taken out as a phase modulation signal of a carrier frequency f, and the relative movement amount is discriminated using a clock pulse having a frequency N × f which is N times the carrier frequency f, and the above-mentioned 2 A displacement amount detecting device configured to detect a relative movement amount between objects with a resolution of 1 / N unit of a reproduction wavelength λ from a scale and then output as pulse signals of two systems according to a movement direction, The relative movement amount detected as a pulse train having a resolution of 1 / N of λ and a frequency of N × f is reduced to an optimum frequency according to the relative movement speed and acceleration between the two objects. A displacement amount detecting device characterized in that it is converted into a pulse train signal and outputted. 2. The displacement amount detecting device according to claim 1, wherein the holding unit holds a cycle time when the relative movement amount between the two objects is detected and a cycle time immediately before the relative movement amount is detected. The relative movement speed and acceleration at the cycle time when the relative movement amount is detected are obtained from these cycle times and the cycle time at rest, and the relative movement speed and acceleration correspond to the relative movement amount. The next cycle time of emitting the pulse is predicted, and the reduction rate for reducing the signal of the pulse train having the frequency of N × f is obtained from the predicted cycle time and the number of pulses to be emitted. Characteristic displacement amount detection device. 3. The displacement amount detecting device according to claim 1, wherein the displacement amount detecting device is allowed a next cycle time predicted from a relative movement speed and an acceleration at a cycle time when the relative movement amount is detected. The maximum value of the predicted next cycle time is corrected using the maximum velocity and the maximum acceleration, and the reduction rate of the pulse train to be discharged is determined based on the corrected cycle time. A displacement amount detection device characterized in that measurement errors due to incomplete pulse are prevented. 4. The displacement amount detecting device according to claim 1, wherein the maximum velocity and maximum acceleration allowed by the displacement amount detecting device and the actual movement velocity and acceleration determined in the cycle time when the relative amount of movement is detected. And detecting that the actual moving speed and acceleration exceed the maximum speed and maximum acceleration allowed by the displacement amount detecting device, and output the detected signal as an abnormal signal. Displacement amount detection device characterized by. 5. The displacement amount detecting device according to claim 1, wherein a holding unit holds data corresponding to a cycle time when the relative movement amount is detected and a cycle time before the relative movement amount is detected. And a storage means for referring to data corresponding to these cycle times as an address, and reducing the pulse train at the next cycle time for sending out the detected relative movement amount by the output from the referenced address. A displacement amount detection device characterized in that the rate is determined. 6. The displacement amount detecting device according to claim 1, which holds data corresponding to a cycle time when the relative movement amount is detected and a cycle time before the relative movement amount is detected. And storage means for referring to data corresponding to these cycle times as an address, and storing the result of comparison between the speed and acceleration allowed by the displacement amount detecting device at the referenced address. The displacement amount detecting device is characterized in that a specific pattern of the compared results is discriminated to be an abnormal signal.