JP3018576B2 - Jitter correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a jitter amount suitable for a movement amount detecting apparatus which detects a movement amount based on a phase modulation signal corresponding to a relative movement amount between two objects which move relatively. Related to the device.

[0002]

2. Description of the Related Art As a prior art of a jitter correction apparatus for detecting the relative movement amount by interpolating a phase modulation signal whose phase is changed according to the relative movement amount between two objects moving relatively, For example, the technology disclosed in Japanese Utility Model Publication No. 58-52484 filed by the present applicant can be cited.

In this technique, a phase modulation signal is obtained by relatively moving two detection heads arranged at a fixed interval in the length direction of the magnetic scale on a magnetic scale having a fixed cycle. Like that. Then, the phase modulation signal obtained in this manner is interpolated by an interpolation clock to display one cycle of the magnetic scale on a display with high resolution. The jitter correction processing as shown is performed.

In this jitter correction processing, as shown in FIG. 7, a phase modulation signal S contains a jitter Tj and a falling edge 8 which is a measurement edge of the phase modulation signal S.
When the phase difference between any falling edge, for example, falling edge 4 among falling edges 1 to 7 which is a counting edge of the interpolation clock CP (an edge whose count value changes by a counter not shown) is small. In this configuration, the count value of the interpolation clock CP is prevented from being changed and displayed as the count value = 3 or 4 due to the jitter Tj of the phase modulation signal S. That is, in such a case, the falling edge 8 of the phase modulation signal S is delayed by a predetermined CR (capacitor and resistance) delay circuit by a phase difference Δφ corresponding to approximately １ ／ cycle of the interpolation clock CP. This is to control to generate the phase modulation signal S ′.

[0005] Even if the jitter Tj occurs in the phase-modulated signal S 'thus delayed, the falling edge 4 which is the counting edge of the interpolation clock CP is not included in the range of the jitter Tj. , The count value of the interpolation clock CP becomes a constant value when the count value = 4, and the display on the display (not shown) does not fluctuate.

[0006]

By the way, in order to realize the above-described correction processing, the phase difference between the falling edge, which is the counting edge of the interpolation clock CP, and the falling edge of the phase modulation signal S is determined. A phase difference measurement circuit to be measured, a switch that opens and closes according to the binary output of the phase difference measurement circuit, and the CR delay circuit whose operation is controlled by the switch are required. However, in the above-described conventional jitter correction apparatus, when the frequency of the interpolation clock CP is increased in order to increase the resolution in order to further increase the accuracy, the cycle of the interpolation clock CP,
In other words, there is a complication that a new CR delay circuit corresponding to the resolution is required. Further, multi-axis, for example,
If these are to be applied to a moving amount detecting device in which three magnetic scales or the like are attached to a machine tool or the like based on three axes, such CR delay circuits are individually provided in three circuits for each axis. In addition to the necessity, the above-described phase difference measurement circuit is also required for each axis, so that three circuits are required for each axis, and the manufacturing cost is significantly increased due to an increase in the number of components and an increase in the wiring board area. there were.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can be used for a phase modulation signal for each axis generated in relation to multiple axes, and can be used regardless of resolution. It is an object of the present invention to provide a jitter correction device which enables the above.

[0008]

According to the present invention, a jitter correcting apparatus is provided.
Is a scale 1 as shown in FIGS. 1 and 2, for example.
And detection heads 2 and 3 relatively moving on the scale 1
Is provided for each axis of the multi-axis, and the relative movement of each axis
The phase modulation signals XS, YS, ZS for each axis are
Scale devices 12, 13, 14 for each axis to be output;
The phase modulation signals XS, YS, ZS for each axis are supplied.
A switching circuit 21 for selectively taking them in,
Interpolation with phase modulation signal XS selected by conversion circuit 21
Clock / CP and CP are supplied to perform jitter correction control
Signal S_FourAnd the synchronized phase modulation signal S_ThreeOutput signal processing
Circuit 41 and the phase modulation signals XS, YS,
ZS, interpolation clock / CP, and synchronization phase modulation signal S3
Are supplied, and the phase modulation signal count values XD, Y for each axis are supplied.
Interpolation circuit that outputs D, ZD and interpolation clock count value CD
Path 40 and a phase modulated signal for each axis from interpolation circuit 40
Count values XD, YD, ZD and interpolation clock count value CD;
Jitter correction control signal S from signal processing circuit 41 _FourAnd sync
Phase modulated signal S_ThreeAnd an arithmetic circuit 30 to which
The jitter correction control signal output from the signal processing circuit 41
No. S_FourIs a counting edge of the phase modulation signals XS, YS, ZS.
Determine the level of the interpolation clock CP at the time,
Depending on the level, it may be low level or high level.
The arithmetic circuit 30 detects the detection heads 2 and 3
Is moving relatively in one direction or in one direction.
In the stationary state after the operation, the interpolation clock count value CD
Output without correction, while the opposite of the above one direction
Jitter correction control when in the stationary state after moving in the direction
Complement to the interpolation clock count value CD according to the level of the signal S4.
The output is multiplied by a positive number.

[0009]

According to the present invention, the level of the interpolation clock CP at the time of the counting edge of the phase modulation signal XS is determined, and the level of the interpolation clock CP becomes low or high according to the level.
Only one signal processing circuit 41 for outputting the phase correction control signal S4 as a value signal is provided, and the signal processing circuit 41 is shared by the scale devices 12, 13, and 14 of each axis. Then, when the detection heads 2 and 3 are relatively moving in one direction or in a stationary state after moving in the one direction,
The interpolated clock count value CD is output without correction, while when the interpolated clock count value CD is stationary after moving in the direction opposite to the one direction, the interpolated clock count value CD is adjusted according to the level of the jitter correction control signal S4. Is corrected, and the output is performed, so that the display 42 that performs display based on this output does not cause jitter, that is, display flicker.

Further, since the phase correction control signal S4 is generated corresponding to the cycle of the interpolation clock CP, it can be used regardless of the resolution.

Therefore, it is possible to share a phase modulation signal for each axis generated in relation to multiple axes, and to use it regardless of the resolution.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a jitter correcting apparatus according to the present invention. In this example,
Machine tool having three axes of X, Y and Z axes (not shown)
However, the present invention is not limited to three axes. The present invention can be applied to a machine tool having at least two axes. In FIG. 2, reference numeral 1 denotes a magnetic scale attached to the X axis, which has a constant period (for example, 200 μm).
A magnetic scale is formed by the sine wave signal of m).
The scale is not limited to a magnetic scale, but may be an optical scale, a capacitive scale, or the like.

There are provided first and second detection heads 2 and 3 which are magnetic heads relatively moving on the magnetic scale 1 in the longitudinal directions R and L. The interval P between the first detection head 2 and the second detection head 3 is arranged at an interval of P = (m ± 1/4) · λ (m is an integer), where λ is the fixed period. .

The input side of the first and second detection heads 2 and 3 is supplied with an excitation current signal having a carrier frequency f 0/2 from an excitation circuit 4. The excitation circuit 4 is supplied from the signal generator 7 with a signal having a carrier frequency f0 / 2. The clock pulse CP is supplied from the oscillator 6 to the signal generator 7. Note that the clock pulse CP is also used as an interpolation clock as will be described later, and is also referred to as an interpolation clock CP as needed.

In such a configuration, the first and second
Are relatively moved in the longitudinal direction R or the opposite direction L on the magnetic scale 1 so that the first and second detection heads 2 and 3 form a sine wave by the magnetic scale 1. A modulated signal is obtained. Here, the sine-wave modulated signal from the first detection head 2 is supplied to one input terminal of an adder 9 through a π / 2 phase shifter 8. On the other hand, the sine-wave modulated signal from the second detection head 3 is directly supplied to the other input terminal of the adder 9. The phase modulation signal S ₁ is extracted from the signal added by the adder 9 through the band pass filter 10. This phase modulation signal S ₁ is well known (for example, Japanese Patent Application Laid-Open No. 57-514, Japanese Patent Application Laid-Open No.
-53484), the following equation 1
Is a signal represented as shown in FIG.

[0016]

S ₁ = sin (ωt + (2π / λ) x)

Here, the symbol x represents the moving distance in the longitudinal directions R and L of the magnetic scale 1, and ω is ω = 2 · π · f0.

Here, assuming that the cycle of the clock pulse CP is the cycle Tcp, the cycle of the carrier frequency f0 is the cycle T0, and the required resolution per cycle λ of the scale is n, the first and second detection heads 2 and 3 when at rest, the period Ts of the phase modulation signals S ₁ becomes Ts = n · Tcp. On the other hand, when the first and second detection heads 2 and 3 are relatively moving with respect to the scale 1, the phase modulation signal S
The period of ₁ changes, and the movement amount d becomes d = nTcp-Ts (unit is time). Therefore, the moving distance 1 on the scale 1 is expressed as follows: l = {(nTcp−Ts) / n} · λ = (λ / n) · d

The phase modulation signal S ₁ having such attributes
Is shaped by the limiter circuit 11, and the X-axis scaler 12 outputs the X-axis phase modulation signal XS, which is a square wave output signal.

Similarly, the Y-axis phase modulation signal YS and the Z-axis phase modulation signal ZS are output from scale devices 13 and 14 configured to correspond to the scale device 12.

The phase modulation signals XS to ZS for each axis, the clock pulse CP, and the clock pulse / CP which is an inverted signal of the clock pulse CP are supplied to the jitter correction circuit shown in FIG.

The jitter correction circuit shown in FIG. 1 includes a selector 21 as a switching circuit, an interpolation circuit 40, a signal processing circuit 41, an arithmetic circuit 30, and a display circuit 42.

Here, the selector 21 outputs a 2-bit axis selection signal S2 supplied to the control terminals A and B from the arithmetic circuit 30.
Is supplied to the signal processing circuit 41 (in this embodiment, the phase modulation signal XS).

The signal processing circuit 41 includes a flip-flop 3
1 and flip-flops 15 and 16, and the selector 2
Phase modulation signal XS and interpolation clock CP selected by 1, and generates the synchronized phase-modulated signal S ₃ and jitter correction control signal S ₄ based on the / CP.

The interpolation circuit 40 includes phase modulation signals XS to ZS.
Counters 22 to 24 for counting the falling edge of
These count values are stored in the latch clock LK (synchronized phase modulation signal).
No. S _Three) To hold the phase modulation signal count values XD to ZD.
Latches 25 to 27 to be supplied to the arithmetic circuit 30 and interpolation clocks
A counter 33 for counting the falling edge of the clock CP;
The count value is held by the latch clock LK and interpolation is performed.
Latch 32 for supplying lock count value CD to arithmetic circuit 30
Is provided.

The arithmetic circuit 30 is a microprocessor, and as will be described in detail later, the detecting heads 2 and 3 are relatively moving in one direction (for example, direction R) or are in a stationary state after moving in that direction R. sometimes, outputs without applying correction in the interpolation clock count value CD to the display circuit 42, whereas, when in the mobile after a stationary state in the direction L opposite to the direction R, in response to the level of the jitter correction control signal S ₄ Then, the interpolation clock count value CD is corrected and output to the display circuit 42. The display circuit 42 is provided with the arithmetic circuit 3
The display drive circuit (not shown) is connected to the display drive circuit and the display is controlled by the display drive circuit (not shown).

Next, with respect to the operation of the above embodiment, first, the calculation processing of the movement amount by the interpolation circuit 40 and the like will be described.
Second, a description will be given of a jitter correction process for the movement amount by the signal processing circuit 41 and the like.

A. Calculation of Movement Amount by Interpolation Circuit 40 and the Like The X-axis will be described with reference to the time chart of FIG. 3 and the flowchart of FIG. In this case, the arithmetic circuit 3
By the selector 21 on the basis of the axis selection signal S ₂ of 0 X-axis of the phase modulation signal XS (see Fig. 3D) is selected, it is supplied to the data input terminal D of the flip-flop 31 (step S1).

The flip-flop 31 synchronizes the supplied phase modulation signal XS with the rising edge of the clock pulse / CP and outputs a synchronized phase modulation signal S ₃ (see FIG. 3E) (point t 1 in FIG. 3). reference). The synchronization is performed in order to prevent occurrence of an error of ± 1 count due to jitter or the like in the counter 33 and the counters 22 to 24.

The arithmetic circuit 30 determines the point at which the supplied synchronized phase modulation signal S ₃ shifts from a low level to a high level (time t).
Is monitored (step S2, step S3).

[0031] Then, a point going from the synchronization phase modulation signal S ₃ of the low level to the high level, in other words, the rise edge, the latch 25 as a latch clock LK
And when supplied to the first latch 32, in this case,
At time t1, the latch 25 outputs the phase modulated signal X
The counter 22 holds the X-axis phase modulation signal count value XD counted up to the falling edge 43a of S by the counter 22, while the latch 32 holds the interpolation clock count value XCD up to the interpolation clock CP1 (see FIG. 3A). You. These X-axis phase modulation signal count data XD and interpolation clock count data X
The CD is read into the arithmetic circuit 30 (step S
4).

Similarly, the arithmetic circuit 30 outputs the axis selection signal S ₂
The selector 21 selects the other Y-axis and Z-axis phase modulation signals YS and ZS based on the, and latches the Y-axis and Z-axis phase modulation signal count values YD and ZD for the selected phase modulation signals YS and ZS. , 27, and the interpolated clock count values YCD, ZCD are sequentially received from the first latch 32. Then, again, for example, at time t2, the count value X of the X-axis phase modulation signal up to the falling edge 43q by the latch clock LK.
D and the interpolation clock count XC up to the interpolation clock CP2
D is read into the arithmetic circuit 30 (again, step S
4). Here, the arithmetic circuit 30 calculates the movement amount dx as shown in Expression 2 from the current count value captured at the time t2 and the previous count value captured at the time t1 (step S5). In addition, the meaning of each symbol in Formula 2 is as follows. dx: Movement amount XCDnew: Current X-axis interpolation clock count value XCDold: Previous X-axis interpolation clock count value n: Resolution per cycle λ (corresponding to the number of interpolation clocks) XDnew: Current X-axis phase modulation Signal count value XDold: Previous X-axis phase modulation signal count value

[0033]

Dx = XCDnew−XCDold−n (XDnew−XDold)

In this way, the movement amount dx can be calculated, and the movement amount dx can be displayed on the display constituting the display circuit 42.

The above operation has been described for the calculation of the movement amount dx by the interpolation circuit 40 and the like. next,
The jitter correction processing by the signal processing circuit 41 and the like will be described.

B. The jitter correction processing by the signal processing circuit 41 and the like will be described with reference to the time chart of FIG. 5 and the flowchart of FIG. The jitter is generated in the phase modulation signals XS to ZS due to mechanical vibration, noise, and the like of the magnetic heads 2 and 3 (see FIG. 2), and the amount of the jitter is 以下 or less of the period Tcp of the clock pulse CP. Has been confirmed. Also, the jitter is a problem in the counting edges of the phase modulation signals XS to ZS, and in the present embodiment, the falling edges correspond. Further, the jitter correction processing according to the present embodiment is performed in the following case.

In FIG. 2, the detection heads 2 and 3
No jitter correction processing is performed during the movement. This is because there is no problem even if the display on the display constituting the display circuit 42 flickers because the display is moving.

The detection heads 2 and 3 are arranged in a direction L in FIG.
No jitter correction processing is performed during the movement. For the same reasons as in the case of

The detection heads 2 and 3 are arranged in a direction R in FIG.
No jitter correction processing is performed even when the operation is stopped after moving to step (1). This is because, as described later, it is possible to cope with the software of the arithmetic circuit 30.

In FIG. 2, the detection heads 2 and 3
Then, when the operation is stopped, jitter correction processing is performed. If the jitter correction process is not performed, there is a possibility that the display of the display device constituting the display circuit 42 may flicker even during the stop.

[0041] First, a description the characteristics of the jitter correction control signal S _4.

The flip-flops 15 and 31 selected by the selector 21 (see FIG. 1)
5C is shown in FIG. 5C. When the falling edge 51a of the phase modulation signal XS is within the high level section of the interpolation clock CP (in FIG. 5,
The output Q of the flip-flop 15 shifts from high level to low level at the next rising edge 52a of the interpolation clock CP. The output / Q (S ₃ ) of the flip-flop 31 shifts from a low level to a high level at the next rising edge 53a (see FIG. 5B) of the interpolation clock / CP (see FIG. 5E). At this time, the jitter correction control signal S ₄ which is the output / Q of the flip-flop 16
Shifts from the high level to the low level (FIG. 5F, position a2).
Point).

As described above, when the falling edge 51a of the phase modulation signal XS is within the high-level section of the interpolation clock CP, thereafter, the period T of the interpolation clock CP
phase modulation signal S ₄ within half cycle of the cp is that the state becomes a low level signal is maintained.

On the other hand, when the rising edge 51b of the phase modulation signal XS is within the low-level section of the interpolation clock CP (see the point b1 in FIG. 5), the output Q of the flip-flop 15 becomes the output Q of the interpolation clock CP. At the next rising edge 52b, the level shifts from the high level to the low level (see FIG. 5D). Also, the output / Q of the flip-flop 31
(S ₃ ) shifts from low level to high level at the next rising edge 53b of the interpolation clock / CP. At this time,
Phase correction control signal S _4, which is an output / Q of the flip-flop 16 goes from low level to high level (see FIG. 5F, the position b2 points).

As described above, when the falling edge of the phase modulation signal XS is within the low-level section of the interpolation clock CP, then the period Tcp of the interpolation clock CP becomes 1
/ Within two periods the phase correction control signal S ₄ so that the state becomes a high level signal is maintained.

Next, the jitter correction processing by the arithmetic circuit 30 will be described. First, capture the jitter correction control signal S _4, determines whether the high level (Fig. 6, step S11). When the level is at the high level, the previous X-axis interpolation clock count value XCDold is updated to the current X-axis interpolation clock count value XCDnew without performing the jitter correction process (step S12).

In the following description, the display circuit 4
It is assumed that the value of XCDnew is displayed on a display (not shown) constituting No. 2 (step S13).

[0048] it does not hold the determination in step S11, performs the determination process for the next few 3 when the level of the jitter correction control signal S ₄ is at the low level (step S14).

[0049]

XCDnew−XCDold ≧ 0

When the value on the left side of Equation 3 is 0, it is determined that the vehicle is stationary after moving in the direction R (the direction in which the count value increases). When the value is positive, the vehicle is moving in the direction R. Since it is determined that there is, the processing of steps S12 and S13 described above is performed without performing the jitter correction processing.

If the value on the left side of Equation 3 is a negative value, the following Equation 4 is determined (Step S15).

[0052]

XCDnew−XCDold = −1

If the value on the left side of Equation 4 is not −1, that is, if it is a value of −2 or less, it is determined that the movement is in the direction L because the count value is decreasing. ,
Steps S12 and S1 described above without performing the jitter correction process
Step 3 is performed.

When the right side of Equation 4 is −1, that is, when it is stationary after moving in the direction L, and when the jitter correction control signal S ₄ is in the high level state (determination in step S 1). Is not satisfied, this condition is satisfied), and the jitter correction process is performed (step S16). That is, the previous X-axis interpolation clock count value XCDold is used as is for the current X-axis interpolation clock count value XCDold.
The update processing as shown in step S12 is not performed as CDnew. Then, the X-axis interpolation clock count value XCDnew that has not been updated is displayed (step S).
13).

This jitter correction processing will be described with reference to FIG. In FIG. 5, when the falling edge of the phase modulation signal XS moves in the direction R, the interpolation clock count value X
It is assumed that the CD is in the increasing direction, and when the CD moves in the opposite direction L, the interpolation clock count value XCD is in the decreasing direction.

Now, it is assumed that the phase modulation signal XS moves in the direction L and stops at the position b1 '. In this state, the phase-modulated signal XS is at the high level of the interpolation clock CP, jitter correction control signal S ₄ is in a state of low level within a half period of the period Tcp (FIG. 5C, the position point a1 And the position a2), so that the jitter correction processing is not performed. When there is jitter in the phase modulation signal XS and the falling edge 51b moves to the regions e to f of the interpolation clock CP (see point b1 in the figure), the jitter correction control signal S ₄
Becomes high level within １ ／ of the cycle Tcp, and the jitter correction process is performed.

That is, in this jitter correction processing, the detection heads 2 and 3 stop after moving in the direction L, and at that time, the falling edge 51b of the phase modulation signal XS is set to the interpolation clock C.
In the state in P a low level (state jitter correction control signal S ₄ becomes a high level in the half period of the periodic Tcp), to process so as not to subtract the interpolation clock count value XCD. In other words, even if the counting edge f is passed from right to left in the figure, the counting is not performed, and the previous interpolation clock count value XCDold is not counted.
Is regarded as the current interpolation clock count value XCDnew.

As described above, according to the above-described embodiment, the jitter correction process is performed based on the relationship between the level of the interpolation clock CP and the count edge of the phase modulation signal XS.
Even if the resolution changes (even if the period of the interpolation clock CP changes), the jitter can be automatically corrected.
There is no need for a delay circuit corresponding to the resolution as shown in the prior art, and there is an advantage that the circuit is significantly simplified.

Further, the jitter correction processing is performed after the phase modulation signals XS, YS, ZS are selected and taken in by the selector 21, so that the signal processing circuit 31 related to the jitter correction processing can be shared. There is an advantage that is.

The present invention is not limited to the above-described embodiment, but can adopt various configurations without departing from the gist of the present invention.

[0061]

As described above, according to the present invention,
A signal processing circuit that determines the level of the interpolation clock at the time of counting edges of the phase modulation signal and outputs a phase correction control signal that is a binary signal having a low level or a high level according to the level is provided, and only one circuit is provided. The signal processing circuit is shared by the scale devices of each axis. When the detection head is moving relatively in one direction or in a stationary state after moving in the one direction, the interpolation clock count value is output without correction, while the detection clock is opposite to the one direction. In the stationary state after moving in the direction of, the interpolation clock count value is corrected and output in accordance with the level of the jitter correction control signal. This has the effect of preventing the display from flickering.

Further, since the phase correction control signal is generated corresponding to the cycle of the interpolation clock, there is an effect that it can be used regardless of the resolution.

Therefore, it is possible to share the phase modulation signal for each axis generated in relation to multiple axes and to use the signal regardless of the resolution.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment of a jitter correction apparatus according to the present invention.

FIG. 2 is a circuit block diagram illustrating an X-axis to Z-axis phase modulation signal generation circuit.

FIG. 3 is a time chart for explaining the operation of an interpolation process in the circuit shown in FIG. 1;

FIG. 4 is a flowchart provided to explain an operation of an interpolation process in the circuit shown in FIG. 1;

FIG. 5 is a time chart for explaining an operation of a jitter correction process in the circuit shown in FIG. 1;

FIG. 6 is a flowchart provided to explain an operation of a jitter correction process in the circuit shown in FIG. 1;

FIG. 7 is a time chart for explaining the operation of a conventional jitter correction apparatus.

[Explanation of symbols]

Reference Signs List 21 selector 30 arithmetic circuit 40 interpolation circuit 41 signal processing circuit CD interpolation clock count value S ₃ synchronization phase modulation signal S ₄ jitter correction control signal XD to ZD phase modulation signal count value

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01D 5/00-5/252 G01D 5/39-5/62

Claims (1)

(57) [Claims] 1. A scale and a detection head which relatively moves on the scale are provided for each of the multiple axes, and output a phase modulation signal for each of the axes according to the relative movement amount of each of the axes. A scale device for each axis, a switching circuit for supplying a phase modulation signal for each axis and selectively taking in the phase modulation signal, and a phase modulation signal and an interpolation clock selected by the switching circuit. A signal processing circuit for outputting a jitter correction control signal and a synchronized phase modulation signal, and a phase modulation signal for each axis, an interpolation clock and the synchronized phase modulation signal being supplied, and a phase modulation for each axis. An interpolation circuit that outputs a signal count value and an interpolation clock count value; a phase modulation signal count value and an interpolation clock count value for each axis from the interpolation circuit; and a jitter correction control from the signal processing circuit. Signal and synchronization position An arithmetic circuit to which a phase modulation signal is supplied, wherein the jitter correction control signal output from the signal processing circuit determines the level of the interpolation clock at the counting edge of the phase modulation signal, and determines the level. A low-level signal or a high-level signal corresponding to the binary signal. When the detection head is relatively moving in one direction or in a stationary state after moving in the one direction, The interpolation clock count value is output without being corrected, while, when moving in the direction opposite to the one direction and in the stationary state, the interpolation clock count value is corrected according to the level of the jitter correction control signal. A jitter correction device, wherein