JPH0832636A - Frequency offset detection device - Google Patents

Abstract

PURPOSE:To reduce the scale of hardware and to reduce software processing quantity by executing a frequency offset detection processing without obtaining the phase of a reception signal when a known symbol is added to a transmission signal and transmitting the signal in a receiver inputting a signal obtained by orthogonally detecting the reception signal amplified through the use of the amplifier of a fixed envelope type. CONSTITUTION:A first memory 107 storing the reception signal for the known signal, a second memory 108 storing a known transmission signal, a complex correlation unit 109 obtaining the complex correlation of the signal of the memory 107 and the signal of the memory 108, an envelope calculation circuit 110 obtaining the envelope of a correlation result, an address calculation circuit 111 calculating an address for obtaining a frequency offset by table extraction from an obtained envelope value and a third memory 112 storing a frequency offset value as against the address calculated from the envelope value are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset detecting device in a receiver of a digital communication device.

[0002]

2. Description of the Related Art In recent years, digitization of communication has been remarkable. In communication equipment, it is difficult to exactly match the fundamental frequency of the transmitter and the fundamental frequency of the receiver, so that the fundamental frequency of the receiving side is generally adjusted to the transmitting side based on the received signal. Therefore, it is an important technique to obtain a good voice quality by detecting the difference between the transmitted frequency and the received frequency, that is, detecting the frequency offset.

FIG. 14 shows the configuration of a communication device equipped with a conventional frequency offset detecting device. In FIG. 14, 1 is a transmitter, 2 and 3 are antennas, 4 is a receiver, 5,
6 is the I and Q signals output from the receiver 4, 7 and 8 are A / D converters, 9 and 10 are A / D
Digital signals output from the converters 7 and 8, 11 is a memory for storing data, 12 and 13 are data output from the memory 11, 14 is a phase controller, and 15 and 16 are output from the phase controller 14. Reference numeral 17 is a decoder, and reference numeral 18 is a decoded data. Further, 19 and 20 are I data and Q data extracted from the memory 11, 21 is a reception phase calculator for calculating reception phases of I data and Q data, 22 is a calculated reception phase, and 23 is an error calculator. , 24 is a memory for storing a synchronization word, 25 is a sum of error squares output from the error calculator 23, 26 is a minimum point detector for obtaining the minimum point of the error square sum 25, and 27 is a pilot symbol obtained from the minimum point. The address of the rough estimated position, 28 is the rough estimated frequency offset value at the minimum point, 29 and 30 are data extracted from the memory 11 according to the address 27, 31 is data 29,
A reception phase calculator for obtaining a deviation of 30, a reception phase for 32, an error calculator for 33, a memory for storing a synchronization word, a sum of squared errors output from error calculator 33, and an error for 36 An identification point detector that obtains an identification point from the minimum point of the sum of squares 35, 37 is an address of the identification point, and 38 is an offset frequency at the minimum point.

Next, the frequency offset detecting operation in the above conventional example will be described. One specific data is selected from the memory 11, the reception phase calculator 21 calculates the reception phase 22, and the error calculator 23 calculates the error sum of squares 25 and the frequency offset. The minimum point detector 26 obtains the minimum point of the error sum of squares 25, obtains the rough estimation value 27 of the pilot symbol from this minimum point and sends it to the memory 11, and also obtains the frequency offset rough estimation value 28 to obtain the error calculator. 33. Next, the reception phase calculator 31 obtains the reception phase 32 of the pilot symbol, and the error calculator 33 corrects the reception phase 32 with the frequency offset rough estimation value 28 from the minimum point detector 26 and a known pilot symbol. The error sum of squares 35 of is calculated. The identification point detector 36 finds the minimum point of the error sum of squares 35, finds the address 37 of the identification point from this minimum point and sends it to the memory 11, and also finds the offset frequency 38 and sends it to the phase controller 14. The phase controller 14 receives the data 12 and 13 designated by the address 37, corrects the frequency offset of the data 12 and 13 in accordance with the offset frequency 38, and decodes the corrected data 15 and 16. The data is input to the device 17 to be decoded, and the decoded data 18 is output.

As described above, the conventional communication device can detect and correct the frequency offset.

[0006]

However, in the above-mentioned conventional configuration, although there is an advantage that the detection of the frequency offset can be detected stably without being affected by the short section fluctuation, the reception signal of the received signal can be detected. Since there is a process for detecting the phase (arctan (x, y) process), there has been a problem that the hardware scale when implemented by hardware and the processing amount when implemented by software increase.

The present invention solves such a conventional problem, and eliminates the processing for detecting the phase of the received signal and realizes it in hardware scale or software in realization. It is an object of the present invention to provide a frequency offset detection device capable of reducing the processing amount of.

[0008]

In order to achieve the above object, the present invention transmits known symbols in a receiver for inputting a signal obtained by quadrature detection of a received signal amplified by a constant envelope type amplifier. When transmitting in addition to a signal, a first memory that stores a reception signal corresponding to a known signal, a second memory that stores a known transmission signal, a signal of the first memory, and a second memory A complex correlator that obtains the complex correlation of the signal, an envelope calculation circuit that obtains the envelope of the correlation result, an address calculation circuit that performs the address calculation to obtain the frequency offset from the obtained envelope value by table lookup, And a third memory for storing the frequency offset value for the address calculated from the envelope value.

The present invention also provides a receiver for inputting a signal obtained by quadrature detection of a reception signal amplified by a constant envelope type amplifier, in the case where a known symbol is added to the transmission signal and transmitted, A first memory for storing a received signal of the first and a second memory for storing a known transmitted signal;
A complex correlator that obtains the complex correlation between the signal of the second memory and the signal of the second memory, a power calculation circuit that obtains the power of the correlation result, and an address calculation to obtain the frequency offset from the obtained power value by table lookup An address calculation circuit for performing the calculation and a third memory for storing the frequency offset value for the address calculated from the power value are provided.

Further, according to the present invention, in a receiver for inputting a signal obtained by quadrature detection of a reception signal amplified by using a constant envelope type amplifier, when a known symbol is added to the transmission signal and transmitted, A first memory for storing a received signal of the first and a second memory for storing a known transmitted signal;
Complex correlator that obtains the complex correlation between the signal of the memory of the second memory and the signal of the second memory, an envelope calculation circuit that obtains the envelope of the correlation result, and an envelope that obtains the frequency offset from the obtained envelope value by an approximate expression. And a frequency offset conversion circuit.

Further, according to the present invention, in a receiver for inputting a signal obtained by quadrature detection of a reception signal amplified by using a constant envelope type amplifier, when a known symbol is added to the transmission signal and transmitted, A first memory for storing a received signal of the first and a second memory for storing a known transmitted signal;
Complex correlator that obtains the complex correlation between the signal of the second memory and the signal of the second memory, a power calculation circuit that obtains the power of the correlation result, and a power / frequency offset conversion that obtains a frequency offset from the obtained power value by an approximate expression And a circuit.

[0012]

According to the present invention, with the above-described configurations, the processing for detecting the phase of the received signal can be eliminated, and the frequency offset can be detected by the calculation of the product and the sum. It is possible to reduce the amount of processing when it is realized by software or software.

[0013]

【Example】

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a frequency offset detecting apparatus according to the first embodiment of the present invention. FIG.
In FIG. 1, 101 is a limiter amplifier to which a signal transmitted from a transmitter by adding a known symbol to the transmitted signal is received by a receiver and the received signal converted to an intermediate frequency is input, and 102 is an output of the limiter amplifier. A quadrature detection circuit that performs quadrature detection and outputs an in-phase component I signal and a quadrature component Q signal. Reference numerals 103 and 104 denote low-pass filters that pass respective low-pass portions of the output I signal and Q signal.
5, 106 are A / D converters for digitizing the low-pass I and Q signals respectively, 107 is a first memory for storing reception signals corresponding to known signals, and 108 is a known transmission signal 2nd memory, 109 is a complex correlator that obtains the complex correlation between the signals of the first memory 107 and the second memory 108, 110 is an envelope calculation circuit that obtains the envelope of the correlation result, and 111 is obtained An address calculation circuit for calculating an address for obtaining a frequency offset from the envelope value obtained by a table lookup, and a third memory 112 for storing a frequency offset value for the address calculated from the envelope value.

The operation of the frequency offset detecting apparatus configured as described above will be described below using the configuration of FIG. 1 and the frame format of FIG.

(1) Transmission signal The transmission signal is shown in equation (1-1). However, I (t) is an in-phase component and Q (t) is a quadrature component. s (t) = I (t) + jQ (t) (1-1)

(2) Input signals of A / D converters 103 and 104 When the transmission signal represented by the equation (1-1) is input, the reception level fluctuates due to fading or the like. Here, only the fluctuation of the reception level is considered, ignoring the phase fluctuation due to fading. The received signal is as shown in equation (1-2). rl (t) = α (t) {I (t) + jQ (t)} (1-2) where I (t) is the in-phase component, Q (t) is the quadrature component, and α (t) Is the level fluctuation of the received signal at time t. Also, the phase of the received signal rotates due to the frequency offset, which is the frequency difference between the transmitted and received signals of the transmitter and the receiver. This is represented by formula (1-3). r2 (t) = α (t) {I (t) + jQ (t)} exp (j (at + b)) = r2I (t) + jr2Q (t) (1-3) where a [rad / s] is The amount of phase rotation per unit time, b [rad] is the phase difference at time t = 0. When this signal is amplified by a saturated amplifier, the envelope of the received signal has a constant value (here, A). When expressed by a formula, it becomes like a formula (1-4). r3 (t) = A {I (t) + jQ (t)} exp (j (at + b)) = r3I (t) + jr3Q (t) (1-4) This input signal is converted into A / D converters 103 and 104. When it is made into a discrete value with, it becomes like the formula (1-5). r4 (nT) = A {I (nT) + jQ (nT)} exp (j (anT + b)) = r4I (nT) + jr4Q (nT) (1-5) where T [s] is a sampling time interval, Here, one symbol time is taken as an example. Of course, it is possible to improve the accuracy by setting the sampling time interval to an integral multiple of one symbol time. a [rad / s] is the amount of phase rotation per sampling time, and b [rad] is the phase difference at time t = 0.

(3) Frequency Offset Detection Operation Theory Next, the operation theory of the frequency offset detection in this embodiment will be described. A known signal is transmitted as N symbols in the transmission signal. Usually, this known signal is called a sync word or a sync symbol. In this embodiment, it is called a sync word. Data corresponding to the synchronization word (N symbols) is taken out from the reception signal, and the complex correlation processing as shown in equation (1-6) is performed with the reception signal of the known synchronization word stored in the receiver.

[Equation 1] However, N samples are stored in the memory from the data at time nT, and this is shown as I (iT) + jQ (iT).
I0 (iT) is the in-phase component of the i-th symbol of the sync word, and Q0 (iT) is the quadrature component of the i-th symbol of the sync word.

At the reception time of the sync word, since the received signal is also the sync word, the expression (1-7) is given.

[Equation 2]

Here, the normal synchronization symbol is transmitted so that the envelope is constant. Here, for the sake of simplicity, the envelope is 1
And Then, the formula (1-7) becomes like the formula (1-8).

(Equation 3)

The equation (1-9) is obtained by obtaining this envelope.

[Equation 4]

As described above, the envelope of the complex correlation value is a function of the phase change amount a [rad / s] per symbol. Therefore, the value of a can be obtained by obtaining ua. However, since it is generally difficult to solve the equation (1-9) for a, ua is obtained in advance using a as a parameter, and ua is used as an index.
It is realized by creating a table that subtracts the value of.

(4) Practical operation of frequency offset detection Next, regarding the practical operation of frequency offset detection,
The operation of the complex correlator 109, the operation of the envelope calculation circuit 110, and the operation of the address calculation circuit 111 will be described in this order. However, the number of synchronization words is 3 symbols.

(4-1) Operation of Complex Correlator 109 The first memory 107 stores the received signals for the synchronization words. The second memory 108 stores a known signal for the synchronization word. FIG. 3 shows a configuration example of the complex correlator 109.
Shown in In FIG. 3, 301 and 302 are multipliers and 30
3, 304 are adders, 305 and 306 are constant multipliers, 30
Reference numerals 7 and 308 are adders. When the formula (1-6), which is the calculation formula of the complex correlator 109, is expanded, the formula (1-10) is obtained. FIG. 3 faithfully realizes the equation (1-10). However, uI is an in-phase component and uQ is a quadrature component.

(Equation 5) Although the 1 / N circuit is provided in the embodiment of the complex correlator 109, a) In order to eliminate the 1 / N circuit, the amplitude of the known signal stored in the second memory 108 is set to 1 / N. Method b) There is a method of ignoring the 1 / N coefficient in the address calculation circuit. In practice, choose a) or b) for simplicity. Although a configuration as shown in FIG. 3 may be adopted for a sync word of about 3 symbols as in the present embodiment, when the sync word becomes long, it is better to perform complex multiplication for each symbol by time division processing. .

(4-2) Operation of Envelope Calculation Circuit 110 An embodiment of the envelope calculation circuit 110 is shown in FIG. In FIG. 4, 401 and 402 are input terminals, 403 and 404 are multipliers, 406 is an adder, 408 is a square root calculation circuit, and 40
In the envelope calculation circuit 110, which is an output terminal, the expression (1
-11) is embodied.

(Equation 6)

(4-3) Operation of Address Calculation Circuit 111 An embodiment of the address calculation circuit 111 is shown in FIG. 105
, 501 is an input terminal, 502 is an adder, 504
Is a multiplier, 506 is a truncation circuit, and 507 is an output terminal. The address calculation circuit 111 includes a third memory 112.
An integer address is created from ua in order to obtain a from the table. The maximum value of the envelope of the correlation value is A. Therefore, an equation for calculating the address when the address is M bits using this is shown in equation (1-12).

(Equation 7) However, [x] is a process of obtaining the integer part of x.

As described above, according to the first embodiment of the present invention, the phase of the received signal is detected (arctan (x, y) processing).
Since the frequency offset can be detected by calculating the product and the sum, it is possible to reduce the hardware scale when implemented by hardware and the processing amount when implemented by software.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows the configuration of the frequency offset detecting apparatus in the second embodiment of the present invention. In FIG. 6, reference numeral 601 denotes a limiter amplifier which receives a signal transmitted by adding a known symbol from a transmitter to a transmission signal at a receiver and inputs a reception signal converted to an intermediate frequency, and 602 denotes a limiter amplifier. A quadrature detection circuit that quadrature-detects the output and outputs an in-phase component I signal and a quadrature-component Q signal, 603 and 604 are low-pass filters that pass respective low-pass parts of the output I signal and Q signal, 605 606 is an A / D converter for digitizing the low-pass I and Q signals, and 607 is a first memory for storing a received signal corresponding to a known signal, 6
08 is a second memory for storing a known transmission signal, 609
Is a complex correlator that obtains a complex correlation between the respective signals of the first memory 607 and the second memory 308, 610 is a power calculation circuit that obtains the power of the correlation result, and 611 is a frequency offset by table lookup from the obtained power value. An address calculation circuit for calculating an address for obtaining
Reference numeral 2 is a third memory for storing the frequency offset value for the address calculated from this power value.

The present embodiment differs from the first embodiment in that the envelope calculation circuit 110 is changed to a power calculation circuit 610 and the address calculation circuit 111 obtains a frequency offset based on the envelope. On the other hand, in the address calculation circuit 611 of the present embodiment, the frequency offset is calculated based on the power, and the third memory 112.
While the frequency offset is tabulated based on the envelope curve, the third memory 612 of the present embodiment is used.
Is that the frequency offset is table-drawn based on the power.

The frequency offset detecting apparatus configured as described above will be described focusing on the points different from the first embodiment.

(1) Power Calculation FIG. 7 shows the configuration of the power calculation circuit 610.
Reference numeral 02 is an input terminal, 703 to 704 are multipliers, 705 is an adder, and 706 is an output terminal. Power calculation circuit 61
0 embodies the equation (2-1). ua2 = uI ² + uQ ² (2-1)

(2) Address Calculation FIG. 8 shows the configuration of the address calculation circuit 611. 801 is an input terminal, 802 is an adder, 803 is a multiplier, 804 is a truncation circuit, and 805 is an output terminal. The address calculation circuit 611 creates an integer address from ua2 in order to obtain a from the third memory 612 by table lookup. The maximum value of the envelope of the correlation value is A ² . Therefore,
Using this, an equation for calculating an address when the address has M bits is shown in equation (2-2).

(Equation 8) However, [x] is a process of obtaining the integer part of x.

(3) Third Memory In the third memory 612, the power of the complex correlation result is obtained in advance using a as a parameter, and the power of the complex correlation result is used as an address and the value of a for that address is stored. .

As described above, according to the second embodiment of the present invention, since the square root circuit can be eliminated as compared with the first embodiment, it is possible to reduce the software processing amount or the hardware scale. Further improvement can be achieved.

(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 9 shows the configuration of a frequency offset detecting apparatus according to the third embodiment of the present invention. In FIG. 9, reference numeral 901 denotes a limiter amplifier which receives a signal transmitted by adding a known symbol from a transmitter to a transmission signal at a receiver and inputs a reception signal converted to an intermediate frequency, and 902 denotes a limiter amplifier. A quadrature detection circuit that quadrature-detects the output and outputs an in-phase component I signal and a quadrature-component Q signal. Reference numerals 903 and 904 denote low-pass filters that pass respective low-pass portions of the output I signal and Q signal. , 906 is an A / D converter for digitizing the low-pass I and Q signals, and 907 is a first memory for storing a received signal corresponding to a known signal, 9
08 is a second memory for storing a known transmission signal, 909
Is a complex correlator that obtains the complex correlation between the signals of the first memory 907 and the second memory 908, 910 is an envelope calculation circuit that obtains the envelope of the correlation result, and 911 is an approximate expression from the obtained envelope value. It is an envelope / frequency offset conversion circuit that obtains a frequency offset by

The present embodiment is different from the first embodiment in that in the first embodiment, the frequency offset is obtained from the envelope of the complex correlation value by the table look-up, but in the present embodiment, the complex correlation value is obtained. The point is that an approximate expression for obtaining the frequency offset from the correlation value of is used.

The frequency offset detecting apparatus configured as described above will be described focusing on the points different from the first embodiment.

(1) Envelope / Frequency Offset Conversion FIG. 10 shows the configuration of the envelope / frequency offset conversion circuit 911. 1001 is an input terminal, 1002 is a multiplier, 1
003 is an adder and 1004 is an output terminal. envelope/
In the frequency offset conversion circuit 911, the approximate expression is the expression (3
The case of -1) is assumed. When the approximate expression is of the third order or higher, the configuration is different from that in FIG. 10, but the circuit configuration may be adapted to it. f _offset = cl × ua + dl (3-1)

As described above, according to the third embodiment of the present invention, since the third memory is unnecessary by implementing the approximation formula, the hardware scale can be further reduced.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 11 shows the configuration of a frequency offset detecting apparatus according to the fourth embodiment of the present invention. In FIG. 11, reference numeral 1101 denotes a limiter amplifier which receives a signal transmitted by adding a known symbol from a transmitter to a transmission signal at a receiver and inputs a reception signal converted to an intermediate frequency, and 1102 denotes a limiter amplifier. The output is quadrature-detected and the in-phase component I signal and quadrature component Q
A quadrature detection circuit that outputs a signal, 1103 and 1104 are low-pass filters that pass respective low-pass portions of the output I signal and Q signal, and 1105 and 1106 are digitized low-pass I and Q signals, respectively. A /
D converter, 1107 is a first memory for storing a reception signal of a known signal, 1108 is a second memory for storing a known transmission signal, and 1109 is a first memory 1107 and a second memory 1108. A complex correlator 1110 for obtaining the complex correlation of each signal is a power calculation circuit 1110 for obtaining the power of the correlation result, and 1111 is a power / frequency offset conversion circuit for obtaining the frequency offset from the obtained power value by an approximate expression.

The present embodiment differs from the second embodiment in that in the second embodiment, the frequency offset is obtained from the envelope of the complex correlation value by table lookup, but in the present embodiment, the complex correlation value is obtained. The point is that an approximate expression for obtaining the frequency offset from the power value of is used.

The frequency offset detecting apparatus constructed as described above will be explained focusing on the points different from the second embodiment.

(1) Power Calculation FIG. 12 shows the configuration of the power calculation circuit 1110.
1201 and 1202 are input terminals, 1203 to 1204 are multipliers, 1205 is an adder, and 1206 is an output terminal. The power calculation circuit 1110 embodies the equation (3-1). ua2 = uI ² + uQ ² (4-1)

(2) Envelope / Frequency Offset Conversion FIG. 13 shows the configuration of the envelope / frequency offset conversion circuit 1111. 1301 is an input terminal, 1302 is a multiplier, 1303 is an adder, and 1304 is an output terminal. is there.
In the envelope / frequency offset conversion circuit 1111, it is assumed that the approximate expression is the expression (4-2). Although the configuration when the approximate expression is of the third order or higher is different from that of FIG. 13, a circuit configuration corresponding to it may be used. f _offset = c2 × ua2 + d2 (4-2)

As described above, according to the fourth embodiment of the present invention, by changing the envelope to the power, the square root circuit becomes unnecessary, and the software processing amount or the hardware base portion is further reduced. be able to. Further, since the third memory is unnecessary by implementing the approximation formula, the hardware scale can be further reduced.

[0045]

As is apparent from the above-described embodiments, the present invention can be realized by hardware because the processing for detecting the phase of the received signal is eliminated and the frequency offset can be detected by the operation of the product and the sum. It is possible to reduce the amount of hardware required for processing and the amount of processing required for software implementation.

[Brief description of drawings]

FIG. 1 is a block diagram of a frequency offset detection device according to a first embodiment of the present invention.

FIG. 2 is a frame format diagram of a transmission signal according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a complex correlator in the first embodiment of the present invention.

FIG. 4 is a block diagram of an envelope calculation circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram of an address calculation circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a frequency offset detection device according to a second embodiment of the present invention.

FIG. 7 is a block diagram of a power calculation circuit according to a second embodiment of the present invention.

FIG. 8 is a block diagram of an address calculation circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram of a frequency offset detection device according to a third embodiment of the present invention.

FIG. 10 is a block diagram of an envelope / frequency offset conversion circuit according to a third embodiment of the present invention.

FIG. 11 is a block diagram of a frequency offset detection device according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram of a power calculation circuit according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram of a power / frequency offset conversion circuit according to a fourth embodiment of the present invention.

FIG. 14 is a block diagram of a frequency offset detection device in a conventional example.

[Explanation of symbols]

 101 Limiter Amplifier 102 Quadrature Detection Circuit 103 Low Pass Filter 104 Low Pass Filter 105 A / D Converter 106 A / D Converter 107 First Memory 108 Second Memory 109 Complex Correlator 110 Envelope Calculation Circuit 111 Address Calculation Circuit 112 Second 3 memory 601 limiter amplifier 602 quadrature detection circuit 603 low-pass filter 604 low-pass filter 605 A / D converter 606 A / D converter 607 first memory 608 second memory 609 complex correlator 610 power calculation circuit 611 address calculation circuit 612 Third memory 901 Limiter amplifier 902 Quadrature detection circuit 903 Low-pass filter 904 Low-pass filter 905 A / D converter 906 A / D converter 907 First memory 908 Second memory 909 Multiple Correlator 910 Envelope calculation circuit 911 Envelope / frequency offset conversion circuit 1101 Limiter amplifier 1102 Quadrature detection circuit 1103 Low pass filter 1104 Low pass filter 1105 A / D converter 1106 A / D converter 1107 First memory 1108 Second memory 1109 Complex correlator 1110 Power calculation circuit 1111 Power / frequency offset conversion circuit

Claims (4)

[Claims] 1. A receiver for inputting a signal obtained by quadrature detection of a reception signal amplified by a constant envelope type amplifier, in the case of adding a known symbol to the transmission signal and transmitting the received signal, the reception signal corresponding to the known signal. , A second memory for storing a known transmission signal, a complex correlator for obtaining a complex correlation between the signal of the first memory and the signal of the second memory, and a correlation result An envelope calculating circuit for obtaining an envelope, an address calculating circuit for performing an address calculation for obtaining a frequency offset by looking up a table from the obtained envelope value, and a frequency offset value for an address calculated from the envelope value are stored. A frequency offset detection device including a third memory. 2. A receiver for inputting a signal obtained by quadrature detection of a reception signal amplified by using a constant envelope type amplifier, in the case of adding a known symbol to the transmission signal and transmitting the received signal, the reception signal corresponding to the known signal. , A second memory for storing a known transmission signal, a complex correlator for obtaining a complex correlation between the signal of the first memory and the signal of the second memory, and a correlation result A power calculation circuit for obtaining power, an address calculation circuit for performing address calculation for obtaining a frequency offset by looking up a table from the obtained power value, and a third memory for storing a frequency offset value for the address calculated from the power value. And a frequency offset detecting device. 3. A receiver for inputting a signal obtained by orthogonally detecting a reception signal amplified by using a constant envelope type amplifier, when a known symbol is added to the transmission signal for transmission, the reception signal corresponding to the known signal is received. , A second memory for storing a known transmission signal, a complex correlator for obtaining a complex correlation between the signal of the first memory and the signal of the second memory, and a correlation result A frequency offset detection device comprising an envelope calculation circuit for obtaining an envelope and an envelope / frequency offset conversion circuit for obtaining a frequency offset from an obtained envelope value by an approximate expression. 4. A receiver for inputting a signal obtained by quadrature detection of a reception signal amplified by using a constant envelope type amplifier, in the case of adding a known symbol to the transmission signal and transmitting the received signal, the reception signal corresponding to the known signal. , A second memory for storing a known transmission signal, a complex correlator for obtaining a complex correlation between the signal of the first memory and the signal of the second memory, and a correlation result A frequency offset detection device comprising a power calculation circuit for obtaining power and a power / frequency offset conversion circuit for obtaining a frequency offset from the obtained power value by an approximate expression.