JPH08322043A - Video encoder/decoder - Google Patents

Abstract

PURPOSE: To perform AV synchronization control with high accuracy regardless of the execution/non-execution of frame rate conversion by checking AV synchronization by a synchronization check timing signal generated in replying to a system clock. CONSTITUTION: A video timing control part 3 generates a display timing signal TH replying to the supply of a video synchronizing signal Y, and supplies it to a picture code part 6, and also, generates a decode timing signal TD, and supplies it to a decode control part 4 and a frame conversion control part 2A. The check signal generation circuit 20 of the frame conversion control part 2A generates a synchronization check timing signal TC representing a decoding timing in the case that no frame conversion is performed according to the frame rate of video code data DV in replying to the supply of the system clock SC, and supplies it to an AV synchronization control part 1A. The check circuit 11 of the AV synchronization control part 1A checks the AV synchronization in replying to the supply of the synchronization check timing signal TC after a decoding start timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video code decoding apparatus, and more particularly to a video code decoding apparatus for decoding video data encoded according to the MPEG standard in synchronization with audio data.

[0002]

2. Description of the Related Art ISO / IEC, JTC1 / are used as interframe predictive coding systems for video signals of televisions and the like.
MPEG (Movi) standardized by SC2 / WG8
ngPicture Expert Group) is known. Among these standards is MPEG1 which defines a video code data decoder. In addition, audio coding / decoding in which subband coding is used as an audio signal coding method for adding audio to an image to reduce the information amount of the audio signal and to transmit or store audio data (audio coded data) MP for technology
There is an EG audio standard. Furthermore, as a multiplexing method of these video code data and audio code data,
There is an MPEG system standard.

The MPEG system standard uses a packet multiplexing system. In this method, a video code and an audio code are divided into bit streams of appropriate lengths, and additional information for identifying video data and audio data is added to the beginning of each to generate a video packet and an audio packet, respectively. Then, the video code and the audio code are multiplexed by appropriately switching these video packets and audio packets.

In the decoding process, an audio code and a video code are separated, and an audio code is decoded by an audio code decoding device to output an audio signal. The video code is decoded by the video code decoding device and a video signal is output. At this time, it is necessary to perform synchronization control in order to synchronize the outputs of the audio signal and the video signal.

According to the MPEG system standard, in order to synchronize an audio signal and a video signal, stamp information indicating output timing and decoding timing of the data is added as additional information of the packet.

The time stamp specifies the timing for a decoding unit called an access unit. This access unit is a unit of decoding reproduction called one picture for video and one audio frame for audio.

These time stamps are added to the head portion of the packet containing the head of the access unit and specify the output timing of the access unit. When there are a plurality of access units at the beginning in the packet, only the time stamp corresponding to the first access unit is added.

In the AV synchronization control, the video and audio access units are controlled to be output when the time reference timer STC (system time clock) and the corresponding time stamp of the access unit substantially match. To do.

STC is an S code multiplexed on a system code.
The value is set and calibrated to a value intended by the encoder by CR (system time reference value), and counted up at regular intervals.

Referring to FIG. 4, which shows a block diagram of a conventional video coding / decoding apparatus capable of AV synchronization control and frame rate conversion, the conventional video coding / decoding apparatus is
An AV synchronization control unit 1 having a system time management function and an AV synchronization check function, and a decoding control unit 4 for transmitting a picture repeat request signal RP or a picture skip request signal RS in response to the supply of a decode timing signal TD.
In response to the supply of the video synchronization signal SY, the video timing generation unit 3 for generating the display timing signal TH and the decode timing signal TD, and the supply of the decode timing signal TD. During normal decoding, the decoding control section 4 that supplies the decoding start signal DS at the same timing to the picture decoding section 6 and the input video code data DV are temporarily stored and the video decoding data 6 are sequentially supplied to the picture decoding section 6. The video code buffer 5 for decoding, and the video code data DV for one picture in response to the supply of the decoding start signal DS, and the video code data for one picture without decoding in response to the supply of the picture skip signal PS. And a picture decoding unit 6 for skipping.

Next, referring to FIG. 4, the operation of the conventional video code decoding apparatus will be described. First, the video timing control unit 3 decodes the display timing signal TH in response to the supply of the video synchronization signal SY. Timing signal T
D and D, respectively, and supplies the signal TH to the picture decoding unit 6 and the signal TD to the frame rate conversion control unit 2. The frame rate conversion control unit 2 responds to the supply of the decode timing signal by the video code data D.
V and the output video signal V have different frame rates, in order to convert the frame rates so that they match each other, a picture repeat request signal PR is generated for every fixed number of pictures.
Alternatively, the picture skip request signal RS is output to the decoding control unit 4. The system time management function of the AV synchronization control unit 1 counts up the system time in response to the supply of the system clock SC, and sets / calibrates it in response to the system clock reference parameter CR which is sometimes input. Next, in the AV synchronization check function, the correspondence between the time stamp and its corresponding picture is managed, and the system time and the video time at the decoding start timing of the corresponding picture being processed by the picture decoding unit 6 in response to the supply of the decoding start signal DS. It is determined whether the time difference from the stamp is within a predetermined range. If the above time difference exceeds the above range and the system time is larger, it indicates that the picture decoding process is too late. Therefore, the picture skip request signal R
If S is smaller than the system time, it indicates that the picture decoding process is too early. Therefore, the picture repeat request signal PR is output to each decoding control unit 4.

In response to the supply of the decode timing signal TD, the decode control section 4 sends the decode start signal DS at the same timing during normal decoding, and the picture decode section 6
Output to. Further, when the picture skip request signal RS and the picture repeat request signal PR are input from the AV synchronization control unit 1 and the frame rate conversion control unit 2, respectively, the skip / repeat of the picture is executed according to these signals RS and PR. The picture skip outputs the picture skip signal PS to the picture decoding unit 6,
This is performed by controlling the picture decoding unit 6 to skip the video code data DV for one picture. The picture repeat is performed by ignoring one pulse of the decode timing signal DT and not outputting the corresponding decode start signal DS, so that the decoding process is controlled not to be performed for one picture period. Video code buffer 5
Is the video code data DV that has temporarily stored the input video code data DV and has been sequentially read by the picture decoding unit 6.
Supply. In response to the supply of the decoding start signal DS, the picture decoding unit 6 decodes the video code data DV for one picture, and when the picture skip signal PS is supplied, the video code data for one picture as described above. Skip without decoding. In addition, the data of the restored picture is output as the video signal V in response to the supply of the display timing signal TH.

Next, the generation of each of the picture repeat request signal PR and the picture skip request signal RS in the frame rate conversion control unit 2 will be described. For convenience of explanation, as an example, a case where a video code of 25 frames / sec is displayed at 30 frames / sec for picture repeat signal generation, and 30 for picture skip signal generation.
A case where a video code of frames / second is displayed at 25 frames / second will be described as an example.

First, the video code of 25 frames / second is set to 3
When displaying at 0 frames / sec, 6 pictures may be displayed by repeating 1 picture for each video code data for 5 pictures, so that the picture repeat request signal PR is provided for every 6 decoding timing signals. Control to output.

In addition, the video code of 30 frames / second is 2
When displaying at 5 frames / second, the video code data for one picture is discarded without decoding for every display period for five pictures, so that the video code data for six pictures is consumed during the display period for five pictures. Therefore, the picture skip request signal RS is controlled to be output every five decode timing signals.

In the conventional video encoding / decoding apparatus described above, the video time stamp and the system time are compared in the AV synchronization control unit at the decoding start timing of the time stamp corresponding picture. Since the decoding timing of the corresponding picture is different from the decoding timing when the original frame rate conversion is not performed, there is a possibility that an error of half a picture period or more occurs in the AV synchronization check timing. Therefore, in the conventional video encoding / decoding device, when the frame rate conversion is performed, the allowable range of the difference between the system time and the time stamp at the time of AV synchronization determination is widened including the above-mentioned error. AV at the wrong timing
It was to prevent the picture skip / repeat caused by the synchronization check.

[0017]

The above-described conventional video coding / decoding apparatus, at the time of frame rate conversion,
There is a possibility that an error of half a picture period or more will occur in the AV synchronization check timing, and in order to prevent picture skip / repeat that occurs in the AV synchronization check at the wrong timing due to the error, the system time and the time stamp are set. It is necessary to widen the allowable range of the difference by a half picture period, and there is a drawback that highly accurate AV synchronization control cannot be performed.

[0018]

A video code decoding apparatus according to the present invention temporarily outputs video code data, and video timing generating means for outputting a display timing signal and a decode timing signal in response to the supply of a video synchronization signal. A video code buffer means for holding, a video decoding means for decoding the video code data read from the video code buffer and outputting a video signal in response to the supply of the display timing signal for each picture, and for supplying a system clock. In response to managing the system time, if the decoding start timing of the video code data is earlier than a video time stamp supplied in synchronization with the video code data by a predetermined time difference range, a repeat request of the picture is requested. If the signal is slow, skip request for the picture A by outputting No. respectively
One of the repeat request signal and the skip request signal when the first frame rate of the video code data is different from the second frame rate of the video output signal It is supplied from each of the frame rate conversion control means for selectively outputting and controlling the required video code data amount to match the first frame rate, the AV synchronization control means and the frame rate conversion control means. In response to the repeat request signal and the skip request signal, either one of a decoding start signal for one picture and a skip signal for instructing skip of the code for one picture is selectively output to the picture decoding unit. In the video code decoding device including decoding control means, the frame rate conversion control Each stage includes a check signal generation circuit for generating a synchronous check timing signal indicating the decode timing when the frame rate conversion is not performed in response to the supply of the system clock, and the AV synchronization control means is provided after the decode start timing. It comprises a check circuit for checking the AV synchronization in response to the supply of the synchronization check timing signal.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the embodiment of this invention shown in FIG. The video coding / decoding apparatus of the present invention has a video timing generation unit 3, a video code buffer 5, and a decoding control unit 4 which are common to the conventional ones.
In addition to the picture decoding unit 6, the AV synchronization control unit 1 has the same system time management function as the conventional one, and in addition to the AV signal in response to the supply of the synchronization check timing signal TC.
Instead of the AV synchronization control unit 1A having an AV synchronization determination function including the check circuit 11 for performing the synchronization check, and the frame rate conversion control unit 2 in addition to the conventional frame conversion function, in response to the supply of the system clock SC. A frame rate conversion control unit 2A including a check signal generation circuit 20 for generating a synchronous check timing signal TC indicating the original decoding timing when frame conversion is not performed.
With.

Next, the operation of the present embodiment will be described with reference to FIG. 1. As in the conventional case, the video timing control section 3 generates the display timing signal TH in response to the supply of the video synchronization signal SY, and outputs the picture. The dead timing signal TD is generated and supplied to the decoding control unit 4 and the frame rate conversion unit 2A while being supplied to the decoding unit 6.

In response to the supply of the decode timing signal TD, the frame rate conversion control unit 2A responds to the supply of the decode timing signal TD and, as in the conventional case, the picture corresponding to the case where the frame rate of the video code data DV and the frame rate of the output video signal V are different. Repeat request signal PR / picture skip signal RS
Is output to the decoding control unit 4. In addition, the check signal generation circuit 20 generates the synchronization check timing signal TC indicating the original decoding timing when the frame rate conversion is not performed according to the frame rate of the video code data DV in response to the supply of the system clock SC, and A
It is supplied to the V synchronization control unit 1A.

The AV synchronization control unit 1A has the same system time management as the conventional one, and the check circuit 1 in addition to the contents of the conventional determination.
A using the synchronous check timing signal TC at 1
V synchronization determination is performed. That is, in the AV synchronization check, the correspondence between the time stamp and its corresponding picture is managed, and after the decoding process is started in response to the supply of the decoding start signal DS, the input timing of the synchronization check timing signal TC supplied by the check circuit 11 is determined. It is determined whether the time difference between the system time and the video time stamp is within a predetermined range. As in the conventional case, the picture skip request signal RS or the picture repeat request signal PR is output to the decoding control unit 4 in correspondence with the magnitude of the system time stamp when the time difference exceeds the range.

Since the operation of the decoding control section 4 and the subsequent steps is the same as the conventional one, the description thereof will be omitted.

Next, referring to FIG. 2, which shows a block diagram of the configuration of the check signal generating circuit 20 of the frame rate conversion control unit 2A, the check signal generating circuit 20 counts up in response to the supply of the decode timing signal TD. Then, a picture counter 21 that outputs a count value N and a 0 detection circuit 22 that outputs "H" when the count value N is 0
And an AND circuit 23 that outputs a logical product value of the signal TD and the output of the 0 detection circuit 22, and a count value NP for one frame period that corresponds to 1/25 second and counts up in response to the supply of the system clock signal SC. , A picture period counter 24 that outputs a coincidence detection circuit 25 that detects the coincidence between the count value NP and the one frame period value F and outputs a coincidence pulse signal, and a logical sum value of the logical product value and the coincidence pulse signal. An OR circuit 26 that outputs the synchronization check timing signal TC is provided.

The operation of this circuit will be described with reference to FIG. 2 and FIG. 3 which is a time chart showing the operation.
First, in FIG. 3A, a video code of 25 frames / sec is set to 3
The display value is 0 frame / second, and the count value N of the picture counter 21 is the decode timing signal TD.
Counts up in response to the supply of
Is controlled to return to 0 after. The 0 detection circuit 22 is
When the count value N is 0, "H" is output and the AND circuit 23
Generates a logical product of "H" of this output signal and the decode synchronization signal TD. The output logical product value of the AND circuit 23 is supplied to the OR circuit 26, and the OR circuit 26 generates the synchronization check timing signal TC. Further, the count value NP of the picture period counter 24 is counted up in response to the supply of the system clock SC, and is 1 corresponding to 1/25 second.
It returns to 0 after the frame period value. In this case, since the system clock is assumed to be 90 KHz, the one frame period value is 3599. The coincidence detection circuit 25 generates a coincidence pulse signal when the count value NP coincides with the one frame period value (3599). This coincidence pulse signal is O
The OR circuit 26 is supplied to the R circuit 26 and generates the synchronization check timing signal TC. In FIG. 3A, P0 to P6 added to the respective pulses of the decode timing signal TD and the synchronization check timing signal TC indicate pictures corresponding to the pulse signal.

Next, FIG. 3B shows a case where a video code of 30 frames / sec is displayed at 25 frames / sec. The difference from the case of FIG. 3A is that the count value N of the picture counter 21 is N. Becomes 0 after 4 and the 1-frame period value F is 2999, and otherwise the same operation is performed to generate the synchronization check timing signal TC.

As described above, in the video coding / decoding apparatus of this embodiment, even during frame rate conversion,
Since the video time stamp and the system time are compared in the AV synchronization control unit not at the decoding start timing of the picture but at the synchronization check timing signal input timing corresponding to the decoding timing when the frame rate is not converted, the AV synchronization determination is accurately performed.

[0028]

As described above, the video code decoding apparatus of the present invention comprises the check signal generating circuit for generating the synchronous check timing signal indicating the decoding timing when the frame rate conversion control means does not convert the frame rate. The AV synchronization control means responds to the supply of the synchronization check timing signal after the decoding start timing by the AV synchronization control means.
Since it has a check circuit for checking synchronization, AV
The synchronization control unit compares the picture time stamp with the system time in accordance with the synchronization check timing signal, so that the AV synchronization check can be accurately performed regardless of whether the frame rate conversion is executed or not.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video encoding / decoding apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of a check signal generation circuit of FIG.

FIG. 3 is a time chart showing the operation of the check signal generation circuit of FIG.

FIG. 4 is a block diagram showing an example of a conventional video code decoding apparatus.

[Explanation of symbols]

 1, 1A AV synchronization control unit 2, 2A frame rate conversion control unit 3 video timing generation unit 4 output code control unit 5 video code buffer 6 picture decoding unit 20 check signal generation circuit 11 check circuit 21 picture counter 22 0 detection circuit 23 AND Circuit 24 Picture period counter 25 Match detection circuit 26 OR circuit

Claims (2)

[Claims] 1. A video timing generation means for outputting a display timing signal and a decode timing signal in response to the supply of a video synchronization signal, a video code buffer means for temporarily holding video code data, and the display timing for each picture. Video decoding means for decoding the video code data read out from the video code buffer in response to the supply of a signal and outputting a video signal; and managing the system time in response to the supply of a system clock and storing the video code data. If the decoding start timing is earlier than the video time stamp supplied in synchronization with the video code data by a predetermined time difference range, the repeat request signal of the picture is output, and if it is late, the skip request signal of the picture is output. By doing AV synchronization And an AV synchronization control unit that performs a clock, and selectively selects one of the repeat request signal and the skip request signal when the first frame rate of the video code data is different from the second frame rate of the video output signal. Frame rate conversion control means for controlling the output and required video code data amount so as to match the first frame rate, and the repeat request supplied from each of the AV synchronization control means and the frame rate conversion control means. A decoding control means for selectively outputting to the picture decoding section either one of a decoding start signal for one picture and a skip signal for instructing skipping of the code for one picture in response to the signal and the skip request signal. In the video coding / decoding apparatus including: A check signal generating circuit for generating a synchronous check timing signal indicating the decode timing when the frame rate conversion is not performed in response to the supply of the system clock, wherein the AV synchronization control means performs the synchronous check timing after the decode start timing. A video encoding / decoding device comprising a check circuit for performing the AV synchronization check in response to the supply of a signal. 2. A first counter, wherein the check signal generation circuit counts up and outputs a first count value in response to the supply of the decode timing signal, and a first counter of the supplied first count value. A 0 detection circuit which outputs a 0 detection signal in response to 0, a first logic circuit which outputs a logical product value of the decode timing signal and the 0 detection signal, and in response to supply of the system clock signal A second counter that counts up and outputs a second count value; a match detection circuit that detects a match between the second count value and a frame set value corresponding to one frame period and outputs a match pulse signal; 2. A video circuit according to claim 1, further comprising a second logic circuit which outputs a logical sum value of a logical product value and a coincidence pulse signal as the synchronization check timing signal. No. decoding apparatus.