JPH08321622A - Method of manufacturing metallic wiring - Google Patents

Abstract

PURPOSE: To facilitate the protection of separated surface of aluminum wiring cut off by separation patterning and the formation of the separated surface protecting film after the formation of anode oxide films. CONSTITUTION: After the formation of anodie oxide films 111 and 112, an alumina film is formed on a separated surface for protecting the separated surface of an aluminum wiring cut off by separation patterning. At this time, the oxide film formation on the separated surface and the substrate cleaning can be performed in the same step by using an oxidizing agent, especially, ozone- dissolved aqueous solution thereby enabling the TFT substrate manufacturing step to be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention disclosed in this specification relates to a semiconductor device formed on an insulating substrate such as glass or various substrates such as a thin film transistor (TFT) or a thin film diode (TFD), or those devices. Among the applied thin film integrated circuits, especially active liquid crystal display device manufacturing methods,
The present invention relates to a method for forming a metal film formed on a wiring.

[0002]

2. Description of the Related Art A liquid crystal display device is widely used as a light and thin display device for a TV, a desktop type or a portable type information processing device, and the like. In particular, an active matrix liquid crystal display device in which a thin film transistor (hereinafter referred to as a TFT) or the like is formed in each display pixel by applying a manufacturing technique of an integrated circuit such as an IC or an LSI can display a favorable image, Moreover, since it is lightweight and compact, it is expected as a next-generation display medium device.

An active matrix type liquid crystal display device usually has a structure in which a liquid crystal material is sandwiched between a pair of glass substrates and a TFT is formed on the side of one of the glass substrates facing the liquid crystal. In the step of forming the TFT, since it is necessary to form the metal wiring in multiple layers, an insulating film (called an interlayer insulating film) is generally formed between the upper and lower wirings.

It is desirable to use aluminum for the wiring. This is because its resistance is low. However, when wiring is formed using aluminum, TF
Because of the heat that is inevitably applied in the manufacturing process of T,
There is a problem that hillocks and whiskers will occur.

Hillocks and whiskers are phenomena in which the aluminum component grows more by heating (generally, heating at 400 ° C. or more), and protrusion-like swelling or spiny growth is observed.

Since the growth distance of these hillocks and whiskers reaches several μm, a short circuit between adjacent wirings and a short circuit between vertically spaced wirings are caused.

As a means for solving this problem, there is a means for forming an oxide film on the surface of aluminum wiring by utilizing a method called anodic oxidation. This is generally done by using an ethylene glycol solution containing tartaric acid neutralized with ammonia water as the electrolytic solution, connecting the aluminum wiring to be oxidized in this solution to the anode, and applying a current to the anode to form the aluminum wiring. This is a technique for forming an anodic oxide film on top. Incidentally, platinum is mainly used as the cathode.

[0008]

Generally, in order to perform anodization on all wirings at once, the wiring pattern is not formed into an independent form but all are connected by one line, and the anodization process is performed. . By doing so, the anodic oxidation can be done only once. However, in this state, all the wires are connected, so the wires are cut (cut) at appropriate points.
There is a need to. Generally, there are many places of this division.

However, when cutting is performed, a surface to which aluminum is directly exposed appears. Although the source / drain regions and the interlayer insulating film are formed after the dividing step, heating is inevitably performed in these steps. For example, in order to form the source / drain regions, implantation of impurity ions and subsequent activation treatment are required, but heating at a temperature of 400 ° C. or higher is performed during the ion implantation. In addition, a temperature of 500 ° C. or higher is required when heat treatment is used for activation of the source / drain regions, and hillocks and whiskers are sufficient even when laser light irradiation is performed. Energy will be supplied. Further, heating is also required in forming an interlayer insulating film (generally a silicon oxide film is used). Further, heating is inevitably performed even when the resist is removed by ashing in various patterning steps, and hillocks and whiskers are generated.

As described above, since heating is performed after the cutting step, hillocks and whiskers are generated on the exposed surface of the aluminum of the cross section. If the area of the divided portion is made sufficiently large, the distance of the divided cross section facing each other can be made sufficiently large, and the divided portion will not short-circuit due to the occurrence of hillocks or whiskers. However, the circuit pattern tends to be further miniaturized in the future, and it is desired to make the area of the divided portion as small as possible. In such a situation, the problem of short-circuiting due to the occurrence of hillocks or whiskers at the dividing point becomes apparent.

An object of the invention disclosed in this specification is to provide a technique for solving such a problem.

[0012]

DISCLOSURE OF THE INVENTION One of the inventions disclosed in the present specification is a wiring made of aluminum or a material containing aluminum as a main component, or a wiring made of a material that can be anodized and having a front surface or a part thereof. Form an anodic oxide film on the surface,
Furthermore, when cleaning the substrate after the dividing step, by using a solution in which a highly oxidizing material is dissolved in pure water, the surface of the wiring where the oxide film is not formed is oxidized in the same step as the cleaning of the substrate. It is characterized in that a film is formed.

With this structure, the surface of the wiring can be covered with an oxide film, and hillocks and whiskers can be prevented from occurring. In addition, the method using a solution in which a material having a strong oxidizing power is dissolved in pure water can be performed without increasing the number of steps, and therefore does not cause an increase in cost in manufacturing a TFT.

Ozone can be used as the material having a strong oxidizing power. Further, as a method for dissolving ozone in pure water, a bubble method, a droplet method, a packed tower method and the like can be mentioned. From the viewpoint of effective use of gas, the bubble method is preferable. Further, even in the bubble type, the method of using an air diffusing tube made of a gas permeable membrane is particularly preferable because it has high dissolution efficiency. At this time, it is desirable that the ozone concentration of the solution is 6 to 16 mg / l.

Cleaning of the substrate (also serves as oxidation of the wiring)
There are a method of dropping the above solution on a substrate and using a spinner, and a method of storing the above solution in a container or the like and performing it in a batch system. Considering the controllability of the oxide film quality, it is necessary that the solution is always clean. From this point, the method using a spinner is desirable. When using a spinner, the dropping amount is 1-2 l / min, and the rotation speed is 100-4000 rp.
It should be m. In terms of washing, a higher rotation speed is preferable because contaminants are easily removed.

[0016]

Function: The oxidizing agent dissolved in water reacts with the metal formed on the substrate to form the metal oxide film on the metal surface. In particular, when ozone is used, a metal oxide film is easily formed because ozone is decomposed into oxygen while forming a strong oxidant in the process of self-decomposition of ozone.

Further, since the oxide film is formed in the cleaning step, the number of steps can be increased as compared with the conventional technique.

By forming the oxide film using such an oxidizing agent after the dividing step performed after forming the anodic oxide film, the entire surface can be covered with the oxide film. Then, the generation of hillocks and whiskers can be suppressed.

[0019]

【Example】

[Example 1] An example in which a TFT substrate is manufactured by using the present invention will be described with reference to FIGS. 1, 2, 3, and 4. This embodiment relates to a liquid crystal display device using a monolithic type active matrix circuit having a structure as shown in FIG. FIGS. 1 and 3 mainly show the vicinity of the boundary between the gate driver and the gate line and the pixel TFT portion.
As shown in Figure 2, the final stage of the gate driver is
A CMOS inverter is provided as a buffer.

A general view of the active matrix circuit of this embodiment is as shown in FIG. Hereinafter, a manufacturing process for obtaining the monolithic active matrix circuit of this embodiment will be described with reference to FIGS.

First, a substrate (Corning # 7059 glass substrate, 100 mm × 100 mm × 1.1 mmt) 101
Is thermally annealed at 640 ° C. for 4 hours in order to reduce heat shrinkage during the manufacturing process. The substrate is heated to 130 by this thermal annealing.
Shrinks about 0 ppm.

Next, a silicon oxide film having a thickness of 1000 to 3000 Å is formed as a base oxide film 102 on the substrate 101.
As a method of forming this oxide film, a sputtering method in an oxygen atmosphere or a plasma CVD method may be used.

After that, an amorphous or crystalline silicon film is formed in a thickness of 300 to 1500 Å, preferably 500 to 1000 Å by plasma CVD or LPCVD. In order to obtain a crystalline silicon film, a method of irradiating a laser or light having an intensity equivalent to that of the amorphous silicon film (optical annealing) may be adopted. Alternatively, a crystalline silicon film may be obtained by performing thermal annealing at a temperature of 500 ° C. or higher for a long time. In addition, when crystallizing by thermal annealing, Japanese Patent Application Laid-Open No. 6-24410 was used.
3, 6-244104, an element (catalyst element) that promotes crystallization of silicon such as nickel may be added.

Next, the silicon film is etched to form the TFT active layers 103 and 104 of the peripheral driving circuit and the TFT active layer 105 of the matrix circuit. Further, a gate insulating film 106 of silicon oxide having a thickness of 500 to 2000 Å is formed by a sputtering method in an oxygen atmosphere. A plasma CVD method may be used as a method for forming the gate insulating film.

In the structure shown in this embodiment, the gate insulating film preferably has a sufficiently high breakdown voltage. This is because a high electric field is applied between the gate electrode and the silicon active layer during the anodic oxidation process. Therefore, the plasma CV
When the gate insulating film is formed by the silicon oxide film obtained by the D method, the source gases are dinitrogen monoxide (N ₂ O) or oxygen (O ₂ ) and monsilane (SiH).
It is preferable to use ₄ ). (Fig. 1 (A))

Thereafter, a film (containing 0.1 to 0.5% by weight of scandium) containing aluminum as a main component and having a thickness of 2000 Å to 5 μm, preferably 2000 to 6000 Å is formed on the entire surface of the substrate by the sputtering method. Then, this is etched to form gate electrodes or gate lines 107, 108, 109 (109 '), 110 (11
0 ′) and the wiring 129 for anodic oxidation are formed. (Fig. 1 (B), Fig. 3 (A))

In this etching process, the gate line 1
All of 09 (109 ') are connected to the wiring 129 for anodic oxidation. On the other hand, the gate electrode 10 of the peripheral logic circuit
7 and 108 are configured to be electrically insulated from the wiring (feed line) 129 for anodic oxidation. (FIG. 1 (B), FIG.
(A))

Then, the substrate is placed in an electrolytic solution, and a current is passed through the anodizing wiring to form the gate line 109 (109 '),
And the gate electrode 110 (110 ') is anodized. At this time, as the electrolytic solution, an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia is used.

In the anodizing step, as shown in FIG. 4 (B), the current is supplied by sandwiching the anodizing wiring 129 with a feeding clip such as a crocodile clip. As a result, the wiring 129 for anodic oxidation (FIG. 3A, FIG. 4A)
(See FIG. 1C), anodic oxide films 111 and 112 (described in FIG. 1C) are obtained on the top and side surfaces of the gate line 109 (109 ′) and the gate electrode 110 (110 ′).
In this example, a voltage of 120 V was applied and an anodic oxide film was grown to a thickness of 1700Å.

Thus, the anodic oxide film obtained by anodic oxidation in a substantially neutral solution is dense and hard and has a high breakdown voltage.
The breakdown voltage is 70% or more of the maximum voltage applied during anodic oxidation. Such an anodized film is called a barrier type anodized film. (Fig. 1 (C))

Next, a resist is formed so that only the boundary between the gate line and the anodic oxidation wiring 129 can be etched, and the etching is divided by an etchant in which hydrofluoric acid, ammonium fluoride and pure water are mixed in an appropriate ratio. . After etching, the groove 130 is formed and the gate line and the anodic oxidation wiring 129 are cut. This step is a dividing step after anodizing. (FIG. 3 (B))

After that, the resist formed on the substrate is stripped in a commercially available stripping solution. Next, the substrate is washed. This step also serves as a step of forming an oxide film on the dividing surface where the material containing aluminum as a main component is exposed in the dividing step from the linear shape.

Here, the concentration of the cleaning liquid is 14 mg /
An ozone aqueous solution of 1 is dropped on the substrate and washed with a spinner. Flow rate is 1 l / min, spinner speed is 10
00 rpm. As a result, an oxide film is formed on the cross section of the gate electrode which is exposed after the dividing etching process. Here, the film thickness is set to 500Å. The film thickness can be controlled by controlling the concentration of the solution and the time during which the surface on which the oxide film is formed is in contact with the solution. The difference between the anodized film and this oxide film can be easily determined by measuring impurities in the film. That is, the anodic oxide film contains many elements contained in the electrolytic solution, but the oxide film using ozone water does not contain such elements.

Then, by ion doping, impurities are self-alignedly implanted into the island-shaped silicon film of each TFT by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) as a mask. At this time, phosphorus is first injected into the entire surface using phosphine (PH ₃ ) as a doping gas, and then only island regions 103 in the figure are covered with a photoresist, and diborane (B ₂ H ₆ ) is used as a doping gas. Boron is implanted into the island regions 104 and 105. The dose is 4 × 10 ¹⁴ to 4 × 10 ¹⁵ atoms / c for phosphorus.
m ² and boron are 1 to 8 × 10 ¹⁵ atoms / cm ^2, and the dose of boron is set to exceed that of phosphorus. As a result, N-type regions 113 and P-type regions 114 and 115 are formed.
(Fig. 1 (D))

Thereafter, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is irradiated to improve the crystallinity of the portion where the crystallinity is deteriorated by introducing the impurity region. At the same time, the implanted impurities are activated.

The energy density of the laser is 200-40
0 mJ / cm2, preferably 250-300 mJ / cm
Set to 2. As a result, the N-type and P-type regions are activated. The sheet resistance of these areas is 200-800Ω / □
Becomes Next, thermal activation is performed at 450 ° C. for 2 hours under a nitrogen atmosphere.

When the source / drain regions are activated, it is possible to suppress the generation of hillocks or whiskers in the divided portion of the gate electrode. this is,
This is because the oxide film is formed on the cross section of the gate electrode in the previous cleaning step.

After that, an interlayer insulating film 116 is formed on the entire surface.
A silicon nitride film is formed to a thickness of 500Å by the plasma CVD method. Further, a silicon oxide film is formed to a thickness of 9000Å. In this way, a multilayer film is formed. And
The interlayer insulating film 116 is etched by a wet etching method. In this way, contact holes 117, 118, and 119 are formed in the N-type region and the P-type region. At the same time, a hole 120 is formed in the gate electrode / gate line. However, at this stage, the anodic oxide 111 becomes a barrier, the etching is interrupted, and the gate line is not reached. (Fig. 1 (E), Fig. 3 (C))

After that, a pattern of contact holes is formed again in the holes 120 formed in the previous step by the photolithography method. Then, etching is performed using an etchant having the same ratio as that used for the above-described divided etching. In this way, the contact hole 121 is formed. (Fig. 1 (F), Fig. 3 (D))

After that, a thickness of 500 is obtained by the sputtering method.
A titanium film of ~ 1000Å is formed, and the thickness is 6000.
Form an aluminum film of ~ 8000Å. The aluminum film contains 2% scandium to prevent hillocks. Next, this is etched using ammonia hydrogen peroxide (hydrogen peroxide: ammonia: water = 5: 2: 2). Further, etching is performed using aluminum mixed acid (phosphoric acid + acetic acid + nitric acid). Thus, the electrodes / wirings 122, 123 of the peripheral circuit,
124 and source line 125, electrode 126 of pixel TFT
To form. The wiring 123 is connected to the gate line 109. (Fig. 1 (G))

Further, a thickness of 500 formed by the sputtering method.
An ITO (indium tin oxide) film of about 1500 Å is etched to form a pixel electrode 127. Finally, a silicon nitride film 128 having a thickness of 1000 to 3000 Å was formed as a passivation film by the plasma CVD method. In this way, the peripheral logic circuit and the active matrix circuit are integrally formed. (Fig. 1 (G))

[Embodiment 2] In this embodiment, the invention disclosed in this specification is utilized to form a circuit (thin film integrated circuit) integrated with a thin film transistor using a crystalline silicon thin film. Here is an example: 5A and 5B show an example of the thin film integrated circuit shown in this embodiment. Shown in (B) is the equivalent circuit of (A). The configuration shown in FIG.
The inverter circuit in which the channel type thin film transistor and the P channel type thin film transistor are configured in a complementary type is arranged in two stages.

The circuit as shown in FIG. 5 is used as an analog buffer circuit which is a part of the peripheral drive circuit of the active matrix type liquid crystal display device as shown in FIG. Figure 5
Shows the basic configuration, but in reality, in FIG.
A thin film integrated circuit is configured by complexly combining various circuits as shown in (1) and other necessary circuits. Also,
It should be noted that the circuits constituting the active matrix type liquid crystal display device are generally formed on a glass substrate as a substrate.

In the circuit shown in FIG. 5, the hatched portion indicated by 11 is the gate wiring (the extended portion constitutes the gate electrode). Also, 13 is 1
The wiring connects the output of the second-stage inverter circuit and the input of the second-stage inverter circuit. The wiring 13 is composed of a second layer wiring formed on an interlayer insulating film (not shown) formed on the gate wiring 11. For convenience, 101 is referred to as a first layer wiring, and 103 is referred to as a second layer wiring.

Generally, the thickness of the interlayer insulating film is 5000 Å or more. Therefore, the gate wirings 11 and 2 which are the first wirings
The wiring 13 which is the wiring of the layer is 50
It means that they are vertically separated from each other with an interval of 00Å or more.

6A and 6B and below show steps of manufacturing the thin film semiconductor circuit shown in FIG. In this embodiment, an example in which a glass substrate is used as the substrate is shown. In addition to the glass substrate, a semiconductor substrate having an insulating film formed on the surface thereof or other materials having an insulating surface can be used.

First, a silicon oxide film is formed as a base film on a glass substrate (not shown in FIG. 6). This silicon oxide film may be formed to a thickness of about 3000 Å by a sputtering method or a plasma CVD method. On top of that, plasma C
An amorphous silicon film (amorphous silicon film) (not shown) is formed by the VD method or the low pressure thermal CVD method. The film thickness of the amorphous silicon film is, eg, 500Å. Then, the amorphous silicon film is crystallized by heat treatment, laser light irradiation, or a combination thereof to obtain a crystalline silicon film.

Next, by patterning the crystalline silicon film, island-shaped regions 201 to 204 to be the active layers of the thin film transistor are formed as shown in FIG. 6 (A). A known photolithography process may be used for patterning.

In the state shown in FIG. 6A, A-
A cross section cut at A ′ is shown in FIG. FIG.
In (A), 401 is a glass substrate, and 402 is a base silicon oxide film formed on the glass substrate.

Next, a silicon oxide film (FIG. 6) is formed as a gate insulating film.
(Not shown) is formed by a plasma CVD method or a sputtering method. The thickness of this silicon oxide film is generally 100.
It may be about 0 to 1500Å.

Next, a film containing aluminum as a main component for forming a gate electrode and a wiring extending from the gate electrode is formed by a sputtering method or an electron beam evaporation method. The film thickness of the film containing aluminum as the main component is, for example, 50
00 Å.

Here, as the material containing aluminum as the main component, a material containing 0.2 wt% of scandium in aluminum is used. This is to suppress the generation of hillocks and whiskers due to heating and laser light irradiation in the subsequent steps. By including a rare earth element in aluminum as described above, the generation of hillocks and whiskers can be suppressed, but it cannot be eliminated. Further, silicon can be used instead of the rare earth element.

After forming a film containing aluminum as a main component on the entire surface, a slit is formed at a portion where hillocks and whiskers are desired to be completely suppressed. This step is performed by partially exposing a region where a slit is to be formed with a resist mask and performing wet etching or dry etching.

In this embodiment, the hatched portion 205 in FIG. 6B is the slit portion. This slit may have a width of about 1 to 30 μm. It should be noted that this dimension may be appropriately selected according to the design rule. Note that a film 206 containing aluminum as a main component exists over the entire surface in a portion where the slit 205 is not formed.

It is necessary to minimize the portion where the slit is formed. This is to suppress the influence of stress generated during anodic oxidation. For example, if the anodic oxidation is performed after forming all the wiring patterns, the fine wiring may be broken or the communication may be poor due to the stress during the anodic oxidation. Therefore, it is preferable to limit the formation of slits for anodic oxidation in the region where the distance between the wirings is narrow and a short circuit is likely to occur due to hillocks or whiskers.

In FIG. 6B, a wiring pattern 207 is obtained by patterning the film 206 containing aluminum as a main component later.
(Of course, no pattern is formed in this state)

As can be seen from FIG. 6B, the slit is formed so that a part of the side surface of the wiring pattern is exposed. This is because the anodic oxide film is selectively formed on a part of the wiring pattern.

In this state, anodization is performed in the electrolytic solution with the film containing aluminum as the main component as the anode. By this anodic oxidation, a dense anodic oxide film of about 600 Å is formed on the surface thereof. Here, as the electrolytic solution, a solution obtained by neutralizing 3% tartaric acid with ammonia was added with 1% ethylene glycol.
Use the one diluted 0 times. The maximum applied voltage for anodic oxidation is 40V. The formed anodic oxide film is Al ₂ O.
_{It has 3} as its main component and is a dense and hard insulating film.

In this anodizing step, the slit 20
An anodic oxide film is also formed inside 5. In this anodizing step, since the film containing aluminum as a main component exists in most of the region, the pattern is deformed due to the generation of stress during the anodization, and is formed due to the voltage drop. Problems such as non-uniformity of the anodic oxide film can be suppressed.

Since the anodic oxide film is not formed especially on the portion where the long wiring is routed, the problem caused by the voltage drop can be suppressed. Further, since the problem of the voltage drop can be suppressed, it becomes possible to finally form a fine pattern.

In the state shown in FIG. 6B, BB '
FIG. 8B shows the state of the cross section cut by. FIG.
In (B), 403 is a silicon oxide film functioning as a gate insulating film, and 404 is a film containing aluminum as a main component which later forms a gate electrode. As shown in FIG. 8B, most of the film 404 containing aluminum as its main component remains, so that the problems of stress generation and voltage drop can be suppressed as described above.

A section taken along line CC 'in FIG. 6B is shown in FIG. 8C. Although not shown in FIG. 6B, the reference numeral 302 in FIG. 8C is an anodized film formed in the anodizing step. And 205 is a slit part.

After the anodic oxidation is completed, patterning is performed on the film containing aluminum as a main component in order to form the wiring in the pattern shown by 207. A required wiring pattern is formed by this patterning. This step also serves as a dividing step.

Thus, as shown in FIG.
Gate wirings denoted by 303 are formed. As shown by 302, an anodic oxide film is selectively formed on the side surface of the gate wiring. An anodic oxide film is formed on the entire upper surface of the gate wiring. In this way, the state is obtained as shown in FIG.

Here, cleaning with ozone water is performed to form an oxide film (aluminum oxide film) not shown on the exposed surface of the gate wiring. The film thickness of this oxide film is 300 Å. The ability of the alumina film to suppress hillocks and whiskers is not as great as that of the anodized film. However, it is possible to suppress the growth of hillocks and whiskers whose growth distance reaches several μm. Therefore, for the time being, an oxide film may be formed by utilizing the above-mentioned oxidation method using ozone water in a region where it is sufficient to suppress the generation of large hillocks and whiskers. In addition, this method of forming an oxide film using ozone water does not have the problem of stress generation as in the anodizing step because the film is less dense.

Next, P (phosphorus) ions are implanted over the entire surface. Next, the regions 202 and 204 are covered with a resist mask, and B ions are implanted. Thus, the active layers 201 and 2
N-type source / drain regions are formed at 03 and 2
P type source / drain regions are formed at 02 and 204.

After completion of the ion implantation, laser light irradiation is carried out to activate the implanted ions and anneal damage to the active layer due to the ion implantation. Thus, N-channel and P-channel thin film transistors are formed. Thus, two sets of P and N type thin film transistors for forming the inverter circuit as shown in FIG. 5B are formed.

In FIG. 7A, 201 and 203 are active layers of N-channel type thin film transistors, and 202 and 204 are active layers of P-channel type thin film transistors.

In the state shown in FIG. 7A, DD ′
A cross section cut by is shown in FIG.

Although the gate wiring is heated at the time of ion implantation or laser light irradiation, no hillocks or whiskers are generated in the portion 302 where the anodized film is formed. On the other hand, even in the portion where the anodic oxide film 302 is not formed, hillocks and whiskers do not occur due to the action of the oxide film formed by ozone water. However, the oxide film formed of ozone water has a lesser ability to suppress hillocks and whiskers than the anodic oxide film. Therefore, it is preferable to use the anodic oxide film as shown in this embodiment in the portion where high reliability is required.

After obtaining the state shown in FIG. 7A, a silicon oxide film is formed as an interlayer insulating film (not shown in FIG. 7).
The gate wirings 301 and 303 are covered with this silicon oxide film. This silicon oxide film is formed by the plasma CVD method,
The film is formed to a thickness of about 6000Å. This silicon oxide film is
It is necessary to form a film by a film forming method with good step coverage.

Next, contact holes are formed to reach the gate wiring and the source / drain regions of the active layer. The contact holes are indicated by, for example, 300 and 304 to 306 in FIG. 7B. Reference numeral 300 is a contact hole that communicates with the drain region of the active layer 201. Further, 304 is the active layer 20.
2 is a contact hole leading to the drain region. Reference numeral 305 is a contact hole that leads to the gate wiring 301. Further, reference numeral 306 is a contact hole communicating with the source region of the active layer 204.

Then, a film containing aluminum as a main component (not shown in FIG. 7) for forming the second-layer wiring is formed on the entire surface. Here, the wirings of the first layer are the gate wirings 301 and 303. Further, by patterning the film containing aluminum as a main component, 307
˜309 to form the second layer wiring.

In FIG. 7B, a part of the wiring on the two-layer surface is shown by 307 to 309. 307 is P
The electrode (wiring) is connected to the source region of the channel thin film transistor. The wiring indicated by 308 is
Through the contact holes indicated by 300 and 304,
The gate wiring 301 is in contact with the drain regions of the upper and lower thin film transistors forming the first-layer inverter circuit at the same time. The wiring indicated by 308 connects the output of the first-stage inverter circuit and the input of the second-stage inverter circuit. 30
The wiring indicated by 9 is a wiring connected to the output of the second-stage inverter circuit.

The wirings indicated by 307 to 309 are wirings connected to the source or drain region of the thin film transistor. The wirings 307 to 309 are formed on an interlayer insulating film (not shown).
The gate wirings denoted by 01 and 303 are vertically separated by an interlayer insulating film.

In the state shown in FIG. 7B, FF '
A cross section cut by is shown in FIG. A cross section taken along line GG 'in FIG. 7B is shown in FIG. 9B. FIG. 9 (A)
In the figure, 404 is an interlayer insulating film made of a silicon oxide film.

307 to 309 which will be the second layer wiring
Hillocks and whiskers do not occur in the wiring indicated by. This is because after the formation of the second-layer wiring, heat treatment or laser light irradiation that causes hillocks or whiskers is not performed.

However, when the heat treatment is performed in a hydrogen atmosphere in order to improve the characteristics of the element after forming the second layer wiring, the oxide film is formed by ozone water before the step, and the second layer wiring is formed. It is necessary to apply to.

In this way, the circuit as shown in FIG. 7B (equivalent to that shown in FIG. 5A) is completed. Figure 7
If the circuit shown in FIG.
It is possible to prevent 01 and 303 from being short-circuited due to the presence of hillocks or whiskers. This is because the anodic oxide film 302 is formed in a portion where the gate wirings 301 and 303 may be short-circuited due to the generation of hillocks or whiskers, and the anodic oxide film serves as a barrier in that portion. , Because hillocks and whiskers do not occur.

As a result, the first-stage inverter and the second-stage inverter can be arranged close to each other. That is, the distance indicated by 501 in FIG. 9B can be shortened. This is important in increasing the degree of integration of integrated circuits.

Note that FIG. 9 (B) is GG ′ of FIG. 7 (B).
It shows a cross section cut by.

Further, the wiring 30 is formed by the anodic oxide film 302 formed on a part of the gate wirings 303 and 301.
It is possible to prevent the gate wirings indicated by 3 and 301 and the second-layer wirings indicated by 307 to 309 from being short-circuited in the vertical direction. This is because the gate wirings indicated by 303 and 301 and
This is because the anodic oxide film is formed on the upper surface and the side surface of the gate wiring in the portion close to the second-layer wiring indicated by 309. That is, in this portion, generation of hillocks and whiskers in the gate wiring portion is suppressed by the anodic oxide film, so that it is possible to prevent contact between the gate wiring and the second layer wiring in this portion. .

For example, when aluminum is used as a material for the gate wiring (gate electrode), impurity ions are implanted for forming source / drain regions and laser light is irradiated for activating the source / drain regions. And during thermal annealing, it will be in an unavoidably heated state. Then, hillocks and whiskers are generated on the side surface of the gate wiring 301. As a result, the gate wiring 301 (first-layer wiring) shown in FIG. 9A and the second-layer wiring 307 extending inside the contact hole 306 often short-circuit themselves. I will end up.

However, when the structure as shown in this embodiment is adopted, the presence of the anodic oxide film 302 results in FIG.
In the cross-section shown in (A), generation of hillocks and whiskers in the gate wiring 301 can be suppressed. Therefore, it is possible to prevent a short circuit between the gate wiring 301 and the second-layer wiring 307. Also, the gate wiring 30
It is difficult to form the contact hole 306 due to the presence of hillocks and whiskers generated in No. 1,
Wiring 307 in contact hole 306 and active layer 203
It is possible to prevent the contact (here, the source region) from becoming defective.

This is also effective in miniaturizing the thin film transistor and achieving integration.

[0086]

The oxidizing agent dissolved in water reacts with the metal formed on the substrate to form this metal oxide film on the metal surface. In particular, when ozone is used, a metal oxide film is easily formed because ozone is decomposed into oxygen while forming a strong oxidant in the process of self-decomposition of ozone. By utilizing this fact, by forming an oxide film, for example, an oxide film can be formed around aluminum or a wiring containing aluminum as its main component, and the occurrence of hillocks or whiskers in the device manufacturing process can be suppressed. can do.

[Brief description of drawings]

1 shows a manufacturing process of Example 1. FIG.

FIG. 2 shows a block diagram of a monolithic active matrix circuit.

3 shows a manufacturing process of Example 1. FIG.

FIG. 4 shows an outline of a monolithic active matrix circuit and an anodic oxidation method.

FIG. 5 illustrates an example of a thin film integrated circuit of an example.

6A to 6C are diagrams showing a manufacturing process of a thin film integrated circuit of an example.

7A to 7C are diagrams showing a manufacturing process of a thin film integrated circuit of an example.

FIG. 8 is a diagram showing a manufacturing process of a thin film integrated circuit of an example.

9A to 9C are diagrams showing a manufacturing process of a thin film integrated circuit of an example.

[Explanation of symbols]

 101 Substrate 102 Base Film 103-105 Active Layer (Silicon) 106 Gate Insulating Film (Silicon Oxide) 107-110 Gate Electrode / Gate Line 111, 112 Anodic Oxide 113-115 N / P Type Region 116 Interlayer Insulator 117-119 Contact hole 120 Hole 121 Contact hole 122 to 126 Metal wiring / electrode 127 Pixel electrode 128 Passivation film 129 Anodizing wiring 130 Dividing portion between anodizing wiring and gate line 11 Gate wiring 13 Second layer wiring 14 Second layer Wirings 201 to 204 Active layer 205 Slits 206 Aluminum-based film 207 Gate wiring patterns 301, 303 Gate wiring 302 Anodic oxide film 300 Contact holes 304 to 306 Contact holes 307 to 309 Second layer wiring 01 glass substrate 402 underlying film (a silicon oxide film) 403 gate insulating film (silicon oxide film) 404 interlayer insulating film (silicon oxide film)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshimitsu Onuma 398 Hase, Atsugi, Kanagawa Prefecture Semiconductor Conductor Research Institute Co., Ltd.

Claims (7)

[Claims] 1. A step of forming an oxide film on a surface of a metal wiring in an anodic oxidation step, a step of dividing the metal wiring at at least one place, and an oxidizing agent on the surface of the metal wiring exposed by the step. And a step of forming an oxide film using a solution containing the metal wiring. 2. A step of forming a metal film, a step of forming a slit in a part of the metal film, and a step of performing anodization to form an anodized film on the surface of the metal film and inside the slit. A step of patterning the metal film to form a metal wiring, a step of dividing the metal wiring at at least one place, and an oxide film formed on the exposed surface of the metal wiring using a solution containing an oxidant And a step of: forming a metal wiring. 3. A method for producing a metal wiring according to claim 1 or 2, wherein radicals generated when the oxidizing agent decomposes participates in the metal oxidation reaction. 4. A method for manufacturing a metal wiring according to claim 1 or 2, wherein ozone is used as an oxidant. 5. A method of manufacturing a metal wiring according to claim 1, wherein aluminum or a material containing aluminum as a main component is used as the anodizable material. 6. A metal wire made of an anodizable material, wherein an anodized film is formed on a part of the surface of the metal wire, and an oxidizer is formed on the other part of the surface of the metal film. A metal wiring, wherein the oxide film used is formed. 7. The metal wiring according to claim 6, wherein aluminum or a material containing aluminum as a main component is used as the anodizable material.