JPH08321562A - Semiconductor device, nonvolatile semiconductor memory, and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a stack gate type memory cell in which the coupling capacity between the floating gate and the control gate can be ensured sufficiently even in the case of fine patterning. CONSTITUTION: An isolation oxide 3 is deposited on a p-type single crystal silicon substrate 2. A control gate 6 comprising an n-type impurity region is formed on the surface of one substrate 2 sectioned by the isolation oxide 3 while an n-type source region 7 and a drain region 8 are formed on the surface of the other substrate 2. A channel region 9 is formed between the regions 7, 8 on the surface of the substrate 2. A part of a floating gate 5 is formed on the channel region 9 through a thermal oxide 4 and another part of the floating gate 5 is formed on the control gate 6 through the thermal oxide 4. A silicon oxide 10 is deposited covering the floating gate 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a non-volatile semiconductor memory device and a method for manufacturing a non-volatile semiconductor memory device, and more particularly to a stacked gate type memory cell and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, FRAM (Ferro-electric Random)
m Access Memory), EPROM (Erasable and Programm)
able Read Only Memory), EEPROM (Elecctrical E)
Non-volatile semiconductor memory devices such as rasable and programmable read only memories) are receiving attention. In EPROM and EEPROM, data is stored by accumulating charges in a floating gate and detecting a change in threshold voltage due to the presence or absence of charges by a control gate. Further, as the EEPROM, there is a flash EEPROM that erases data in the entire chip or in block units.

The stacked gate type is currently the mainstream as a memory cell (memory cell transistor) constituting a flash EEPROM. FIG. 11 is a partial cross-sectional perspective view of a conventional stacked gate type memory cell (stacked gate type transistor) 100.

LOC is formed on the p-type single crystal silicon substrate 101.
An element isolation oxide film 102 having an OS structure is formed. The floating gate 103 is formed so as to be orthogonal to the element isolation oxide film 102.
And the control gate 104 is arranged. A part of the floating gate 103 is formed on the substrate 101 via the gate oxide film 105
The floating gate 103 is disposed above, and the remaining portion of the floating gate 103 is disposed on the element isolation oxide film 102. Control gate 104
Part of ONO (silicon Oxide / silicon Nitride / sili
(con oxide) film is arranged on the floating gate 103 via an insulating film 106, and the rest of the control gate 104 is arranged on the element isolation oxide film 102. Board 10
N type source region 107 and drain region 1 on one surface
08 is formed. A channel region 109 is formed between the regions 107 and 108 on the surface of the substrate 101, and a part of the floating gate 103 is formed on the channel region 109 via a gate oxide film 105. An insulating film 110 is formed on both sides of the floating gate 103. An insulating film 111 is formed so as to cover the control gate 104. Note that the control gate 104 is elongated and the substrate 101
The word lines of the flash EEPROM are configured by being shared by the plurality of floating gates 103 formed above.

Incidentally, the structure and operation of such a stacked gate type memory cell are described in detail in "Flash Memory Technology Handbook" (Science Forum Co., Ltd., published in 1993, pp53-148.).

[0006]

To miniaturize the conventional stacked gate type memory cell 100, the insulating film 106 is used.
It is necessary to improve the quality of the film and make it thinner. By thinning the insulating film 106, even if the stacked gate type memory cell 100 is miniaturized, each gate 103, 10
It is possible to obtain a sufficient coupling capacity between the four. However, when the insulating film 106 is made thin, it is easily broken when a high electric field stress is continuously applied to the insulating film 106. Therefore, when the insulating film 106 is thinned, it is particularly important to improve the quality of the insulating film 106.

However, since the insulating film 106 is made of an ONO film, there is a limit in improving the quality and reducing the film thickness. However, if a silicon oxide film formed by a thermal oxidation method is used for the insulating film 106, the quality can be improved and the film can be easily thinned. However, in the structure of the conventional stacked gate type memory cell 100, it is impossible to use the silicon oxide film formed by the thermal oxidation method for the insulating film 106. Further, since the ONO film has a three-layer structure, there is a problem that the manufacturing method becomes complicated by the steps of sequentially forming each layer.

In addition, since the structure of the conventional stacked gate type transistor 100 is more complicated than that of a normal MOS transistor, the manufacturing process is complicated. There was also the problem of needing it. Therefore, it is difficult to incorporate the conventional stacked gate type memory cell 100 into an LSI chip such as an MPU.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a stack capable of sufficiently obtaining a coupling capacitance between a floating gate and a control gate even when miniaturized. Another object of the present invention is to provide a non-volatile semiconductor memory device including a gate type memory cell. Another object of the present invention is to provide a simple and easy manufacturing method of such a nonvolatile semiconductor memory device.

[0010]

The gist of the invention according to claim 1 is to use an impurity region formed in a semiconductor substrate as a gate or a word line.

A second aspect of the present invention provides a stacked gate type memory cell using an impurity region formed on a surface of a semiconductor substrate as a control gate or a word line.

According to a third aspect of the present invention, a control gate or word line made of an impurity region formed on the surface of a semiconductor substrate, an insulating film formed on the control gate or word line, and an insulating film on the insulating film are formed. The gist of the present invention is to provide a stacked gate type memory cell including a floating gate formed in.

According to a fourth aspect of the present invention, a control gate or word line made of an impurity region formed on the surface of a silicon substrate, a silicon oxide film formed on the control gate or word line, and a silicon oxide film thereof are formed. A gist of the present invention is to provide a stacked gate type memory cell including a floating gate formed on the film, wherein the silicon oxide film is formed by using a thermal oxidation method.

According to a fifth aspect of the present invention, an element isolation region formed on a silicon substrate, the surface of the substrate being divided into a first region and a second region by the element isolation region, A control gate or a word line formed of an impurity region formed in the first region, a source region and a drain region formed in the second region, and a source region and a drain region formed in the second region. A stacked gate including a channel region, a floating gate formed over the isolation region over the channel region and the control gate, and a silicon oxide film formed between the channel region and the control gate and the floating gate. The gist of the present invention is to provide a memory cell of the type, and the silicon oxide film is formed by using a thermal oxidation method.

According to a sixth aspect of the present invention, an element isolation region formed on a silicon substrate, an active region formed on the substrate surface other than the portion where the element isolation region is formed, and an active region are formed. A control gate or a word line formed of an impurity region, a source region and a drain region formed in the active region, a channel region formed between the source region and the drain region in the active region, and an element isolation region. A stacked gate type memory cell including a floating gate formed on the channel region and the control gate, and a silicon oxide film formed between the channel region and the control gate and the floating gate. The gist is that it was formed using a thermal oxidation method.

According to a seventh aspect of the present invention, a step of forming an element isolation region on a silicon substrate and a step of forming a control gate formed of the impurity region by doping an impurity on a portion of the substrate surface corresponding to the control gate. A step of forming a silicon oxide film over the entire surface of the substrate by using a thermal oxidation method, a step of forming a floating gate by patterning a conductive film over the entire surface of the device, and the substrate using the floating gate as a mask for ion implantation. And a step of forming a source region and a drain region in a self-aligned manner with respect to the floating gate by ion-implanting impurities.

[0017]

According to the invention described in claim 1, it is possible to obtain a semiconductor device using an impurity region formed in a semiconductor substrate as a gate or a word line. If the semiconductor device is used as a memory cell transistor of a nonvolatile semiconductor memory device, a stacked gate memory cell can be embodied.

According to the second aspect of the present invention, the impurity region formed on the surface of the semiconductor substrate is used as a control gate or a word line. Therefore, by using a silicon substrate as a semiconductor substrate and forming a floating gate through an insulating film formed on the silicon oxide film, a stacked gate type memory cell can be realized. In this case, a silicon oxide film formed by using a thermal oxidation method can be used as the insulating film. Since the silicon oxide film formed by using the thermal oxidation method can be easily thinned while improving the quality, even if the stacked gate memory cell is miniaturized, the floating gate and the control gate are A sufficient coupling capacity between them can be obtained.

In the invention described in claim 3, if a silicon substrate is used as the semiconductor substrate, a silicon oxide film formed by using a thermal oxidation method can be used as the insulating film. Therefore, according to the invention described in claim 3, it is possible to obtain the same operation and effect as the invention described in claim 2.

According to the invention described in any one of claims 4 to 6, a silicon oxide film formed by a thermal oxidation method is used as an insulating film between the control gate and the floating gate. . Therefore, according to the invention described in any one of claims 4 to 6, it is possible to obtain the same operation and effect as the invention described in claim 2.

In a fifth aspect of the present invention, the stacked gate type memory cell has the same structure as the normal MOS transistor on the second region side, and the second region side is similar to the normal MOS transistor. It has a structure of. Therefore, according to the invention described in claim 5, the structure is much simpler than that of the conventional stacked gate type memory cell.

In a sixth aspect of the invention, the side of the stacked gate type memory cell on which the source region and the drain region are provided has the same structure as an ordinary MOS transistor and is provided with a control gate. The side has a structure similar to that of a normal MOS transistor. Therefore, according to the invention described in claim 6, the structure is much simpler than that of the conventional stacked gate type memory cell.

According to the invention of claim 7, claim 2
The nonvolatile semiconductor memory device described in any one of 1 to 6 can be manufactured easily and easily by using a general technique.

[0024]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial sectional perspective view of a stacked gate type memory cell (stacked gate type transistor) 1 of this embodiment. FIG. 2 is a plan view of the stacked gate memory cell 1 shown in FIG. 3A is a sectional view taken along the line AA in FIG. 2, and FIG. 3B is a sectional view taken along the line BB in FIG.

An element isolation oxide film (element isolation region) 3 is formed on a p-type single crystal silicon substrate 2. A floating gate 5 is arranged on the substrate 2 so as to cross the element isolation oxide film 3 at right angles through a silicon oxide film (hereinafter referred to as a thermal oxide film) 4 formed by a thermal oxidation method. . A control gate 6 composed of an n-type impurity region is formed on the surface (first region) of one substrate 2 divided by the element isolation oxide film 3, and an n-type impurity is formed on the surface (second region) of the other substrate 2. A source region 7 and a drain region 8 are formed. A channel region 9 is formed between the regions 7 and 8 on the surface of the substrate 2. Part of the floating gate 5 is formed on the channel region 9 via the thermal oxide film 4, and another part of the floating gate 5 is formed on the control gate 6 via the thermal oxide film 4. A silicon oxide film 10 is formed so as to cover the floating gate 5. The control gate 6 is shared by the plurality of floating gates 5 formed on the substrate 2 to form a word line of the flash EEPROM.

Next, a method of manufacturing the stacked gate type memory cell 1 of this embodiment will be described. Step 1: The element isolation oxide film 3 is formed on the p-type single crystal silicon substrate 2 by using the LOCOS method.

Step 2: The device surface except the portion corresponding to the control gate 6 is covered with a resist pattern. Next, using the ion implantation method, n-type impurities (arsenic, phosphorus, etc.) are ion-implanted into the substrate 2 using the resist pattern as an ion implantation mask to form the control gate 6 composed of an n-type impurity region.

Step 3: A thermal oxide film 4 is formed on the entire surface of the substrate 2 by using a thermal oxidation method. Step 4: A floating gate 5 is formed by forming a doped polysilicon film on the entire surface of the device by using the low pressure CVD method and patterning the doped polysilicon film.

Step 5: Using the ion implantation method, the floating gate 5 is ion-implanted into the substrate 2 using the floating gate 5 as a mask for ion implantation.
An n-type source region 7 and a drain region 8 are formed in a self-aligned manner with respect to.

Step 6: A silicon oxide film is formed on the entire surface of the device by using the CVD method, and the other silicon oxide film is removed by leaving the silicon oxide film 10 covering the floating gate 5 by using the whole surface etchback method. . At this time, the thermal oxide film 4 exposed from the silicon oxide film 10 is also removed.

As described above, in the stacked gate type memory cell 1 of this embodiment, the thermal oxide film 4 is used as the insulating film between the gates 5 and 6. Since the thermal oxide film 4 can be easily thinned while improving its quality, the coupling capacitance between the floating gate 5 and the control gate 4 can be reduced even when the stacked gate memory cell 1 is miniaturized. You can get enough.

Further, the thermal oxide film 4 can be formed in a single manufacturing process using the thermal oxidation method, and the manufacturing method is simple and the manufacturing process is small compared to the ONO film. Therefore,
The method of manufacturing the stacked gate memory cell 1 of this embodiment is simpler and easier than the method of manufacturing the conventional stacked gate memory cell 100 shown in FIG.

Further, the structure of the stacked gate type memory cell 1 of this embodiment is the same as that of a normal MOS transistor on the side where the regions 7 to 9 are formed on the substrate 2, and the control gate on the substrate 2 is the same. The side where 6 is formed is also similar to a normal MOS transistor. That is, the structure of the stacked gate type memory cell 1 of this embodiment is the same as that of the conventional stacked gate type memory cell 1.
Much easier than 00.

The manufacturing process of this embodiment is the same as the ordinary M
A process having poor compatibility with the manufacturing process of the OS transistor is not required. Therefore, the stacked gate memory cell 1 of this embodiment can be easily incorporated in an LSI chip such as an MPU. In addition, according to this embodiment, the reliability and yield of the device can be improved due to the above-described actions and effects.

The operation of the stacked gate type memory cell 1 of this embodiment is the same as that of the conventional stacked gate type memory cell 100, and therefore its explanation is omitted. (Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows the flash EEPROM of this embodiment.
It is a top view of the memory cell portion in M. FIG. 5 (A)
4 is a sectional view taken along the line AA in FIG. 4, FIG. 5B is a sectional view taken along the line BB in FIG. 4, and FIG. 5C is a sectional view taken along the line CC in FIG. 6D is a sectional view taken along the line D-D in FIG. 4, and FIG. 6E is an E in FIG.
FIG. 4 is a sectional view taken along line -E.

LOCO is formed on the p-type single crystal silicon substrate 21.
An element isolation oxide film (element isolation region) 22 having an S structure is formed. The surface of the substrate 21 on which the element isolation oxide film 22 is not formed becomes an active region. A control gate 23 made of an n-type impurity region, an n-type source region 24 and a drain region 25, and a channel region 26 formed between the regions 24, 25 are formed in the active region. On the substrate 22, each floating gate 28 is arranged so as to straddle the element isolation oxide film 22 with a silicon oxide film (hereinafter referred to as a thermal oxide film) 27 formed by a thermal oxidation method interposed therebetween. Part of the floating gate 28 is formed on the channel region 26 via the thermal oxide film 27, and another part of the floating gate 28 is formed on the control gate 23 via the thermal oxide film 27. A source line 29 and a bit line 30 are arranged in parallel on the substrate 22 so as to extend over the element isolation oxide film 22.

A silicon oxide film 31 is formed so as to cover the floating gate 28. An interlayer insulating film 32 is formed on the entire surface of the device. The source line 29 is the interlayer insulating film 3
Source region 2 through the contact hole formed in
It is connected with 4. The bit line 30 is an interlayer insulating film 32.
Through the contact hole formed in the drain region 2
5 is connected. Source line 29 and bit line 30
And the control gate 23 are arranged so as to be orthogonal to each other.
The control gate 23 is shared by the plurality of floating gates 28 formed on the substrate 21 to form a word line of the flash EEPROM.

The stacked gate type memory cell 33 of this embodiment comprises a control gate 23, a source region 24, a drain region 25, a channel region 26, a thermal oxide film 27 and a floating gate 28.

Next, the manufacturing method of this embodiment will be described with reference to FIGS.
It will be sequentially described with reference to the schematic sectional view shown in FIG. 7 and 8 correspond to a part of FIG. 5B, and FIGS.
Corresponds to a part of FIG.

Step 1 (see FIGS. 7A and 9A);
An element isolation oxide film 22 is formed on the p-type single crystal silicon substrate 21 by using the LOCOS method. Step 2 (see FIGS. 7B and 9B); control gate 2
The surface of the device except for the portion corresponding to 3 is covered with a resist pattern 41. Next, an n-type impurity (arsenic, phosphorus, etc.) is ion-implanted into the substrate 21 using the resist pattern 41 as an ion-implantation mask by using an ion implantation method.
A control gate 23 composed of a type impurity region is formed.

Step 3 (see FIGS. 7C and 9C);
A thermal oxide film 27 is formed on the entire surface of the substrate 21 by using a thermal oxidation method. Next, a low-pressure CVD method is used to form a doped polysilicon film 42 to be the floating gate 28 on the entire surface of the device. Then, a silicon oxide film 31 is formed on the entire surface of the device by using the CVD method.

Step 4 (see FIGS. 7D and 9D);
Silicon oxide film 31 and doped polysilicon film 42
The floating gate 28 is formed by patterning. Next, an n-type impurity (arsenic, phosphorus, etc.) is ion-implanted into the substrate 21 using the ion implantation method using the floating gate 28 as an ion implantation mask, thereby self-aligning with the floating gate 28. The source region 24 and the drain region 25 are formed.

Step 5 (see FIGS. 8A and 10A); a silicon oxide film is formed on the entire surface of the device by using the CVD method, and the floating gate 2 is formed by using the entire surface etchback method.
Other silicon oxide films are removed, leaving only the silicon oxide film 31 covering 8 That is, the exposed floating gate 2
A sidewall spacer 43 made of a silicon oxide film 31 is formed at the end of No. 8. At this time, the silicon oxide film 3
The thermal oxide film 27 exposed from 1 is also removed.

Step 6 (see FIGS. 8B and 10B): An interlayer insulating film 32 is formed on the entire surface of the device. Next, a contact hole 44 for contacting the source region 24 and the drain region 25 is formed in the interlayer insulating film 32.

Step 7 (see FIGS. 7A and 9A);
A source film 29 and a bit line 30 are formed by forming a metal film (various metals including refractory metal) on the entire surface of the device including the inside of the contact hole 44 by using a sputtering method and patterning the metal film.

As described above, in the stacked gate memory cell 33 of this embodiment, the thermal oxide film 27 is used as the insulating film between the gates 23 and 28. Since the thermal oxide film 27 can be easily thinned while improving the quality, the coupling capacitance between the floating gate 28 and the control gate 23 can be reduced even when the stacked gate memory cell 33 is miniaturized. You can get enough.

The thermal oxide film 27 is formed by the thermal oxidation method 1.
It can be formed in a single manufacturing process, and the manufacturing method is simple and the manufacturing process is small compared to the ONO film. Therefore, the method of manufacturing the stacked gate memory cell 33 of the present embodiment is simpler and easier than the method of manufacturing the conventional stacked gate memory cell 100 shown in FIG.

Further, the structure of the stacked gate type memory cell 33 of the present embodiment is such that the regions 24 to 24 in the substrate 21.
The side on which 26 is formed is the same as a normal MOS transistor, and the control gate 23 is formed on the substrate 21.
The side on which is formed is similar to a normal MOS transistor. That is, the structure of the stacked gate type memory cell 33 of this embodiment is much simpler than that of the conventional stacked gate type memory cell 100.

Then, the manufacturing process of the present embodiment is the same as the ordinary M
A process having poor compatibility with the manufacturing process of the OS transistor is not required. Therefore, according to the stacked gate type memory cell 33 of the present embodiment, it is possible to obtain the same operation and effect as the first embodiment. The operation of the stacked gate type memory cell 33 of the present embodiment is the same as that of the conventional stacked gate type memory cell 100, and therefore its explanation is omitted.

By the way, each of the above embodiments may be modified as follows, and in that case, the same operation and effect can be obtained. (1) The material of the floating gates 5 and 28 is replaced with an appropriate conductive material (various metals including refractory metal, silicide, etc.) other than doped polysilicon.

(2) The silicon oxide films 10 and 31 are replaced with another appropriate insulating film (such as a silicon nitride film) or a film having a laminated structure of a plurality of insulating films. (3) Replace the material of the source line 29 and the bit line 30 with an appropriate conductive material (silicide, doped polysilicon, etc.) other than metal.

(4) The element isolation oxide films 3 and 22 of the LOCOS structure are replaced with the element isolation regions of other structures (trench structure, junction isolation structure, etc.). (5) The p-type single crystal silicon substrates 2 and 21 are replaced with p-type wells.

(6) Replace the p-type single crystal silicon substrates 2 and 21 with n-type single crystal silicon substrates or n-type wells,
P-type impurity ions (boron, iridium, etc.) are used as the impurity ions implanted to form the source regions 7 and 24 and the drain regions 8 and 25.

Although the respective embodiments have been described above, the technical ideas other than the claims that can be understood from the respective embodiments will be described.
The effects will be described below. (A) In the nonvolatile semiconductor memory device according to any one of claims 2 to 6, the control gate forms a word line by being shared by a plurality of floating gates formed on a substrate. Nonvolatile semiconductor memory device.

In this way, the word line can be formed by the control gate. (B) The nonvolatile semiconductor memory device according to claim 6, further comprising a source line connected to the source region and a bit line connected to the drain region, and the source line and the bit line are orthogonal to the control gate. Non-volatile semiconductor memory device that is arranged in such a manner.

(C) A method of manufacturing a nonvolatile semiconductor memory device according to claim 7, wherein a doped polysilicon film is used as the conductive film.

This makes it possible to reduce restrictions on the processing temperature when forming the upper structure of the floating gate. By the way, in this specification, a member according to the constitution of the invention is defined as follows.

(A) The semiconductor substrate includes not only a single crystal silicon substrate but also a well. (B) The conductive film includes not only the doped polysilicon film but also various metals including refractory metal and silicide.

[0061]

As described above in detail, according to the present invention, a stacked gate type memory cell capable of sufficiently obtaining the coupling capacitance between the floating gate and the control gate even when miniaturized is provided. A nonvolatile semiconductor memory device can be provided. Further, it is possible to provide a simple and easy manufacturing method of such a nonvolatile semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a perspective view of a first embodiment.

FIG. 2 is a plan view of the first embodiment.

3A is a cross-sectional view taken along the line AA of FIG. FIG.
2B is a cross-sectional view taken along the line BB of FIG.

FIG. 4 is a plan view of the second embodiment.

5A is a cross-sectional view taken along the line AA of FIG. Figure 5
4B is a cross-sectional view taken along the line BB of FIG. FIG. 5C is C of FIG.
-C line sectional view.

6 (D) is a cross-sectional view taken along line DD of FIG. Figure 6
(E) is the EE sectional view taken on the line of FIG.

FIG. 7 is a schematic cross-sectional view for explaining the manufacturing method of the second embodiment.

FIG. 8 is a schematic cross-sectional view for explaining the manufacturing method of the second embodiment.

FIG. 9 is a schematic cross-sectional view for explaining the manufacturing method of the second embodiment.

FIG. 10 is a schematic cross-sectional view for explaining the manufacturing method of the second embodiment.

FIG. 11 is a perspective view of a conventional example.

[Explanation of symbols]

 2, 21 p-type single crystal silicon substrate as semiconductor substrate 6, 23 ... Gate and control gate or word line 5, 28 ... Floating gate 1, 33 ... Stacked gate memory cell 4, 27 ... Silicon oxide film 7, 24 Source region 8, 25 ... Drain region 9, 26 ... Channel region 3, 22 ... Element isolation oxide film as element isolation region 42 ... Doped polysilicon film as conductive film

Claims (7)

[Claims] 1. A semiconductor device using an impurity region formed in a semiconductor substrate as a gate or a word line. 2. A nonvolatile semiconductor memory device comprising a stacked gate type memory cell using an impurity region formed on a surface of a semiconductor substrate as a control gate or a word line. 3. A control gate or word line formed of an impurity region formed on the surface of a semiconductor substrate, an insulating film formed on the control gate or word line, and a floating gate formed on the insulating film. Non-volatile semiconductor memory device including a stacked gate type memory cell including the following. 4. A control gate or word line formed of an impurity region formed on the surface of a silicon substrate, a silicon oxide film formed on the control gate or word line, and a floating film formed on the silicon oxide film. A nonvolatile semiconductor memory device comprising a stacked gate type memory cell including a gate, wherein the silicon oxide film is formed by using a thermal oxidation method. 5. An element isolation region formed on a silicon substrate, the element isolation region dividing the substrate surface into a first region and a second region, and the element isolation region being formed in the first region. A control gate or word line formed of an impurity region, a source region and a drain region formed in the second region, a channel region formed between the source region and the drain region in the second region, and an element isolation A stacked gate type memory cell including a floating gate formed over the channel region and the control gate across the region, and a silicon oxide film formed between the channel region and the control gate and the floating gate, The silicon oxide film is a non-volatile semiconductor memory device formed by using a thermal oxidation method. 6. A control comprising an element isolation region formed on a silicon substrate, an active region formed on a substrate surface other than a portion where the element isolation region is formed, and an impurity region formed in the active region. A gate or word line, a source region and a drain region formed in the active region, a channel region formed between the source region and the drain region in the active region, and a channel region and a control gate across the element isolation region. A stacked gate type memory cell including a floating gate formed above and a channel region and a silicon oxide film formed between the control gate and the floating gate is provided, and the silicon oxide film is formed by using a thermal oxidation method. The formed nonvolatile semiconductor memory device. 7. A step of forming an element isolation region on a silicon substrate, a step of forming a control gate made of an impurity region by doping an impurity on a portion of the substrate surface corresponding to the control gate, and a thermal oxidation method. To form a silicon oxide film over the entire surface of the substrate, forming a floating gate by forming a conductive film over the entire surface of the device, and implanting impurities into the substrate using the floating gate as an ion implantation mask. And a step of forming a source region and a drain region in a self-aligned manner with respect to the floating gate.