JPH08320294A - Device and method for inspecting defect of pattern to be inspected - Google Patents

Abstract

PURPOSE: To inspect a defect with high reliability by gradation-converting detected image signals when an area with high pattern density and an area with low pattern density are included in a pattern to be inspected, and almost equalizing the respective detecting sensitivities of defect to each other. CONSTITUTION: Gradation converters 17a, 17b gradually increase and decrease output to input by logarithmic conversion or polynomial conversion or the like to perform a gradation conversion. They also have delay memories 3a, 3b. A first comparator 18a corresponding to a mat part performs the cell comparison of the image signal 10a outputted from the gradation converter 17a with the signal 11a obtained from the first delay memory 3a and subjected to gradation conversion with a delay for a pitch of one cell or a plurality of cells to detect a defect in a memory mat part. The comparator 18b also performs the chip comparison of a signal 116 through the same process to detect the defect. A CPU 9 selects the result from the comparator 18a and the result from the comparator 18b to perform a final judgment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a visual inspection for detecting defects in a pattern to be inspected, and more particularly to a method and apparatus for inspecting a pattern to be inspected for defects in a pattern to be inspected such as a semiconductor wafer and a liquid crystal display. .

[0002]

2. Description of the Related Art Conventionally, an inspection device of this type has been disclosed in Japanese Patent Laid-Open No.
As described in Japanese Patent No. 74409 (Prior Art 1), an image of the pattern to be inspected is detected by an image sensor such as a line sensor while moving the pattern to be inspected, and the detected image signal and an image signal delayed by a predetermined time are detected. By comparing the shades, the discrepancy was recognized as a defect.

Further, as a conventional technique relating to the defect inspection of the pattern to be inspected, Japanese Patent Laid-Open No. 174652/1994 (conventional technique 2) is known. The prior art 2 has a brightness on an image detected from a pattern to be inspected such as a semiconductor wafer in which an area having a high pattern density such as a memory mat portion and an area having a low pattern density such as a peripheral circuit are mixed in a chip. From the frequency distribution, the detected image signal is obtained by A / D conversion so that the brightness or contrast between the high density area and the low density area of the pattern to be inspected has a relationship determined by gradation conversion. Gradation conversion is performed on the digital image signal, and the gradation-converted image signal to be compared with this gradation-converted image signal is function-approximated,
The difference between these function-approximated curves is integrated, and based on the high-precision detection of the positional deviation from this integrated value, the image signals that have undergone both gradation conversions are aligned and the patterns to be inspected are compared to make a finer comparison. A technique for inspecting defects with high accuracy is described.

[0004]

By the way, in a pattern to be inspected such as a semiconductor wafer, an area having a high pattern density such as a memory mat portion and an area having a low pattern density such as a peripheral circuit are mixed in a chip, and a memory mat is formed. The pattern is observed dark in the area, and the pattern is observed bright in the peripheral circuit area. However, in the above-mentioned conventional technique, no consideration has been given to the problem of making the detection sensitivities of defects substantially equal in a region having a high pattern density such as a memory mat portion and in a region having a low pattern density such as a peripheral circuit.

An object of the present invention is to solve the above problems.
In a pattern to be inspected in which a region having a high pattern density and a region having a low pattern density coexist, the defect detection sensitivity is made substantially equal so that the defect can be inspected with high reliability. A method and an apparatus therefor are provided. Another object of the present invention is to
In a pattern to be inspected such as a semiconductor wafer in which an area having a high pattern density such as a memory mat portion and an area having a low pattern density such as a peripheral circuit are mixed in a chip, a defect occurs in both areas of the memory mat portion and the peripheral circuit portion. It is an object of the present invention to provide a defect inspection method for a pattern to be inspected and an apparatus therefor capable of inspecting a defect with high reliability without lowering the detection sensitivity. Another object of the present invention is to
Realizes highly reliable defect inspection in the memory mat part in a pattern to be inspected such as a semiconductor wafer in which a high density pattern area of the memory mat part and a low density pattern region of the peripheral circuit are mixed in the chip. An object of the present invention is to provide a defect inspection method for an inspected pattern and an apparatus therefor.

[0006]

In order to achieve the above object, the present invention provides a plurality of chips each having a memory mat portion including a repetitive pattern area which is a cell and a peripheral circuit portion including a non-repeating pattern area. In the defect inspection method for the inspected pattern, the image signal is detected from the inspected pattern, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a first circuit suitable for the peripheral circuit section. A defect in the memory mat portion is detected by performing the gradation conversion of 2 and comparing the first gradation-converted image signal with the reference first image signal, and the second gradation conversion is performed. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a peripheral circuit portion by comparing an image signal with a reference second image signal. . According to the present invention, in the defect inspection method for the pattern to be inspected, the reference first image signal is subjected to a first gradation conversion suitable for a memory mat portion,
The reference second image signal is a second image signal suitable for the peripheral circuit unit.
Is characterized by being subjected to gradation conversion. The present invention also provides a defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat portion formed of a repetitive pattern area which is a cell and a peripheral circuit portion formed of a non-repeated pattern area are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. Defect inspection of the pattern to be inspected by detecting the defect in the memory mat portion by the cell comparison of the image signal, and detecting the defect in the peripheral circuit portion by the chip comparison of the second gradation-converted image signal. Is the way.

The present invention also provides a defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat portion consisting of a repetitive pattern area which is a cell and a peripheral circuit portion consisting of a non-repeating pattern area are arranged. An image signal is detected from the pattern, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section. The tone-converted image signal is compared with the reference first image signal, and a defect in the memory mat portion is detected based on the length of the mismatch area or the brightness information between the images of the mismatch area, and the second floor is detected. Defects in a pattern to be inspected, characterized by detecting a defect in a peripheral circuit section by comparing a tone-converted image signal with a reference second image signal. It is a 査方 method. The present invention also provides a defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat portion formed of a repetitive pattern area which is a cell and a peripheral circuit portion formed of a non-repeated pattern area are arranged. Detect the signal,
The detected image signal is subjected to the first gradation conversion suitable for the memory mat portion and the second gradation suitable for the peripheral circuit portion.
Is performed, and the first gradation-converted image signal is compared with the reference first image signal to detect a defect in the memory mat portion, and the defect is detected based on the light-dark distribution information of the mismatched region. A defect inspection method for a pattern to be inspected, characterized by detecting a defect in a peripheral circuit section by classifying and comparing the second gradation-converted image signal with a reference second image signal. The present invention also provides a defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat portion formed of a repetitive pattern area which is a cell and a peripheral circuit portion formed of a non-repeated pattern area are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. Cell comparison is performed on the image signal, the defect in the memory mat portion is detected based on the length of the mismatch area or the brightness information between the images of the mismatch area, and the second gradation-converted image signal is compared by chip comparison. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a peripheral circuit section.

The present invention also provides a defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat portion consisting of a repetitive pattern area which is a cell and a peripheral circuit portion consisting of a non-repeating pattern area are arranged. An image signal is detected from the pattern, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section. For the tone-converted image signal, a defect in the memory mat portion is detected by cell comparison, and the defect is classified based on the light-dark distribution information of the non-coincidence area. For the second gradation-converted image signal, the peripheral circuit portion is compared by chip comparison. Is a defect inspection method for a pattern to be inspected. Further, according to the present invention, in the defect inspection method for the pattern to be inspected, the first and second gradation conversions are logarithmic conversions, exponential conversions, and polynomial conversions. Further, in the present invention, in the method of inspecting a defect of a pattern to be inspected, in comparing a plurality of patterns to be inspected formed to be the same, the defect is darker than the original pattern by using the brightness of the mismatched area. It is characterized by distinguishing whether it is bright or bright. The present invention also provides
In the method of inspecting a defect of a pattern to be inspected, light and dark information of mismatches detected at positions corresponding to two consecutive times, for example, positive and negative is detected, and when the same sign is used for both times, this is not output. . Further, the present invention relates to a mismatch detected only once in the defect inspection method for the pattern to be inspected. When the length of the mismatch area is larger than a predetermined value, the change of the light and dark information in the mismatch area is detected. , It is characterized by identifying whether the defect is darker or brighter than the original brightness of the pattern.

Further, the present invention provides a defect inspection apparatus for a pattern to be inspected, in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system (detection optical system, which detects an image signal from a pattern,
Secondary electron detection system), a first gradation conversion means for performing a first gradation conversion suitable for the memory mat portion on the image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit portion on the signal, and first gradation conversion means for the first gradation conversion means.
First comparing means for detecting a defect in the memory mat portion by comparing the gradation-converted image signal with the reference first image signal; and the second gradation by the first gradation converting means. In each of the first comparing means and the second comparing means, second comparing means for detecting a defect in the peripheral circuit section by comparing the converted image signal with a reference second image signal. A defect inspection apparatus for a pattern to be inspected, comprising: comparison or selection means for selecting a defect detected from each of the first comparison means and the second comparison means. Further, according to the present invention, in the defect inspection apparatus for the pattern to be inspected, the first comparing means is obtained by subjecting the reference first image signal to first gradation conversion suitable for a memory mat portion. And the second comparing means is the second of the reference.
This image signal is subjected to the second gradation conversion suitable for the peripheral circuit section to obtain the image signal.
Further, the present invention provides a defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat portion formed of a repeated pattern region which is a cell and a peripheral circuit portion formed of a non-repeated pattern region are arranged. A detection system (detection optical system, secondary electron detection system) for detecting a signal, and a first gradation conversion for applying a first gradation conversion suitable for a memory mat portion to an image signal detected by the detection system. Means, second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit section on the image signal detected from the detection system, and the first gradation conversion means for the first floor. First comparison means for detecting a defect in the memory mat portion by cell comparison for the tone-converted image signal and chip comparison for the second tone-converted image signal by the first tone conversion means. Second comparison means for detecting a defect in the peripheral circuit section, and comparison in each of the first comparison means and the second comparison means or each of the first comparison means and the second comparison means A defect inspection apparatus for a pattern to be inspected, comprising: a selecting unit that selects a defect detected from the defect.

Further, the present invention provides a defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system (detection optical system, which detects an image signal from a pattern,
Secondary electron detection system), a first gradation conversion means for performing a first gradation conversion suitable for the memory mat portion on the image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit portion on the signal, and first gradation conversion means for the first gradation conversion means.
The first comparison for comparing the gradation-converted image signal with the reference first image signal to detect a defect in the memory mat portion based on the length of the mismatch area or the brightness information between the images in the mismatch area. Means and second comparing means for detecting a defect in the peripheral circuit section by comparing the image signal which has been subjected to the second gradation conversion by the first gradation conversion means with a reference second image signal, Comprising a comparison in each of the first comparison means and the second comparison means, or a selection means for selecting a defect detected from each of the first comparison means and the second comparison means. Is a defect inspection apparatus for a pattern to be inspected.

The present invention also provides a defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system (detection optical system, which detects an image signal from a pattern,
Secondary electron detection system), a first gradation conversion means for performing a first gradation conversion suitable for the memory mat portion on the image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit portion on the signal, and first gradation conversion means for the first gradation conversion means.
The gradation-converted image signal is compared with the reference first image signal, and a defect in the memory mat portion is detected based on the length of the mismatch area or the brightness information between the images of the mismatch area to detect the mismatch area. A first comparing means for classifying defects on the basis of the light and dark distribution information, and a peripheral circuit by comparing the second gradation-converted image signal by the first gradation converting means with a reference second image signal. Second comparing means for detecting a defect in a part, and comparison by each of the first comparing means and the second comparing means or detection by each of the first comparing means and the second comparing means A defect inspection apparatus for inspecting a pattern to be inspected. Further, the present invention provides a defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat portion formed of a repeated pattern region which is a cell and a peripheral circuit portion formed of a non-repeated pattern region are arranged. A detection system (detection optical system, secondary electron detection system) for detecting a signal, and a first gradation conversion for applying a first gradation conversion suitable for a memory mat portion to an image signal detected by the detection system. Means, second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit section on the image signal detected from the detection system, and the first gradation conversion means for the first floor. First comparing means for performing cell comparison on the tone-converted image signals and detecting a defect in the memory mat portion based on the length of the non-matching area or the brightness information between the images of the non-matching area; and the first gradation. conversion A second comparing means for detecting a defect in the peripheral circuit portion by chip comparison for the second gradation-converted image signal in the stage, and a comparison in each of the first comparing means and the second comparing means; A defect inspection apparatus for a pattern to be inspected, comprising: a selection unit that selects a defect detected by each of the first comparison unit and the second comparison unit.

Further, the present invention is a defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system (detection optical system, which detects an image signal from a pattern,
Secondary electron detection system), a first gradation conversion means for performing a first gradation conversion suitable for the memory mat portion on the image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit portion on the signal, and first gradation conversion means for the first gradation conversion means.
First comparing means for detecting a defect in the memory mat portion by performing cell comparison on the gradation-converted image signal and classifying the defect based on the light-dark distribution information of the non-coincidence region; and the first gradation converting means. In the second gradation converting image signal, the second comparing means for detecting a defect in the peripheral circuit portion by chip comparison, and the first comparing means and the second comparing means respectively comparing or A defect inspection apparatus for a pattern to be inspected, comprising: a selection unit that selects a defect detected by each of the first comparison unit and the second comparison unit. Further, the present invention is characterized in that, in the defect inspection apparatus for an inspected pattern, the selecting means is configured to make a selection based on array data of a memory mat portion and a peripheral circuit section in the inspected pattern. Further, the present invention is characterized in that, in the defect inspection apparatus for the pattern to be inspected, the selecting means is configured to select based on the mismatch information obtained in the cell comparison in the first comparing means. Further, the present invention is a defect inspection method for an inspected pattern having a high pattern density region and a low pattern density region, wherein an image signal is detected from the inspected pattern, and a pattern density is detected with respect to the detected image signal. The first gradation conversion suitable for the high area is performed and the second gradation conversion suitable for the low pattern density area is performed.
The first reference of the first gradation-converted image signal
Defect in a region having a high pattern density is detected by comparing the image signal with the second image signal and a defect in a region having a low pattern density by comparing the second tone-converted image signal with a reference second image signal. Is a defect inspection method for a pattern to be inspected.

Further, the present invention is a defect inspection apparatus for a pattern to be inspected having a region having a high pattern density and a region having a low pattern density, and a detection system (detection optical system, secondary system) for detecting an image signal from the pattern to be inspected. An electronic detection system) and a first gradation conversion suitable for an area having a high pattern density for the image signal detected by the detection system.
Gradation conversion means, second gradation conversion means for performing a second gradation conversion suitable for an area having a low pattern density on the image signal detected by the detection system, and the first gradation conversion means. First reference of the image signal which has been subjected to the first gradation conversion by the means
First comparing means for detecting a defect in a region having a high pattern density by comparing with the image signal of No. 2 and the second reference image of the image signal subjected to the second gradation conversion by the first gradation conversion means. Second comparing means for detecting a defect in an area having a low pattern density by comparing with the image signal, and comparison in each of the first comparing means and the second comparing means or the first comparing means The second
And a selecting means for selecting a defect detected from each of the comparing means and the defect inspecting apparatus for a pattern to be inspected.

[0014]

According to the above structure, in the pattern to be inspected in which a plurality of chips each having a memory mat portion including a repetitive pattern area which is a cell and a peripheral circuit portion including a non-repeating pattern area are arranged, a difference in pattern density is caused. The defect can be detected with high sensitivity without being affected by the difference in the brightness of the pattern to be inspected. Therefore, it is possible to inspect defects with high sensitivity even in a region having a high pattern density such as a memory mat portion. Further, in a region having a low pattern density such as a peripheral circuit, the defect can be inspected without unnecessarily raising the defect detection sensitivity. Moreover, it is particularly effective not only in the method of detecting the grayscale difference of images but also in the case of comparing differential values of images. Further, in a pattern to be inspected having a region having a high pattern density and a region having a low pattern density, a defect is detected with high sensitivity without being affected by a difference in brightness of the pattern to be inspected caused by a difference in the pattern density. be able to. Further, according to the above configuration, in comparing cells or the like of the pattern to be inspected, it is possible to inspect the defect with higher reliability due to the mismatch in the images.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a defect inspection method for a pattern to be inspected and an apparatus therefor according to the present invention will be described with reference to the drawings. Figure 2
FIG. 4 is a diagram showing a memory chip formed in large numbers on a semiconductor wafer 4, which is an example of a pattern to be inspected according to the present invention. Memory chips 20 are roughly divided into
The memory mat section 21 and the peripheral circuit section 22 can be roughly classified. The memory mat part 21 is a set of small repeating patterns, and the peripheral circuit part 22 is a set of random patterns.
FIG. 3 is a histogram showing the frequency with respect to the brightness (shading) (10-bit configuration: maximum 1024) in the memory mat section 21 and the peripheral circuit section 22. As shown in FIG. 3, the memory mat portion 21 has a high pattern density and is generally dark. On the other hand, the peripheral circuit section 22 has a low pattern density and is bright. Therefore, it is difficult to detect a defect in the memory mat portion 21, and it is easy to erroneously detect a normal portion as a defect in the peripheral circuit portion 22. Defects in such an inspected pattern are inspected using the apparatus shown in FIG. 1 is shown in FIG.
FIG. 3 is a configuration diagram showing an embodiment of a defect inspection device for an inspected pattern for inspecting a defect in the inspected pattern shown in FIG.
That is, 5 is an X, Y, Z, θ (rotation) stage on which the semiconductor wafer 4, which is an example of the pattern to be inspected, is placed. Reference numeral 6 is an objective lens. An illumination light source 7 illuminates the semiconductor wafer 4, which is an example of the pattern to be inspected. Reference numeral 8 denotes a half mirror, which is configured to reflect the illumination light from the illumination light source 7 and to apply, for example, bright field illumination to the semiconductor wafer 4 through the objective lens 6. An image sensor 1 outputs a grayscale image signal according to the brightness (grayscale) of the reflected light from the semiconductor wafer 4, which is an example of the pattern to be inspected. Reference numeral 2 denotes an A / D converter, which converts a grayscale image signal obtained from the image sensor 1 into a digital image signal 9.

Reference numeral 17a is a first gradation converter, which is A /
The digital image signal 9 output from the D converter 2 is subjected to gradation conversion 41 (shown in FIG. 4) corresponding to the memory mat section 21. That is, the first gradation converter 1
7a increases the output with respect to the input by performing logarithmic conversion, exponential conversion, polynomial conversion, etc., and when the input reaches a certain value (maximum value of gradation conversion in the memory mat part 21), outputs 7a. The gradation conversion 41 is performed so as to make it a constant value. The first gradation converter 17a is configured to output an 8-bit digital signal, for example. 17b
Is a second gradation converter that performs gradation conversion 42 (shown in FIG. 4) corresponding to the peripheral circuit section 22 on the digital image signal 9 output from the A / D converter 2. Is. That is, the second gradation converter 17b performs gradation conversion 42 that performs logarithmic conversion, exponential conversion, polynomial conversion, and the like to gradually reduce the output with respect to the input. The second gradation converter 17b is also configured to output an 8-bit digital signal, for example. Reference numeral 3a denotes a first delay memory, which stores and delays the image signal 10a output from the first gradation converter 17a and subjected to the gradation conversion 41 by the repeated one cell or a plurality of cell pitches. . Three
b is a second delay memory, which is a second gradation converter 17b
The image signal 10b output from
Is stored for one chip or a plurality of chip pitches that are repeated and delayed.

Reference numeral 18a denotes a first comparator corresponding to the memory mat section 21, and the image signal 10a output from the first gradation converter 17a and subjected to the gradation conversion 41 and the first delay memory 3a. A defect in the memory mat portion 21 is detected by performing a cell comparison for comparing with the image signal 11a that has been subjected to the gradation conversion 41 delayed by one cell or a plurality of cell pitches obtained from FIG. Reference numeral 18b denotes a second comparator corresponding to the peripheral circuit section 22, which is obtained from the image signal 10b which has been subjected to the gradation conversion 42 and is output from the second gradation converter 17b and the second delay memory 3b. Peripheral circuit unit 22 performs chip comparison to compare with image signal 11b subjected to gradation conversion 42 delayed by one chip or a plurality of chip pitches.
To detect defects in the. 19 is a CPU,
For example, based on the coordinate information of the semiconductor wafer, it is discriminated whether it is the memory mat section 21 or the peripheral circuit section 22, and the comparison result from the first comparator 18a and the second comparator 18b.
The final judgment is made by selecting the comparison result from.

Next, the operation will be described. That is, while scanning the stage 5 and moving the semiconductor wafer 4 which is an example of the pattern to be inspected at a constant speed, the pattern to be inspected (the memory mat portion 21 in the chip 20 formed on the semiconductor wafer 4 by the image sensor 1 is moved. And brightness information (grayscale image signal) of the peripheral circuit section 22) is detected. And A / D
The converter 2 outputs the image sensor 1 (gray image signal)
Is converted into a digital image signal 9. This digital image signal 9 has a 10-bit configuration. Next, the output of this digital image signal 9 is increased with respect to the input by the first gradation converter 17a as shown in FIG. 4, and the input has a certain value (the maximum value of the gradation conversion in the memory mat portion 21). ) Is reached, gradation conversion 4 is performed so that the output becomes a constant value.
Give 1. FIG. 5 shows a histogram of the output image signal 10a which has been subjected to the gradation conversion 41 in the first gradation converter 17a. This output has an 8-bit structure as is apparent from FIG. Further, the digital image signal 9 is converted by the second gradation converter 17b as shown in FIG. 4, in which the output is gradually reduced with respect to the input (input signal 10
A gradation conversion 42 is performed in which the bits are logarithmically converted, and the dark portion is slightly darkened and the bright portion is further darkened for output. FIG. 6 shows a histogram of the output image signal 10b subjected to the gradation conversion 42 in the second gradation converter 17b. This output also has an 8-bit structure as is apparent from FIG.

The gradation conversion 41 in the first gradation converter 17a and the gradation conversion 42 in the second gradation converter 17b detect the images of the memory mat section 21 and the peripheral circuit section 22 before the inspection. Then, it is determined from these histograms (shown in FIGS. 5 and 6). The gradation conversion 41 in the first gradation converter 17a is performed, for example, as shown in FIG. 5, so that the shape of the histogram, that is, the gradation range defined by the memory mat section including the minimum value and the maximum value is included. Decide Further, the gradation conversion 42 in the second gradation converter 17b
Is determined so that the contrast of the pattern is approximately the same in the memory mat portion and the peripheral circuit portion as shown in FIG. The contrast may be obtained by differentiating the image signal. In either case, it is necessary to decide so as to maintain a desired relationship before and after gradation conversion. Specifically, the gradation conversion is logarithmic conversion, exponential conversion, polynomial conversion, or the like. By the way, the histogram shown in FIG. 5 (corresponding to the memory mat section 21) and the histogram shown in FIG. 6 (corresponding to the peripheral circuit section 22)
Comparing with, the frequency for the brightness (shading) (8-bit configuration) in the memory mat portion 21 and the frequency for the brightness (shading) (8-bit configuration) in the peripheral circuit portion 22 are almost the same. It is clear that

Then, the image signal 10a subjected to the tone conversion 41 by the first tone converter 17a is stored in the first delay memory 3a, and the image signal 11a already stored is read out. By performing cell comparison in the first comparator 18a, a defect in the memory mat portion 21 can be detected. In addition, the second gradation converter 17
The image signal 10b which has been subjected to the gradation conversion 42 by
Of the second comparator 18b while storing the image signal 11b already stored in the delay memory 3b of the second comparator 18b.
By comparing the chips in, the defect in the peripheral circuit portion 22 can be detected. First comparator 18
a is a cell comparison for comparing the detected image with the image delayed by an amount corresponding to the cell pitch output from the first delay memory 3a, and the second comparator 18b outputs from the second delay memory 3b. 2 is a chip comparison in which an image delayed by an amount corresponding to the chip pitch is compared with a detected image. The coordinates of the array data and the like in the chip on the semiconductor wafer 4 shown in FIG. 2 obtained based on the design information are
The CPU 19 causes the first comparator 1 to operate by inputting with the input means 12 composed of a keyboard, a disk and the like.
The cell comparison result by 8a and the chip comparison result by the second comparator 18b are selected based on the coordinates of the input array data in the chip on the semiconductor wafer 4 and the defect inspection data is created. And stores it in the storage device 13. The defect inspection data can be displayed on a display unit such as a display as necessary, or can be output to an output unit.

In the above embodiment, the first comparator 18
The CPU 19 is made to select the result of the cell comparison by a and the result of the chip comparison by the second comparator 18b.
In the first comparator 18a and the second comparator 18b,
It is clear that you can go. The selection of the cell comparison by the first comparator 18a and the chip comparison by the second comparator 18b may be performed as follows. That is, the CPU 19 calculates the mismatch information obtained by the cell comparison from the first comparator 18a for each image in a predetermined range, for example, the number of mismatch pixels, and when this is larger than the threshold value, the second It is possible to select the result of chip comparison using the corresponding image obtained from the comparator 18b, and select the cell comparison result obtained from the first comparator 18a when the number of mismatched pixels is smaller than the threshold value. it can. According to this method, it is possible to select chip comparison and cell comparison without having array information in the chip.
According to the present invention, as described in the above embodiment, after performing the gradation conversion corresponding to the memory mat section and the gradation conversion corresponding to the peripheral circuit section, the comparisons (cell comparison and chip comparison) are performed respectively. It is characterized by that.

The details of the first comparator 18a and the second comparator 18b may be the method developed by the present inventors, such as the one disclosed in Japanese Patent Laid-Open No. 61-212708, for example, image alignment. From a circuit, a difference image detection circuit for aligned images, a discrepancy detection circuit for binarizing the difference image, and a feature extraction circuit for calculating area, length (projection length), coordinates, etc. from the binarized output Become. Further, in the case of the present invention, as will be described later, it is composed of a circuit for detecting the light and dark information of the difference image at the disagreement portion. In the above embodiment, the case where the first gradation converter 17a and the second gradation converter 17b output in 8-bit configuration has been described, but it may output in 10-bit configuration. However, the output in the 8-bit configuration can reduce the number of effective bits after gradation conversion. In the above embodiment, the defect inspection image processing of the pattern to be inspected (A / D converter 2 to C according to the present invention is performed.
PU 19) up to the optical microscope (stage 5, objective lens 6, illumination light source 7, half mirror 8, image sensor 1) has been described, but it is clear that it can also be applied to a scanning electron microscope. . However, when the defect inspection image processing of the pattern to be inspected (from the A / D converter 2 to the CPU 19) according to the present invention is applied to the scanning electron microscope, the image sensor 1 becomes a detector such as a scintillator.

Next, one embodiment of the comparative defect determination in the repeated pattern area having a high pattern density such as the memory mat portion 21 will be described with reference to FIGS. First, an embodiment in which a defect is determined based on the length L of the mismatch area will be described with reference to FIGS. That is, in FIG. 7, the image A has minute defects. This image A
Is the delay amount Δ determined by the first delay memory 3a, for example.
Delay by t to obtain image A '. The delay amount is an amount corresponding to the cell pitch of the repeating pattern. When these images A and A'are compared by, for example, the first comparator 18a and | A-A '| is detected as a mismatched image, a mismatch due to a difference in brightness occurs at two places. As described above, since the defect always appears twice, the CPU 19, for example, may determine the defect having the interval corresponding to Δt that appears twice as the correct defect. Obviously, this determination may be performed by the first comparator 18a. If this judgment appears only once, it can be regarded as a false alarm. However, as shown in FIG. 8, in the case of a defect that is relatively larger than Δt, there is only one mismatch. Therefore, the above-mentioned rule that the inconsistency always appears twice cannot be applied, and this is overlooked. Therefore, for example, the CPU 19 detects the mismatched length L as shown in the figure, and when L is as large as Δt, it may be determined as a correct defect without appearing twice. .

Next, with reference to FIG. 9 and FIG. 10, an embodiment in which a defect is judged based on the brightness information of the non-coincidence area will be described. That is, FIG. 9 shows the brightness including mismatch. In the case of a small dark defect, the disagreement appears twice in the order of negative and positive. Therefore, for example, the CPU 19 can determine that the defect is darker than the original brightness of the pattern in this order. Similarly, as shown in FIG.
In the case of a relatively large dark defect compared to Δt, the mismatch is 1
Although it appears only once, the internal brightness change information of disagreement is in the order of negative and positive. Therefore, in this case, for example, even if the mismatch occurs only once in the CPU 19, it can be determined from the brightness change information that the dark defect exists. The embodiments of the image gradation conversion and comparison method according to the present invention have been described above. According to the above embodiment, the defect can be detected with high sensitivity without being affected by the difference in the brightness of the pattern depending on the place. Therefore, a dark area such as the memory mat portion 21 can be inspected with high sensitivity. In addition, a bright area such as the peripheral circuit section 22 can be inspected without unnecessarily raising the defect detection sensitivity. Moreover, it is effective not only in the method of detecting the grayscale difference of images, but also in the method of comparing differential values of images. Therefore, it is possible to realize a highly reliable inspection as compared with the conventional case.

Further, according to the above-mentioned embodiment, by using the information of the length of mismatch and the brightness, or the information of the change of the brightness, the false detection can be reduced and the brightness of the defect can be judged, and the inspection reliability and the defect can be improved. Classification is possible. The present invention mainly described a comparative inspection method based on image detection using an optical microscope, but also when using a scanning electron microscope,
Equally effective.

[0026]

According to the present invention, it is possible to detect defects with high sensitivity without being affected by the difference in brightness of the pattern to be inspected depending on the location. Further, according to the present invention, defects can be inspected with high sensitivity in a dark area such as a memory mat portion such as a semiconductor wafer having a pattern to be inspected, and the defect detection sensitivity can be unnecessarily raised too much in a bright area such as a peripheral circuit. Therefore, the inspection can be performed without any trouble, and the highly reliable inspection can be realized. Further, according to the present invention, by using the information on the length of mismatch and the information on the brightness, it is possible to reduce the false detection and significantly improve the reliability of the inspection, and moreover, it is possible to judge the brightness of the defect. It also has the effect of enabling the classification of defects based on it.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a defect inspection apparatus for an inspection pattern according to the present invention.

FIG. 2 is a diagram showing a configuration of a memory chip as a pattern to be inspected according to the present invention.

3 is a diagram showing a histogram of the brightness of a pattern in a memory chip as the pattern to be inspected shown in FIG.

FIG. 4 is a diagram showing two types of gradation conversion (corresponding to a memory mat section and a peripheral circuit section) according to the present invention.

FIG. 5 is a diagram showing a histogram of brightness of a pattern after gradation conversion corresponding to the memory mat portion according to the present invention.

FIG. 6 is a diagram showing a histogram of brightness of a pattern after gradation conversion corresponding to a peripheral circuit unit according to the present invention.

FIG. 7 is a diagram showing how mismatch occurs in the case of defects that are smaller than the cell pitch in cell comparison and the like according to the present invention.

FIG. 8 is a diagram showing how mismatch occurs in the case of a defect larger than the cell pitch in the cell comparison or the like according to the present invention.

FIG. 9 is a diagram showing light and dark information of non-coincidence in the case of a defect that is smaller than a cell pitch in the cell comparison or the like according to the present invention.

FIG. 10 is a diagram showing light and dark information of non-coincidence in the case of a defect larger than a cell pitch in the cell comparison or the like according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image sensor, 2 ... A / D converter, 3a ... 1st delay memory 3b ... 1st delay memory, 4 ... Semiconductor wafer 5 ... Stage (X, Y, Z, theta), 6 ... Objective lens, 7
... illumination light source 12 ... input means, 13 ... storage device, 17a ... first gradation converter 17b ... second gradation converter, 18a ... first comparator, 1
8b ... 2nd comparator 19 ... CPU, 20 ... Chip, 21 ... Memory mat part,
22 ... Peripheral circuit section

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Kubota, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock, Institute of Industrial Science, Hitachi, Ltd. (72) Kenji Oka, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Production Engineering Laboratory, Hitachi, Ltd. (72) Inventor Tan Makihira, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company, Production Engineering Laboratory, Hitachi, Ltd.

Claims (19)

[Claims] 1. A defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. A defect in the memory mat portion is detected by comparing the image signal with the reference first image signal, and the defect is detected by comparing the second gradation-converted image signal with the reference second image signal. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a circuit portion. 2. The reference first image signal is subjected to a first gradation conversion suitable for a memory mat portion, and the reference second image signal is converted.
2. The defect inspection method for an inspected pattern according to claim 1, wherein the image signal is subjected to the second gradation conversion suitable for the peripheral circuit section. 3. A defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area, which is a cell, and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. Defect inspection of the pattern to be inspected by detecting the defect in the memory mat portion by the cell comparison of the image signal, and detecting the defect in the peripheral circuit portion by the chip comparison of the second gradation-converted image signal. Method. 4. A defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat part consisting of a repetitive pattern region which is a cell and a peripheral circuit part consisting of a non-repeating pattern region are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. The image signal is compared with the reference first image signal, a defect in the memory mat portion is detected based on the length of the mismatch area or the brightness information between the images of the mismatch area, and the second gradation conversion is performed. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a peripheral circuit section by comparing the image signal with a reference second image signal. 5. A defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat part consisting of a repetitive pattern region which is a cell and a peripheral circuit part consisting of a non-repeating pattern region are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. The detected image signal is compared with the reference first image signal to detect a defect in the memory mat portion, the defect is classified based on the light-dark distribution information of the non-coincidence region, and the second gradation-converted image signal is detected. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a peripheral circuit section by comparing with a reference second image signal. 6. A defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat part consisting of a repetitive pattern region which is a cell and a peripheral circuit part consisting of a non-repeating pattern region are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. Cell comparison is performed on the image signal, the defect in the memory mat portion is detected based on the length of the mismatch area or the brightness information between the images of the mismatch area, and the second gradation-converted image signal is compared by chip comparison. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a peripheral circuit section. 7. A defect inspection method for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area, which is a cell, and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A signal is detected, and the detected image signal is subjected to a first gradation conversion suitable for the memory mat section and a second gradation conversion suitable for the peripheral circuit section, and is subjected to the first gradation conversion. The defective image in the memory mat portion is detected by cell comparison with respect to the image signal, and the defect is classified based on the light and dark distribution information of the non-coincidence area. A method of inspecting a defect of a pattern to be inspected, which comprises detecting. 8. The pattern to be inspected according to claim 1, wherein the first and second gradation conversions are logarithmic conversions, exponential conversions, and polynomial conversions. Defect inspection method. 9. A defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system that detects a signal, a first gradation conversion unit that performs a first gradation conversion suitable for a memory mat section on an image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit section on the signal, and first reference of the image signal subjected to the first gradation conversion by the first gradation conversion means. First comparing means for detecting a defect in the memory mat portion by comparing the second gradation-converted image signal with the second gradation-converted image signal by the first gradation converting means. When Second comparison means for detecting a defect in the peripheral circuit section by comparing, and comparison in each of the first comparison means and the second comparison means or the first comparison means and the second comparison And a selecting means for selecting a defect detected from each of the means. 10. The first comparing means is configured to be obtained by subjecting the reference first image signal to first gradation conversion suitable for a memory mat section, and the second comparing means is provided. 10. The defect inspection apparatus for an inspected pattern according to claim 9, wherein the reference second image signal is obtained by performing second gradation conversion suitable for a peripheral circuit section. 11. A defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area, which is a cell, and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system that detects a signal, a first gradation conversion unit that performs a first gradation conversion suitable for a memory mat section on an image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit section on the signal, and memory for cell comparison of the image signal subjected to the first gradation conversion by the first gradation conversion means. First comparison means for detecting a defect in the matte portion and defect in the peripheral circuit portion are detected by chip comparison with respect to the image signal which has been subjected to the second gradation conversion by the first gradation conversion means. A second comparison means, and a comparison in each of the first comparison means and the second comparison means, or a defect detected from each of the first comparison means and the second comparison means is selected. A defect inspection apparatus for a pattern to be inspected, comprising: 12. A defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area, which is a cell, and a peripheral circuit section consisting of a non-repeating pattern area, are arranged. A detection system that detects a signal, a first gradation conversion unit that performs a first gradation conversion suitable for a memory mat section on an image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit section on the signal, and first reference of the image signal subjected to the first gradation conversion by the first gradation conversion means.
And a first comparing means for detecting a defect in the memory mat portion based on the length of the non-matching area or the brightness information between the images of the non-matching area, and the first gradation converting means. Second comparing means for detecting a defect in the peripheral circuit section by comparing the gradation-converted image signal of 2 with a reference second image signal; the first comparing means and the second comparing means. And a selecting unit for selecting a defect detected from each of the first comparing unit and the second comparing unit. 13. A defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat part consisting of a repetitive pattern region which is a cell and a peripheral circuit part consisting of a non-repeating pattern region are arranged. A detection system that detects a signal, a first gradation conversion unit that performs a first gradation conversion suitable for a memory mat section on an image signal detected by the detection system, and an image detected by the detection system. Second gradation conversion means for performing second gradation conversion suitable for the peripheral circuit section on the signal, and first reference of the image signal subjected to the first gradation conversion by the first gradation conversion means.
The first comparison in which the defect in the memory mat portion is detected based on the length of the mismatch area or the brightness information between the images of the mismatch area and the defect is classified based on the light-dark distribution information of the mismatch area. Means and second comparing means for detecting a defect in the peripheral circuit section by comparing the image signal which has been subjected to the second gradation conversion by the first gradation conversion means with a reference second image signal, Comprising a comparison in each of the first comparison means and the second comparison means, or a selection means for selecting a defect detected from each of the first comparison means and the second comparison means. A defect inspection apparatus for a pattern to be inspected. 14. A defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area which is a cell and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system that detects a signal, a first gradation conversion unit that performs a first gradation conversion suitable for a memory mat section on an image signal detected by the detection system, and an image detected by the detection system. Cell comparison is performed on the second gradation conversion unit that performs the second gradation conversion suitable for the peripheral circuit section on the signal, and the image signal that has undergone the first gradation conversion by the first gradation conversion unit; A first comparing unit that detects a defect in the memory mat portion based on the length of the non-matching region or the brightness information between the images of the non-matching region, and the second gray-scale conversion by the first gray-scale converting unit. image No. 2 is compared with each other by the second comparison means for detecting a defect in the peripheral circuit portion by chip comparison, the first comparison means and the second comparison means, or the first comparison means and the second comparison means. A defect inspection apparatus for a pattern to be inspected, comprising: a comparing unit and a selecting unit that selects a defect detected from each of the comparing units. 15. A defect inspection apparatus for a pattern to be inspected in which a plurality of chips each having a memory mat section consisting of a repetitive pattern area, which is a cell, and a peripheral circuit section consisting of a non-repeating pattern area are arranged. A detection system that detects a signal, a first gradation conversion unit that performs a first gradation conversion suitable for a memory mat section on an image signal detected by the detection system, and an image detected by the detection system. A cell comparison is performed between the second gradation conversion unit that performs the second gradation conversion suitable for the peripheral circuit section on the signal and the image signal that has been subjected to the first gradation conversion by the first gradation conversion unit. First, a defect in the memory mat portion is detected and the defect is classified based on the light and dark distribution information of the non-matching area.
Comparing means, second comparing means for detecting a defect in the peripheral circuit portion by chip comparison of the image signal which has been subjected to the second gradation conversion by the first gradation converting means, and the first comparing means.
Comparing means in each of the first comparing means and the second comparing means, or selecting means for selecting a defect detected from each of the first comparing means and the second comparing means. Defect inspection device for inspected pattern. 16. The selection means is configured to make selection based on arrangement data of a memory mat portion and a peripheral circuit portion in a pattern to be inspected. Alternatively, the defect inspection apparatus for the pattern to be inspected according to item 15. 17. The defect of the pattern to be inspected according to claim 14 or 15, wherein said selecting means is configured to select based on the mismatch information obtained in the cell comparison in said first comparing means. Inspection device. 18. A defect inspection method for a pattern to be inspected having a region having a high pattern density and a region having a low pattern density, wherein an image signal is detected from the pattern to be inspected and the pattern density is detected with respect to the detected image signal. The first gradation conversion suitable for the high area of the pattern and the second gradation conversion suitable for the area of the low pattern density are performed.
Defect in a region having a high pattern density is detected by comparing the gradation-converted image signal with the reference first image signal, and the reference second image with respect to the second gradation-converted image signal. A defect inspection method for a pattern to be inspected, which comprises detecting a defect in a region having a low pattern density by comparing with a signal. 19. A defect inspection apparatus for a pattern to be inspected having an area having a high pattern density and an area having a low pattern density, and a detection system for detecting an image signal from the pattern to be inspected, and an image detected by the detection system. First gradation converting means for performing a first gradation conversion suitable for an area having a high pattern density on a signal, and a second gradation converting means suitable for an area having a low pattern density on an image signal detected by the detection system. Higher pattern density is obtained by comparing the second gradation conversion unit that performs gradation conversion with the reference first image signal for the image signal that has been subjected to the first gradation conversion by the first gradation conversion unit. First comparing means for detecting defects in the area;
A second method for detecting a defect in a region having a low pattern density by comparing the second gradation-converted image signal by the first gradation conversion means with a reference second image signal.
Selection means for selecting a defect detected from each of the first comparison means and the second comparison means or a defect detected from each of the first comparison means and the second comparison means. A defect inspection apparatus for a pattern to be inspected, comprising: