JPH0832018A - Hybrid ic - Google Patents

Abstract

PURPOSE:To make a package unnecessary and realize miniaturization, high performance and cost reduction of a high frequency hybrid IC. CONSTITUTION:Spiral inductors 102-107 are formed on a ceramic board 122 by using a single layer wiring of a metal thin film and connected with wirings of a back surface via through holes 114-119, respectively. A semiconductor chip 101 is so mounted on the board in the face down manner by flip chip mounting. A capacitance element using high permittivity material, a resistance element using an ion implantation method or a thin film, and a field-effect transistor are formed on the surface of the semiconductor chip 101. The board is connected with an outer board, through terminals 108-113 formed as recessed parts to the end surface of the board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small, high-performance, high-frequency hybrid IC.

[0002]

2. Description of the Related Art With the rapid spread of mobile devices, there has been a strong demand for smaller size and lighter weight which were originally required for mobile devices. The miniaturization of the high-frequency circuit section, which has conventionally been difficult to integrate, is becoming an essential issue.

A conventional example of a high frequency hybrid IC will be described below with reference to the drawings.

FIG. 1 shows a conventional hybrid IC 10 disclosed in Japanese Patent Application Laid-Open No. 5-251629. In FIG. 1, a surface of a semiconductor chip 1 (a surface not shown in FIG. 1) is provided with a field effect transistor (hereinafter referred to as an FET).
), And a resistance element and a capacitance element are formed.
The semiconductor chip 1 is mounted face-down on pads on the surface of the ceramic substrate 4 by flip chip bonding 2. The spiral inductor 3 is further formed on the surface of the ceramic substrate 4 by a printing technique.

Next, the ceramic substrate 4 on which the semiconductor chip 1 is mounted is mounted on a package 8 and the ceramic substrate 4
The upper bonding pad 6 and the bonding pad 7 of the package 8 are connected by a bonding wire 5 such as an Au wire. Finally, the entire surface is covered with resin (not shown in FIG. 1) to protect the surface.

The package 8 is provided with package pins 9 connected to each bonding pad 7. Thus, the circuit elements of the semiconductor chip 1 are connected to external circuits via the package pins 9.

[0007]

However, the above-mentioned conventional hybrid IC 10 requires a wire bonding step for connecting the ceramic substrate 4 and the package 8. Therefore, there is a problem that the number of processes increases and the manufacturing cost increases. Also,
When a high-frequency signal is transmitted through the bonding wire 5 or the package pin 9, the operation characteristics of the hybrid IC 10 may be adversely affected. Further, the size of the semiconductor chip 1 increases because the capacitor built in the semiconductor chip 1 increases, and it is difficult to reduce the cost and achieve the miniaturization.

The present invention has been made in view of the above problems, and enables miniaturization of a semiconductor chip without using a package or performing a wire bonding process for connecting a package and a substrate. It is an object to provide an ultra-small and low-cost hybrid IC.

[0009]

SUMMARY OF THE INVENTION The hybrid I of the present invention
C is a substrate, at least one inductor formed on the substrate, a semiconductor chip arranged on the substrate by a flip chip method, and at least one terminal formed at a predetermined position on the outer periphery of the substrate. And a semiconductor integrated circuit having a plurality of circuit elements therein, at least one of the circuit elements having a metal-insulating film-metal (MIM) configuration. In addition, the insulating film is a MIM capacitor formed of a high dielectric material, and the above-mentioned object is achieved thereby.

In one embodiment, the semiconductor device further includes at least one matching circuit for matching an input signal to the circuit element inside the semiconductor chip, and the matching circuit includes at least one inductor.

In another embodiment, a wiring pattern is formed by a single metal layer on each surface of the substrate,
The wiring patterns on each surface of the substrate are connected to each other by through holes, and the inductor included in the matching circuit is formed in the wiring pattern on one surface of the substrate.

[0012] In still another embodiment, the matching circuit includes only inductors, and includes at least one series inductor and at least one parallel inductor. Preferably, the parallel inductor included in the matching circuit is a spiral inductor, and an outermost peripheral line of a spiral portion of the spiral inductor is grounded.

In still another embodiment, the inductor constituting the matching circuit is a spiral inductor or a meander inductor.

In still another embodiment, the matching circuit includes:
The semiconductor chip includes an inductor and a capacitor, and the capacitor is formed inside the semiconductor chip. Preferably, the inductor forming the matching circuit is a spiral inductor or a meander inductor.

In still another embodiment, the terminals include at least an RF terminal serving as an RF signal input terminal, a LO terminal serving as an LO signal input terminal, an IF terminal serving as an IF signal output terminal, and a ground. And a power supply terminal.

In still another embodiment, among the terminals, a terminal adjacent to the RF terminal, the LO terminal and the IF terminal is the ground terminal or the power supply terminal.

In still another embodiment, the semiconductor chip R amplifies an RF signal input from the RF terminal.
An F amplifier, an LO amplifier that amplifies the LO signal input from the LO terminal, and a mixer that generates an IF signal based on the amplified RF signal and the amplified LO signal.

In still another embodiment, the RF signal is connected between the RF terminal and the RF amplifier to transmit the RF signal.
An RF input matching circuit that matches the amplifier, and an LO input matching circuit that is connected between the LO terminal and the LO amplifier to match the LO signal to the LO amplifier. The LO input matching circuit is
Each includes at least one inductor.

In yet another embodiment, the line width of the inductor included in the RF input matching circuit is larger than the line width of the inductor included in the LO input matching circuit.

[0020] In still another embodiment, the RF input matching circuit includes at least one spiral inductor formed on one surface of the substrate, and the center of the spiral inductor has a through hole and a through hole. It is connected to the RF terminal by a wiring formed on the other surface of the substrate connected to the through hole.

[0021] In still another embodiment, an LC resonance circuit or a 1 / L resonant circuit connected to the coupling section between the RF amplifier and the mixer and the coupling section between the LO amplifier and the mixer, respectively.
A four-wavelength line, the LC resonance circuit or the 1 /
The four-wavelength line includes a high frequency grounding capacitor, which is formed inside the semiconductor chip.

In yet another embodiment, the LC resonance provided in the RF input matching circuit, the LO input matching circuit, the coupling section between the RF amplifier and the mixer, and the coupling section between the LO amplifier and the mixer, respectively. Circuit or 1
The / 4 wavelength lines are respectively provided on the substrate, and the output matching circuit corresponding to the mixer is not provided on the substrate.

In still another embodiment, a ground electrode is arranged on the surface of the substrate at a position corresponding to the mounting position of the semiconductor chip.

In still another embodiment, the line width of the power supply wiring on the substrate is equal to the minimum line width in the substrate.

In still another embodiment, the terminal includes at least one power supply terminal, a plurality of inductors are connected to the same power supply terminal, and the line width of the wiring connecting the plurality of inductors is the substrate. It is a value equivalent to the minimum line width.

In still another embodiment, the inductor on the substrate is provided with a short-circuit conductor that short-circuits adjacent conductors.

In still another embodiment, a plurality of materials having different dielectric constants are used as the high dielectric material.

In still another embodiment, the semiconductor chip is mounted on the substrate using a flip chip bonding technique by a micro bump bonding (MBB) method or a stud bump bonding (SBB) method.

In still another embodiment, the semiconductor chip is fixed to the substrate with a resin.

In still another embodiment, the terminal is concave with respect to a side surface of the substrate.

In still another embodiment, the terminal has a through hole formed in a portion corresponding to the terminal when the substrate is processed, and at least an inner surface of the through hole is covered with a metal film and then the through hole is cut. It is formed by doing. Preferably, the shape of the metal film associated with the terminal on the surface of the substrate is polygonal or circular.

In still another embodiment, the semiconductor device further includes a power electrode and a ground electrode connected to the semiconductor chip provided on one surface of the substrate, wherein at least one of the power electrode and the ground electrode is The power supply electrode and the ground electrode arranged on the other surface of the substrate are connected through a plurality of through holes, respectively.

In still another embodiment, at least one of the terminals is provided at one of four corners of the substrate.

In yet another embodiment, the substrate is made of a material having a high dielectric constant. Preferably, the substrate is a ceramic substrate.

In yet another embodiment, the substrate is made of a material having a low dielectric constant. Preferably, the substrate is a glass epoxy substrate.

In still another embodiment, a pin electrode made of a conductive material having a shape extending outward from the substrate is provided so as to be connected to each of the terminals.

In still another embodiment, a plurality of the MIM capacitors are provided inside the semiconductor chip, and the lower electrodes included in the plurality of MIM capacitors are connected to each other.

In still another embodiment, among the plurality of circuit elements included in the semiconductor chip, a first type of circuit element relating to a signal of a large voltage is attached to an outer edge of the semiconductor chip. Are arranged so as not to be adjacent to
A second type of circuit element responsible for the small voltage signal is arranged between the first type of circuit element.

In still another embodiment, among the plurality of circuit elements included in the semiconductor chip, the first type circuit elements having high characteristic impedance are not adjacent to each other at the outer edge portion of the semiconductor chip. And the circuit element of the second type having a low characteristic impedance is
Are placed between different types of circuit elements.

In still another embodiment, the semiconductor device further comprises a resin layer having a flat upper surface covering the surface of the substrate on which the semiconductor chip is disposed, and the semiconductor chip is covered with the resin layer.

[0041]

The hybrid I according to the present invention as defined in claim 1
In C, terminals are formed directly on the outer periphery of the substrate on which the semiconductor chips are arranged. This terminal is used to connect a circuit inside the hybrid IC to an external circuit. This eliminates the need for wire bonding and packaging related to the connection with external circuits as in the past.
The number of manufacturing steps is minimized, and cost reduction and miniaturization are possible. Further, there is no adverse effect of the bonding wire or the package on the operating characteristics in terms of high frequency, and a hybrid circuit having excellent characteristics can be realized. Further, in the hybrid IC of the present invention defined in claim 1, a large-capacity MIM capacitor using a high dielectric material is built in a semiconductor chip. Therefore, it is not necessary to mount the capacitive element as a chip component on the substrate, and the substrate area can be reduced. A super-compact and low-cost hybrid IC can be realized by a combination of the above operations.

The hybrid IC according to the present invention is provided with a matching circuit for matching an input signal to a circuit element inside the semiconductor chip. Thereby, impedance matching can be obtained, and good operation characteristics can be obtained.

According to the hybrid IC of the present invention defined in claim 3, the inductor included in the matching circuit is:
It is formed not on the semiconductor chip but on one surface of the substrate. This can prevent an increase in the size of the semiconductor chip.

In the hybrid IC according to the present invention defined in claim 4, the matching circuit has a configuration including only an inductor. This reduces the required number of inductors and occupied area. This makes it possible to reduce the size of the hybrid IC and obtain an excellent image frequency suppression ratio and isolation characteristics.

In the hybrid IC of the present invention defined in claim 5, the outermost peripheral wire of the spiral inductor is grounded. As a result, the voltage of the outermost peripheral line of the spiral type inductor approaching other wirings can be suppressed low. As a result, coupling to other signal lines can be prevented, and excellent isolation characteristics can be obtained.

On the other hand, in the hybrid IC according to the present invention as defined in claim 7, the matching circuit includes an inductor and a capacitor, and the capacitor is formed inside the semiconductor chip. This can reduce the required number of inductors, but does not increase the board area. For this reason,
A smaller hybrid IC can be realized.

The inductor included in the matching circuit is
It can be spiral or meander type. In the spiral type, the inductance value per unit area can be increased. On the other hand, in the meander type, the number of through holes is reduced.

In the hybrid IC according to the present invention as defined in claim 10, of the terminals formed on the outer periphery of the substrate,
A ground terminal or a power supply terminal is arranged as a terminal adjacent to an RF terminal, an LO terminal, and an IF terminal involved in inputting and outputting a high-frequency signal. As a result, the high-frequency signal input / output terminal is sandwiched by the low-impedance terminals, and interference between high-frequency signals can be eliminated. Further, even if a high frequency signal such as an RF signal leaks from the RF terminal or the like, it can be escaped to the ground at a high frequency, so that the isolation characteristic between the high frequency signal input / output terminal and other terminals is improved. As a result, the hybrid IC can be downsized while maintaining excellent characteristics.

In the hybrid IC according to the present invention, the line width of the inductor included in the RF input matching circuit is made larger than the line width of the inductor of the LO input matching circuit. As a result, while the line width of the RF input matching circuit in which the increase in the wiring resistance affects the input loss is increased, the line width of the LO input matching circuit in which the loss due to the increase in the wiring resistance is small can be reduced. Therefore, the outer dimensions of the inductor can be further reduced, and a smaller hybrid IC can be realized.

In the hybrid IC of the present invention as defined in claim 14, the wiring connecting the RF input matching circuit and the RF terminal is passed through the surface of the substrate opposite to the side where the RF input matching circuit is formed. As a result, it is possible to prevent a signal line related to an RF signal that is a high-frequency signal from being coupled to another signal line, and to obtain excellent isolation characteristics.

In the hybrid IC according to the present invention, an LC resonance circuit including a high-frequency grounding capacitor or a 波長 wavelength line is provided at a coupling point between the RF amplifier and the mixer and between the LO amplifier and the mixer. I have. As a result, current consumption in the semiconductor chip is reduced.
Further, since the high-frequency grounding capacitor is provided inside the semiconductor chip, there is no need to form a capacitance on the substrate, and the size of the substrate can be reduced.

In the hybrid IC according to the present invention, only the output matching circuit corresponding to the mixer is not provided on the substrate on which the hybrid IC is formed. This prevents an increase in substrate size and cost.

In the hybrid IC according to the present invention as defined in claim 17, a ground electrode is arranged on the surface of the substrate corresponding to the mounting position of the semiconductor chip. Thus, the ground electrode is arranged between the input terminal side and the output terminal on the substrate surface. As a result, the input and the output can be separated at high frequencies, so that excellent isolation characteristics can be obtained.

In the hybrid IC according to the present invention as defined in claim 18, the line width of the power supply line is set to a narrow value equal to or less than the line width of the LO signal line. As a result, it is possible to reduce the influence between the elements connected to the same power source, which occurs through the power source line, so that a hybrid IC having excellent characteristics can be realized.

In the hybrid IC of the present invention defined in claim 19, the power supply wiring connected to each of the plurality of inductors has a value equivalent to the minimum line width in the substrate.
As a result, the interaction between the inductors can be suppressed.

In the hybrid IC according to the present invention as defined in claim 20, a short-circuit wire is provided for the inductor. By appropriately cutting the short-circuit wiring, the inductance value can be adjusted with a simple configuration, and the desired gain and gain can be adjusted.
Noise characteristics can be obtained.

In the hybrid IC according to the present invention as defined in claim 21, a high dielectric material for forming the insulator film is selected from a plurality of materials according to the size and precision of the formed capacitance. Thus, the size and accuracy of the semiconductor chip can be reduced.

In the hybrid IC according to the present invention, the area of the bonding pads on the semiconductor chip and the ceramic substrate is reduced by adopting the flip chip bonding by the MBB method or the SBB method. At the same time, since the bonding pad position on the ceramic substrate can be arranged on the lower surface of the chip, the ceramic substrate can be downsized.

In the hybrid IC according to the present invention as defined in claim 23, the adhesion between the semiconductor chip and the substrate increases as the resin cures. Therefore, the adhesion strength between the semiconductor chip and the ceramic substrate and the reliability of the semiconductor chip can be improved at the same time. In addition, it is possible to lower the contact resistance value of the connection portion and to ensure reliable electrical conduction.

In the hybrid IC according to the present invention as defined in claim 24, when the board and the printed board are connected by soldering, the solder is taken into the recess of the terminal. As a result, stable soldering can be performed.

According to the hybrid IC of the present invention defined in claim 25, the terminals of the substrate can be easily formed, and a low-cost hybrid IC can be realized.

In the hybrid IC according to the present invention, the area of the metal film portion formed on the substrate surface adjacent to the terminal and functioning as a part of the terminal is reduced.
Thus, a low-cost hybrid IC is realized.

In the hybrid IC of the present invention defined in claim 27, the areas of the power supply electrode and the ground electrode are reduced. As a result, the substrate can be downsized.

By forming the terminals at the four corners of the substrate as defined in claim 28, the terminal area is reduced and the substrate is miniaturized.

If a high dielectric material is used for the substrate as defined in claim 29, the effect of phase rotation due to the length of the transmission line is increased, and the area of the inductor can be reduced. On the other hand, if a low dielectric material is used for the substrate, the resonance frequency of the spiral inductor can be improved. Alternatively, since the wiring interval can be reduced, the area occupied by the inductor required to obtain the same inductance value is reduced.

In the hybrid IC according to the present invention, the conventional solder mounting process can be applied to the mounting of the hybrid IC on the circuit board by using the pin electrodes, thereby suppressing an increase in assembly cost. Is done.

In the hybrid IC of the present invention defined in claim 34, a plurality of MIs formed in the semiconductor chip are provided.
By connecting the lower electrodes of the M capacitors to each other, parasitic capacitance is not formed on the substrate side. As a result, adverse effects on operating characteristics are suppressed.

In the hybrid IC according to the present invention as defined in claim 35 or 36, coupling between circuit elements related to a high-frequency signal is prevented.

In the hybrid IC of the present invention defined in claim 37, by forming the resin layer having a flat upper surface, the conventional inserter can be used for mounting the hybrid IC on the circuit board, and the assembling cost can be improved. Increase is suppressed.

[0070]

【Example】

(Embodiment 1) Hereinafter, a hybrid IC according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 2 shows a hybrid IC 10 of this embodiment.
FIG. In FIG. 2, the ceramic substrate 12
On the surface of 2, spiral type inductors 102 to 107 are formed by a single layer wiring of a metal thin film. Each of the inductors 102 to 107 has a through hole 114 to
The wiring pattern 119 is connected to a wiring pattern (not shown in FIG. 2) formed on the back surface of the ceramic substrate 122. The connection between the ceramic substrate 122 and the external circuit is performed by connecting the terminal 108 formed in a concave shape to the end surface of the ceramic substrate 122.
To 113.

The terminals 108 to 113 are formed, for example, as follows. The ceramic substrate 122 is obtained by dividing a substrate having a large area by predetermined lines.
Prior to this dividing step, a plurality of through holes are provided along the position corresponding to the dividing line, and the inner surface of the through holes is plated with Au. After that, the substrate is divided along a dividing line passing through these through holes. by this,
The Au-plated through-hole is divided to obtain terminals 108 to 113. From this, each terminal 108 ~
The Au plating layer 1 for ensuring the electrical continuity is provided on the surface adjacent to each of the terminals 108 to 113 on the front surface of the substrate 113 and the front and back surfaces of the ceramic substrate 122.
08a to 113a are formed.

In FIG. 2, each of the terminals 108 to 113
Has a shape in which a semi-cylindrical portion having a semi-circular cross section is removed from the ceramic substrate 122. However, the shape is not limited to this. For example, a terminal having a shape in which a prismatic portion such as a quadrangle in cross section is removed from the ceramic substrate 122 may be formed. However,
In the case where the terminals 108 to 113 are formed by the above-described method, by simplifying the forming process and increasing the accuracy of the formed shape by setting the terminal shape as shown in FIG. .

The terminals 111 to 113 adjacent to the high frequency signal input / output terminals 108 to 110 are arranged so as to be the low impedance power supply terminal 111 or the ground terminals 112 and 113. This corresponds to each of the terminals 108-1.
This is to prevent high-frequency coupling between 13.

On the surface of the ceramic substrate 122, GaAs
A semiconductor chip 101 such as an sIC chip is mounted face-down. The surface of the semiconductor chip 101 (FIG. 2)
(Not shown), a capacitive element using a high dielectric constant material, a resistance element made by an ion implantation method or a thin film forming method, and a FET are formed. Semiconductor chip 101
Through holes 111b and 112b are provided adjacent to the. The through hole 111b is formed on the ceramic substrate 1
It is connected to the power supply terminal 111 via a wiring pattern provided on the back surface of 22. Similarly, through hole 112
b is connected to the ground terminals 112 and 113 via a wiring pattern provided on the back surface of the ceramic substrate 122. The semiconductor chip 101 further includes an RF (Radio Fr
equency) signal line 130 and LO (Local Oscillator)
The signal lines 131 are connected to the through holes 114 and 116. These through holes 114, 116
Are connected to the RF terminals 108 and L via a wiring pattern provided on the back surface of the ceramic substrate 122, as described later.
Each is connected to the O terminal 109.

Inductor 103 having spiral structure
In this case, since the outermost peripheral wire of the spiral is connected to the ground terminal 112 and grounded, the impedance becomes lower from the center of the spiral toward the outer periphery. Therefore, for example, the LO leakage power generated in the semiconductor chip 101 is RF
Even when the signal propagates through the signal line 130, the LO leakage power is not directly coupled to the RF terminal 108 due to the shielding effect of the inductor 103 adjacent to the RF signal line 130 by the low impedance line.

FIG. 3 shows the ceramic substrate 12 shown in FIG.
2 is a top view of FIG. However, the state before mounting the semiconductor chip 101 depicted in FIG. 2 is shown. The same components as those in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will not be repeated.

As shown in FIG. 3, a ground electrode 140 is provided at a position corresponding to the mounting portion of the semiconductor chip. The ground electrode 140 is connected to the ground terminals 112 and 113 provided on the end surface of the ceramic substrate 122 via the through holes 112b. By providing the ground electrode 140 in this manner, the RF signal and the LO signal are electrically separated. Therefore, from the LO signal to RF
Leakage power to the signal is reduced.

In the spiral type inductors 102 to 107, the short-circuit conductor 150 is provided between the adjacent conductors. By appropriately cutting the short-circuit conductor 150 using a laser trimming device or the like, the inductance value can be easily finely adjusted.

In the inductors 102 and 103 included in the RF input matching circuit described later, the wiring resistance thereof affects the input loss. Therefore, in order to reduce the wiring resistance,
The wiring width and the wiring interval are each set to 50 μm. On the other hand, the inductors 105 and 106 and the interstage load inductor 104 included in the LO input matching circuit described later,
In 107, the loss is less of a problem, so
In order to reduce the area occupied by the inductor, the wiring width and the wiring interval are set to 30 μm to reduce the size of the ceramic substrate 122.

FIG. 4 is a rear view of the ceramic substrate 122. However, for the sake of clarity, FIG. 4 is drawn as a perspective view so that the vertical and horizontal directions of the drawn ceramic substrate 122 are the same as those shown in FIGS. 2 and 3. Further, in FIG. 4, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals.

The wiring pattern on the back surface of the ceramic substrate 122 and the flow of input signals will be described below with reference to FIGS. 3 and 4.

The RF signal input from the RF terminal 108 is transmitted to the inductors 102, 103 on the front surface of the substrate 122 through the through holes 114, 115 connected by the signal line 108c provided on the back surface of the substrate 122. . Further, from the inductor 102, the RF signal line 130
Is input to the RF input terminal of the semiconductor chip 101.

The LO signal input from LO terminal 109 is transmitted to inductors 105 and 106 on the surface of substrate 122 through through holes 116 and 117 connected by signal lines 109c provided on the back surface of substrate 122. . Further, from the inductor 105, the LO signal line 131
Through the LO input terminal of the semiconductor chip 101.

The power supply terminal 111 is connected to the power supply terminal of the semiconductor chip 101 via the through hole 111b connected by the signal line 111c provided on the back surface of the substrate 122. Further, a ground wiring pattern 112c connected to the ground terminals 112 and 113 is provided so as to cover most of the back surface of the ceramic substrate 122.

FIG. 5 is a sectional view taken along the line AA ′ of FIG. Also in FIG. 5, the same components as those in FIGS. 2 to 4 are denoted by the same reference numerals. Further, a metal wiring pattern provided on the surface of the ceramic substrate 122 individually shown in the previous figures, and a through hole 111
b, 112b connected to the ceramic substrate 1
The metal wiring patterns provided on the back surface of 22 are generically indicated by reference numerals 302 and 303 in FIG.

After bonding the Au bump 301 to the bonding pad on the chip, the semiconductor chip 101 is fixed at a predetermined position on the ceramic substrate 122 with the chip surface facing down. The semiconductor chip 101 is fixed to the ceramic substrate 122 by irradiating ultraviolet rays with a photocurable resin 304 for fixing. Due to the contracting force of the photocurable resin 304 at this time, the Au bumps 301 are connected to the metal wiring 302 on the surface of the ceramic substrate 122 with a low contact resistance value.

In fixing the semiconductor chip 101,
The resin is cured while pressing the semiconductor chip 101 toward the ceramic substrate 122. Since the photocurable resin used in the above cures in a short time, there is little possibility that the semiconductor chip 101 is damaged in the above process.
Alternatively, a thermosetting resin or a quick-drying resin can be used instead of the photocurable resin.

FIG. 6 is a circuit diagram of the hybrid IC and peripheral circuits of this embodiment. 6, parts corresponding to the terminals 108 to 113 in FIGS. 2 to 4 are indicated by the same reference numerals.

As shown in FIG. 6, the ceramic substrate 1
The semiconductor chip 101 including an RF amplifier 430, an LO amplifier 431, and a mixer 432 is provided on the semiconductor chip 22.
Are mounted by the flip chip method. Also, R
F input matching circuit 439, LO input matching circuit 440, RF
The load inductor 104 of the amplifier 430 and the load inductor 107 of the LO amplifier 431
2 is further formed. The load inductor 104 of the RF amplifier 430 and the load inductor 107 of the LO amplifier 431 are both connected to the power supply terminal 111.

The RF input matching circuit 439 is of a type called "series-parallel type", and is of the signal line 108c.
, And a parallel inductor 103 provided in parallel between the signal line 108c and the ground electrode 456. L
The O input matching circuit 440 is also of the same “series-parallel type”, and is provided in parallel between the series inductor 105 connected in series to the signal line 109 c and the ground electrode 456. It is composed of a parallel inductor 106.

In FIG. 6, the parallel inductors 103 and 106 are connected.
Are located near the input side of each matching circuit.
Alternatively, the series inductors 102 and 105 may be arranged close to the input side of each matching circuit.

In the hybrid IC of this embodiment, the DC blocking capacitor 40 connected to the input line to the RF amplifier 430
9, the connection capacitance 411 between the RF amplifier 430 and the mixer 432, the DC blocking capacitance 410 connected to the input line to the LO amplifier 431, and the LO amplifier 431 and the mixer 432.
And the connection capacitance 412 between them is integrated inside the semiconductor chip 101.

Further, the load inductor 104 of the RF amplifier 430 and the load inductor 107 of the LO amplifier 431
A grounding capacitance 407 for grounding the power source end of the
Similarly, 408 is integrated inside the semiconductor chip 101. The ground capacitors 407 and 408 are formed using a high dielectric material as an insulating film.

The RF amplifier 430 includes a bias resistor 41
Dual gate F self biased by 3,416
ET401. Similarly, the LO amplifier 4
Reference numeral 31 denotes a dual-gate FET 402 which is self-biased by bias resistors 414 and 417. Further, the mixer 432 includes bias resistors 415,
It is composed of a dual gate FET 403 self-biased by 18, 419. Source terminals of the dual gate FETs 401 to 403 are grounded at high frequencies by grounding capacitors 404 to 406 made of a high dielectric material.

IF converted by mixer 432
The (Intermediate Frequency) signal is matched with the characteristic impedance of the external circuit system by the IF output matching circuit 451 provided outside the ceramic substrate 122 provided with the hybrid IC of this embodiment. Then I
It is output from the F output terminal 454. IF output matching circuit 4
Reference numeral 51 denotes an inductor 446 connected in parallel between the power supply 455 and the signal line, a ground capacitance 448 connected in parallel between the signal line and the ground electrode 456, and a signal line connected in series. It is composed of an inductor 447 and a capacitor 449 that are present.

The power supply 455 and the ceramic substrate 122
A grounding capacitor 450 is connected to a power supply line connecting the power supply terminal 111 to the power supply terminal 111.

In this embodiment, in order to connect a circuit element inside the semiconductor chip 101 and another circuit element on the ceramic substrate 122, a micro bump bonding method (M
The semiconductor chip 101 is mounted face down on the ceramic substrate 122 using the BB method). Specifically, Au bumps are bonded onto the bonding pads 420 to 429 of the semiconductor chip 101, and the surfaces of the semiconductor chip 101 face down and are accurately arranged at the bonding pad positions of the ceramic substrate 122. After that, as described above with reference to FIG. 5, the semiconductor chip 101 is fixed on the ceramic substrate 122 with a resin, for example, a photocurable resin. In addition,
In mounting, a stud bump bonding method (SBB method) can be used instead of the MBB method.

In this embodiment, typically, the frequency of the RF signal is 880 MHz, and the frequency of the LO signal is 790 MHz.
Hz and the frequency of the IF signal is 90 MHz. As described above, since the frequency of the IF signal is much lower than the frequency of the RF signal or the LO signal, the inductance values of the inductors 446 and 447 forming the IF output matching circuit 451 are equal to those of the inductor included in the RF input matching circuit 439. 10
2, 103, and the inductance values of the inductors 105 and 106 included in the LO input matching circuit 440 are 10 times or more. For this reason, forming the IF output matching circuit 451 on the ceramic substrate 122 results in an extremely large substrate area, resulting in an increase in cost.

In this embodiment, both the high performance and the low cost can be realized by forming only the circuit portion on which a great effect can be obtained by forming the circuit portion on the ceramic substrate 122 by integrating the circuit portion on the substrate 122. ing.

Note that the line width of the power supply wiring provided on the ceramic substrate 122 is made equal to the minimum line width in the substrate. The power supply terminal 111 has a load inductor 104 of the RF amplifier 430 and a load inductor 10 of the LO amplifier 431.
7 are connected together but these inductors 10
The line width of the wiring connecting the wirings 4 and 107 is also made equal to the minimum line width in the substrate.

FIG. 7 is a plan view showing a specific arrangement of circuit elements of the semiconductor chip 101 corresponding to the circuit diagram shown in FIG. 7, the same circuit elements as those in FIG. 6 are denoted by the same reference numerals.

In the semiconductor chip 101, the MESFET and the resistance element are formed on the GaAs substrate 200 by using the ion implantation method. On the other hand, an MIM structure is adopted for the capacitance element, and two types of materials are selectively used for the insulating film. That is, a part that requires a large capacitance value,
Specifically, the grounding capacitor 40 that grounds the load inductors 104 and 107 of the RF amplifier 430 and the LO amplifier 431 is grounded.
7, 408, etc., have a relative dielectric constant of 1 which is a high dielectric constant material.
A strontium titanate film of about 20 is used.
On the other hand, a silicon nitride film having a relative dielectric constant of about 7, which is a low dielectric constant material, is used for other capacitances that require precision in capacitance value. This is because the thickness of the silicon nitride film can be controlled more reliably, so that the value of the formed capacitance can be controlled more accurately. However, usable materials are not limited to the above. For example, barium strontium titanate (B
aSrTiO) or tantalum oxide (TaO) can be used, and silicon oxide (Si) is used as the low dielectric constant material.
O ₂ ) or silicon oxynitride (SiON) can be used.

Further, the hybrid IC 100 of the present embodiment.
In order to prevent coupling between different signals, a portion where a signal voltage is relatively high and a portion where a signal voltage is relatively low are arranged separately from each other in the semiconductor chip 101. That is,
Portions having a high signal voltage and high characteristic impedance (first-type circuit elements) are arranged on the outer edge of the semiconductor chip 101 so as to be separated from each other. On the other hand, the portion where the signal voltage and the characteristic impedance are low (the second type circuit element) is arranged inside the semiconductor chip 101 and between the first type circuit elements.

Specifically, in the RF signal system, the bonding pads 420 and 423, the DC blocking capacitance 409, and the F
The ET 401 and the connection capacitor 411, and in the LO signal system, the bonding pads 421 and 424, the DC cutoff capacitor 410, the FET 402 and the connection capacitor 412 are connected to the chip 1.
It is placed outside 01. All of the above circuit elements have high signal voltage and characteristic impedance involved.
On the other hand, the ground capacitance (bypass capacitor), which is a circuit element with low signal voltage and characteristic impedance involved
404 and 405 are arranged between the RF signal system and the LO signal system inside the semiconductor chip.

Also, in the mixer 432, the ground capacitance (bypass capacitor) 40 having a low characteristic impedance is used.
6 are integrated and arranged inside the semiconductor chip 101, and R
The F signal and the LO signal are separated.

With such an arrangement, the RF signal and the LO
Excellent high-frequency characteristics can be obtained by suppressing high-frequency coupling with a signal.

The operation of the hybrid IC 100 according to this embodiment having the above-described configuration will be described with reference to the above-described circuit diagram shown in FIG.

The RF signal input from the RF input terminal 452 is input to the RF input matching circuit 439 via the RF terminal 108, which is one of the terminals provided on the end face of the ceramic substrate 122. After that, it is input to the first gate of the dual gate FET 401 that constitutes the RF amplifier 430, and is amplified by the FET 401. Thereafter, through the connection capacitor 411, the dual gate FET 4
It is input to the first gate of 03.

Similarly, the LO signal input from the LO input terminal 453 is input to the LO input matching circuit 440 via the LO electrode 109 which is one of the terminals provided on the end surface of the ceramic substrate 122. Then, the LO amplifier 43
1 is input to the first gate of the dual-gate FET 402 and amplified by the FET 402. afterwards,
It is input to the second gate of the dual gate FET 403 of the mixer 432 via the connection capacitor 412.

Dual gate FET 40 of mixer 432
Reference numeral 3 converts the frequency of the RF signal and the LO signal, and outputs an IF signal having a sum and difference frequency components of the respective frequencies of the RF signal and the LO signal. The IF signal is an IF terminal 1 which is one of the terminals provided on the end surface of the ceramic substrate 122.
The signal is input to the IF output matching circuit 451 through the IF output terminal 10 and further output from the IF output terminal 454 to a subsequent circuit.

The inductor 1 is placed in the load of the RF amplifier 430.
04, the drain-gate capacitance Cgd of the dual gate FET 401 and the dual gate F
A parallel resonance circuit is formed together with the first gate-source capacitance Cgs of the ET403. Therefore, by adjusting the resonance frequency of the parallel resonance circuit to the frequency of the RF signal, the RF amplifier 430 having a high gain can be configured.

Similarly, for the LO amplifier 431, the inductor load 107, the drain-gate capacitance Cgd of the dual gate FET 402, and the dual gate FET are the same.
An LO amplifier 431 having a high gain is obtained by forming a parallel resonant circuit by the second gate-source capacitance Cgs of 403.

Alternatively, the RF amplifier 430 and the LO
Even if the load inductors 104 and 107 of the amplifier 431 are replaced with quarter-wavelength lines, equivalent performance can be obtained. RF input matching circuit 439 and LO input matching circuit 44
0 is designed based on the same concept. For example,
Taking the RF input matching circuit 439 as an example, the series inductor 102 is connected to the gate terminal of the dual gate FET 401, and the parallel inductor 103 is connected to the input side of the series inductor 102. With this configuration, the inductance values of the inductors 102 and 103 can be made smaller than the inductance value obtained when another matching circuit configuration is adopted. Therefore,
The area occupied by the matching circuit 439 can be reduced.
This is the same for the LO input matching circuit 440.

In this embodiment, spiral inductors are used as the inductors 102 to 107 for the purpose of miniaturization. Alternatively, a meander type inductor may be used. When the spiral type inductor and the meander type inductor are compared, the spiral type is advantageous in characteristics in that the inductance value per unit area can be increased. On the other hand, the meander-type inductor can reduce the number of through holes that need to be formed, so that the cost can be reduced.

The structure of the capacitor in this embodiment will be described below with reference to FIGS. 8 (a) and 8 (b).

FIG. 8A is a cross-sectional view taken along line BB ′ in FIG. 7, and shows the RF amplifier 430 and the LO amplifier 431.
The structure of the ground capacitors 404 and 405 respectively included in FIG. On the other hand, FIG. 8B is a cross-sectional view in the case where the structure of FIG. Note that FIG.
The components shown in (b) are numbered by adding "b" to the reference numbers of the corresponding components in FIG. 8 (a).

In FIG. 8A, a GaAs substrate 200
A first interlayer film 201 is deposited thereon, and a lower electrode 202 patterned to an appropriate size is further formed thereon. The lower electrode 202 has two ground capacitors 404,
405 functions as a ground electrode common to both.

On the lower electrode 202, a high dielectric thin film 203, a capacitor electrode 204 and an upper electrode 205 corresponding to the respective ground capacitors 404 and 405 are provided. A portion other than the portion where the ground capacitors 404 and 405 are formed is covered with the second interlayer film 206, and a protective film 207 is further covered thereon.

On the other hand, in the prior art, as shown in FIG. 8B, a first interlayer film 201b is generally deposited on a GaAs substrate 200b and further patterned thereon to an appropriate size. The lower electrode 202b is separately formed corresponding to each of the ground capacitors 404b and 405b. On each lower electrode 202b, a ground capacitance 404b, 4
A high dielectric thin film 203b and a capacitor electrode 204b corresponding to 05b are formed. Further, the ground capacitors 404b and 40
The portion other than the portion where 5b is formed is covered with the second interlayer film 206b. To cover the above structure,
An upper electrode 205b is provided, and a protective film 2
07b covers.

As described above, in the prior art, the upper electrode 20
5b is shared as a ground electrode. In this case, the parasitic capacitance Cs ′ existing between the lower electrode 202b corresponding to the two ground capacitances 404b and 405b exists on the substrate 200b side as shown in FIG. 8B. This parasitic capacitance Cs' is
Since the substrate 200b has a high dielectric constant, it has a relatively large value and, as a result, two capacitors 404.
b and 405b.

On the other hand, in the present embodiment, the lower electrode 202 is shared between the two ground capacitors 404 and 405 to function as the ground electrode. In this configuration, the parasitic capacitance Cs
Is formed only above the lower electrode 202 as shown in FIG. Therefore, the high dielectric constant of the substrate 200 does not affect the parasitic capacitance Cs. On the contrary, the parasitic capacitance Cs
When a resin corresponding to the formation position is filled with a resin such as an epoxy resin, since the resin generally has a low dielectric constant, the value of the parasitic capacitance Cs can be reduced.

As described above, by forming the capacitor having the structure shown in FIG. 8A, the hybrid IC 100 of this embodiment greatly reduces the high frequency coupling between the ground capacitors 404 and 405. It is possible to improve the high frequency characteristics of the circuit.

In the above description, the ground capacitances 404, 4
05 is taken as an example, but the configuration of the capacitance as shown in FIG. 8A can be applied to other capacitances included in the semiconductor chip 101 in the hybrid IC 100 of this embodiment.

Embodiment 2 Hereinafter, a hybrid IC according to a second embodiment of the present invention will be described with reference to FIG.

FIG. 9 shows a hybrid IC according to the second embodiment.
FIG. 25 is a circuit diagram of a peripheral circuit and a peripheral circuit; FIG. 9 differs from FIG. 6 showing the hybrid IC 100 in the first embodiment in that parallel capacitors 605 and 606 are added to the RF input matching circuit 607 and the LO input matching circuit 608, and
Series inductors 601, 603 and parallel inductor 60
The point that the connection order of 2,604 is reversed. Thus, the RF input matching circuit 607 and the LO input matching circuit 608 each have a “parallel-series inductor + parallel capacitance” configuration. 6 and 9, the same components are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The RF input matching circuit 607 includes a series inductor 601, a parallel inductor 602, and a parallel capacitor 605.
The configuration is as shown in FIG. Similarly, the LO input matching circuit 608 includes a series inductor 603, a parallel inductor 604, and a parallel capacitor 606, as shown in FIG.
It is configured as shown in FIG.

In the configuration of the RF input matching circuit 607 and the LO input matching circuit 608,
Reference numeral 604 denotes a ceramic substrate 4 outside the semiconductor chip 457.
Parallel capacitors 605 and 606 formed on 58
Are integrated inside the semiconductor chip 457, respectively. Specifically, MIM using silicon nitride as an insulating film
It is formed using a capacitor. With this configuration, the inductance values of the parallel inductors 602 and 604 can be reduced, so that the ceramic substrate 458 can be downsized and the ability to eliminate the interference due to the IF signal having the image frequency is enhanced.

Embodiment 3 Hereinafter, a hybrid IC according to a third embodiment of the present invention will be described with reference to FIG.

FIG. 10 is a top view of a ceramic substrate included in the hybrid IC 300 according to the third embodiment. However, this shows a state before the semiconductor chip is mounted.
Note that the same components as those of the first embodiment shown in FIG. 3 are denoted by the same reference numerals, and a detailed description thereof will be omitted here.

As shown in FIG. 10, in the hybrid IC 300 of this embodiment, meander-type inductors 701 to 70 are used instead of some of the spiral-type inductors in the hybrid ICs 100 and 250 of the first and second embodiments.
Use 4 In the inductors 102 and 701 of the RF input matching circuit that require low loss, the wiring width and the wiring interval are set to 50 μm in order to reduce the wiring resistance. On the other hand, since the loss of the inductors 105 and 703 and the interstage load inductors 702 and 704 of the LO input matching circuit does not matter so much, the wiring width and the wiring interval are set to 30 μm in order to reduce the occupied area of the inductor. The size of the ceramic substrate has been reduced.

In each of the meander type inductors 701 to 704 and the spiral type inductors 102 and 105, short-circuit conductors 712 and 150 are provided between adjacent conductors. By appropriately cutting the short-circuit conductors 712, 150 with a laser trimming device or the like, the inductance values of the inductors 102, 105, 701 to 704 can be easily finely adjusted.

By using the meander type inductors 701 to 704, the number of through holes to be formed can be reduced. Therefore, the manufacturing cost can be reduced.

On the other hand, in this embodiment, the ground electrode 710 formed near the mounting position of the semiconductor chip
The through holes 705 and 706 are provided. Similarly, two through holes 707,
708 is provided. These through holes 705-7
08, the ground electrode 710 and the power electrode 711,
Each is connected to a predetermined wiring pattern provided on the other surface of the ceramic substrate. At this time, as shown in FIG. 10, by using a plurality of small through holes, the inductance of the through holes can be reduced, and at the same time, the size of the ceramic substrate can be reduced.

The formation of such a plurality of through holes is not limited to the hybrid IC including the meander type inductor described in this embodiment. The present invention is also applicable to a hybrid IC including only a spiral inductor as described in other embodiments.

(Fourth Embodiment) FIG. 11 is a top view showing the structure of a hybrid IC 400 according to a fourth embodiment of the present invention. FIG. 12 is a circuit diagram of the hybrid IC 400 shown in FIG.

In the hybrid IC 400 of this embodiment,
A part of the terminals formed on the end surface of the substrate 530 is removed from the substrate 530.
Not on the sides, but on the four corners. Specifically, the RF terminal 501, the LO terminal 503, the power terminals 502 and 504
Are provided at four corners of the substrate 530. On the other hand, IF terminal 5
06 and the ground terminal 505 are provided on the side of the substrate.
As described above, by forming some of the terminals formed at the ends of the substrate 530 at the four corners of the substrate, the required area of the substrate 530 can be reduced.

On the upper surface of the substrate 530, circuit elements including the spiral type inductors 102 to 107 are formed. The circuit element formed here is a resistive element 5 described later.
Except for 20, 521, the hybrid IC 100 is the same as the hybrid IC 100 of the first embodiment described above with reference to FIG. 3, and therefore detailed description thereof will be omitted here. Further, the actual arrangement of each circuit element on the surface of the substrate 530 may be optimized in consideration of the area of the substrate 530 to be used.

The hybrid IC of this embodiment shown in FIG.
Is basically the same as the circuit configuration of the first embodiment described above with reference to FIG. The difference is the RF
Load inductor 104 of amplifier 430 and LO amplifier 4
This is the point that the resistance elements 520 and 521 are connected in parallel to the 31 load inductors 107 respectively. Thereby, the load inductor 104 or the load inductor 1
It is possible to freely adjust the Q value of the resonance circuit configured by 07 and to prevent the oscillation of the circuit. The resistance elements 520 and 5 included in FIG.
The circuit elements other than 21 are the same as those in the case of the hybrid IC 100 of the first embodiment described with reference to FIG.

As described above, according to this embodiment, the size of the substrate 530 can be reduced.

(Fifth Embodiment) FIG. 13 is a perspective view of a hybrid IC 500 according to a fifth embodiment of the present invention.

In the hybrid IC 500 of this embodiment,
Terminal pins 108 made of a conductive material such as a metal or a metal compound are further connected to the terminals 108 to 113 provided at the ends (that is, along the sides) of the ceramic substrate 122. As a material for the terminal pin, a copper alloy generally used for a semiconductor lead frame is suitable.

More specifically, in the configuration of the hybrid IC 100 of the first embodiment described above with reference to FIG. 2, each of the terminals 108 to 113 is replaced with a prism-shaped portion removed from the substrate 122. It is formed so as to have an appropriate shape. Then, the terminal pins having a shape extending outward from the substrate 122 while filling the recesses of the respective terminals are further connected to the terminals 103 to 108.

By providing the terminal pins having such a shape, the hybrid IC 50 can be formed by conventional solder mounting.
0 can be mounted on a circuit board, and an increase in assembly cost can be suppressed.

In FIG. 13, the same components as those in FIG. 2 are designated by the same reference numerals. Although some arrangements are different, their functions and obtained characteristics are the same, and thus detailed description thereof is omitted here.

(Embodiment 6) FIG. 14 is a sectional view showing a configuration of a hybrid IC 600 of this embodiment. 14
5 corresponds to FIG. 5 described above in connection with the first embodiment. The same components are denoted by the same reference numerals, and a detailed description thereof will not be repeated.

The hybrid ICs 100 to 500 of the first to fifth embodiments described above are in a state in which a semiconductor chip is mounted on a ceramic substrate, and no subsequent steps are performed. On the other hand, in the present embodiment, as shown in FIG. 14, after the semiconductor chip 101 is flip-chip bonded on the ceramic substrate 122, the resin is further filled on the ceramic substrate 122 to form the resin layer 610. At this time, the resin layer 610
Is flattened. The resin layer 610 is formed so as to cover at least the semiconductor chip 101 and the spiral inductor formed on the surface of the ceramic substrate 122. As a material for the resin layer 610, for example, an epoxy resin, a silicone resin, or the like can be used.

As a result, the inserter can be used when the hybrid IC 600 is mounted on a circuit board or the like, and the productivity is improved. Further, as described above with reference to FIGS. 8A and 8B in relation to the first embodiment, when the resin 610 is filled in this way, even if a parasitic capacitance is generated, the capacitance is not changed. The value can be reduced.

The formation of the resin layer 610 is not limited to the hybrid IC 100 described in the first embodiment.
Can be similarly applied to.

In the first to sixth embodiments described above,
In each case, the hybrid IC of the present invention is formed on a ceramic substrate having a relatively high dielectric constant. Alternatively, instead of the ceramic substrate, a substrate formed of a material having a low dielectric constant, for example, a glass epoxy substrate (dielectric constant: 4.0) can be used.

By using a substrate made of a material having such a low dielectric constant, the resonance frequency of the spiral type inductor can be improved. As a result,
It can be used in a higher frequency band as compared with the case where the ceramic substrate as described above is used. Alternatively, when used in the same frequency band, the area occupied by the spiral inductor can be reduced without lowering the resonance frequency.

[0152]

As described above, according to the hybrid IC of the present invention defined in claim 1, the hybrid IC
By forming terminals for connecting a circuit inside C to an external circuit directly on the outer periphery of the substrate on which the semiconductor chip is arranged, wire bonding and a package related to connection with an external circuit as in the related art become unnecessary. Therefore, the number of manufacturing steps is minimized, and cost reduction and miniaturization are possible. Further, there is no adverse effect of the bonding wire or the package on the operating characteristics in terms of high frequency, and a hybrid circuit having excellent characteristics can be realized. Further, since a large-capacity MIM capacitor using a high-dielectric material is built in the semiconductor chip, it is not necessary to mount a capacitance element as a chip component on the substrate, and the substrate area can be reduced. By combining the above points, an ultra-compact and low-cost hybrid IC can be realized.

By providing the matching circuit for matching the input signal to the circuit element inside the semiconductor chip as defined in claim 2, impedance matching can be obtained and good operating characteristics can be obtained.

The inductor included in the above matching circuit is
By forming the semiconductor chip not on the semiconductor chip but on one surface of the substrate as defined in claim 3, an increase in the size of the semiconductor chip can be prevented.

The number of required inductors and the occupied area are reduced by configuring the matching circuit to include only inductors as defined in claim 4. This makes it possible to reduce the size of the hybrid IC and obtain an excellent image frequency suppression ratio and isolation characteristics.

As described in claim 5, by grounding the outermost line of the spiral inductor, the voltage of the outermost line of the spiral inductor approaching another wiring can be suppressed low. As a result, coupling to other signal lines can be prevented, and excellent isolation characteristics can be obtained.

On the other hand, if the matching circuit is composed of an inductance and a capacitor as defined in claim 7, and the capacitor is formed inside the semiconductor chip, the required number of inductors can be reduced and the substrate area does not increase. . For this reason, a smaller hybrid IC can be realized.

Note that the inductor included in the matching circuit is:
It can be spiral or meander type. In the spiral type, the inductance value per unit area can be increased. On the other hand, in the meander type, the number of through holes is reduced.

As defined in claim 10, among the terminals formed on the outer periphery of the substrate, the ground terminal or the terminal adjacent to the RF terminal, LO terminal and IF terminal involved in inputting / outputting of a high-frequency signal is used. By arranging the power supply terminal, the input / output terminal of the high-frequency signal is sandwiched between the terminals of low impedance, and interference between the high-frequency signals can be eliminated. Further, even if a high frequency signal such as an RF signal leaks from the RF terminal or the like, it can be escaped to the ground at a high frequency, so that the isolation characteristic between the high frequency signal input / output terminal and other terminals is improved. As a result, the hybrid IC can be downsized while maintaining excellent characteristics.

If the line width of the inductor included in the RF input matching circuit is made larger than the line width of the inductor of the LO input matching circuit as defined in claim 13, the increase in wiring resistance affects the input loss. While the line width of the applied RF input matching circuit is increased, the line width of the LO input matching circuit that causes less loss due to an increase in wiring resistance can be reduced, so that the outer dimensions of the inductor can be further reduced. A smaller hybrid IC can be realized.

If the wiring connecting the RF input matching circuit and the RF terminal is wired so as to pass through the substrate surface opposite to the side on which the RF input matching circuit is formed as defined in claim 14, It is possible to prevent coupling between a signal line related to an RF signal which is a high-frequency signal and another signal line. Than this,
It is possible to obtain excellent isolation characteristics.

According to the fifteenth aspect of the present invention, by providing the LC resonance circuit including the high frequency grounding capacitor or the quarter wavelength line at the coupling point of the RF amplifier and the mixer and the LO amplifier and the mixer, Current consumption is reduced. Furthermore, if the high-frequency grounding capacitor is provided inside the semiconductor chip, it is not necessary to form a capacitor on the substrate, and the size of the substrate can be reduced.

By not providing only the output matching circuit corresponding to the mixer on the substrate on which the hybrid IC is formed, an increase in substrate size and an increase in cost can be prevented.

According to a seventeenth aspect of the present invention, when a ground line is arranged on the substrate surface corresponding to the mounting position of the semiconductor chip, the ground line is arranged between the input terminal side and the output terminal on the substrate surface. Therefore, the input and the output can be separated at a high frequency. Therefore, excellent isolation characteristics can be obtained.

If the line width of the power supply line is set to a thin value equal to or less than the line width of the LO signal line, the influence between the elements connected to the same power supply through the power supply line is defined. Can be reduced. Therefore, a hybrid IC having excellent characteristics can be realized.

[0166] As defined in claim 19, by setting the power supply wiring connected to each of the plurality of inductors to a value equivalent to the minimum line width in the substrate, the interaction between the inductors can be suppressed. .

According to the twentieth aspect, by providing the inductor with the short-circuit conductor and cutting the short-circuit wire appropriately, the inductance value can be adjusted with a simple configuration, and the desired gain and noise can be obtained. The characteristics can be obtained.

If a plurality of materials having different dielectric constants are used as the constituent materials of the MIM capacitor formed inside the semiconductor chip as defined in claim 21, depending on the size and accuracy of the formed capacitance, A high dielectric material forming the insulating film can be appropriately selected. Thus, the size and accuracy of the semiconductor chip can be reduced.

When the semiconductor chip is mounted on the substrate by flip chip bonding according to the MBB method or the SBB method as defined in claim 22, the bonding pad area on the semiconductor chip and the ceramic substrate is reduced, and at the same time, The bonding pad position on the ceramic substrate can be arranged on the lower surface of the chip. Therefore, the size of the ceramic substrate can be reduced.

If the semiconductor chip is fixed to the substrate with a resin, the fixing force between the semiconductor chip and the substrate increases with the curing of the resin. The adhesion strength and the reliability of the semiconductor chip can be improved at the same time.
In addition, it is possible to lower the contact resistance value of the connection portion and to ensure reliable electrical conduction.

If the concave terminal is formed as defined in claim 24, the solder is taken into the concave portion of the terminal when the board and the printed board are connected by soldering, and stable soldering is realized.

According to claim 25, the terminals of the substrate can be easily formed, and a low-cost hybrid IC can be realized.

According to the twenty-sixth aspect, the area of the metal film portion formed on the substrate surface adjacent to the terminal and functioning as a part of the terminal is reduced, so that a low-cost hybrid IC is realized.

According to the twenty-seventh aspect, since the areas of the power supply electrode and the ground electrode are reduced, the size of the substrate can be reduced.

When the terminals are formed at the four corners of the substrate as defined in claim 28, the terminal area is reduced and the substrate is downsized.

When a high dielectric material is used for the substrate as defined in claim 29, the effect of phase rotation due to the length of the transmission line is increased, so that the area of the inductor can be reduced. On the other hand, if a low dielectric material is used for the substrate, the resonance frequency of the spiral inductor can be improved. Alternatively, since the wiring interval can be reduced, the area occupied by the inductor required to obtain the same inductance value is reduced.

By using the pin electrode as defined in claim 33, the conventional solder mounting process can be applied when mounting the hybrid IC on the circuit board, and an increase in assembly cost can be suppressed.

If the lower electrodes of a plurality of MIM capacitors formed in a semiconductor chip are connected to each other, no parasitic capacitance is formed on the substrate side. As a result, adverse effects on operating characteristics are suppressed.

By arranging the circuit elements in the semiconductor chip as defined in claim 35 or claim 36, coupling between circuit elements relating to high-frequency signals is prevented.

If a resin layer having a flat upper surface is formed as defined in claim 37, a conventional inserter can be used for mounting the hybrid IC on a circuit board, thereby suppressing an increase in assembly cost. .

[Brief description of drawings]

FIG. 1 is a perspective view showing an example of the configuration of a conventional hybrid IC.

FIG. 2 is a hybrid IC according to a first embodiment of the present invention.
It is a perspective view of.

FIG. 3 is a top view of a ceramic substrate constituting the hybrid IC shown in FIG. 2;

FIG. 4 is a rear view of the ceramic substrate shown in FIG. 3;

FIG. 5 is a cross-sectional view of the hybrid IC shown in FIG. 2 along the line AA ′ in FIG. 2;

FIG. 6 is a circuit diagram of the hybrid IC shown in FIG.

FIG. 7 is a plan view showing an example of an arrangement of circuit elements of a semiconductor chip corresponding to the circuit diagram shown in FIG. 6;

8A is a cross-sectional view taken along the line BB ′ of FIG. 7, showing the configuration of the capacitor in the present embodiment,
(B) is sectional drawing which shows an example of a structure at the time of forming the structure of (a) by the prior art.

FIG. 9 is a hybrid IC according to a second embodiment of the present invention.
It is a circuit diagram of.

FIG. 10 is a hybrid I according to a third embodiment of the present invention.
It is a top view of the ceramic substrate which comprises C.

FIG. 11 shows a hybrid I according to a fourth embodiment of the present invention.
It is a top view of the ceramic substrate which comprises C.

FIG. 12 is a circuit diagram of the hybrid IC shown in FIG. 11;

FIG. 13 shows a hybrid I according to a fifth embodiment of the present invention.
It is a perspective view of C.

FIG. 14 shows a hybrid I according to a sixth embodiment of the present invention.
It is sectional drawing of C.

[Explanation of symbols]

100, 250, 300, 400, 500, 600 Hybrid IC 101, 457 Semiconductor chip 102, 103, 104, 105, 106, 107 Spiral inductor 108, 501 RF terminal 109, 503 LO terminal 110, 506 IF terminal 111, 502 , 504 Power supply terminals 112, 113, 505 Ground terminals 111b, 112b, 114, 115, 116, 11
7, 118, 119 Through hole 108c, 109c, 111c Signal line 112c Ground wiring pattern 122, 458, 530 Ceramic substrate 130 RF signal line 131 LO signal line 140 Ground electrode 150 Short-circuit conductor 200, 200b GaAs substrate 201, 201b First Interlayer film 202, 202b Lower electrode 203, 203b High dielectric thin film 204, 204b Capacitor electrode 205, 205b Upper electrode 206, 206b Second interlayer film 207, 207b Protective film 301 Au bump 302 Metal wiring on the surface of ceramic substrate 303 Ceramic substrate Backside metal wiring 304 Photocurable resin 401, 402, 403 Dual gate FET 407, 408 High dielectric capacitance element 404, 405, 406, 409, 410, 411, 4
12 capacitive elements 413, 414, 415, 416, 417, 418, 4
19 Bias resistors 420, 421, 422, 423, 424, 425, 4
26, 427, 428, 429 Bonding pad 430 RF amplifier 431 LO amplifier 432 Mixer 439 RF input matching circuit 440 LO input matching circuit 451 IF output matching circuit 452 RF input terminal 453 LO input terminal 454 IF output terminal 456 Ground electrode 601, 603 Series inductor 602, 604 Parallel inductor 605, 606 Parallel capacitance 607 RF input matching circuit 608 LO input matching circuit 610 Filled resin layer 701, 702, 703, 704 Meander type inductor 705, 706, 707, 708 Through hole 710 Ground electrode 711 Power supply Electrode 712 short-circuit conductor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuru Nishitsuji 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (37)

[Claims] 1. A substrate, at least one inductor formed on the substrate, a semiconductor chip arranged on the substrate by a flip chip method, and at least one formed at a predetermined position on the outer periphery of the substrate. A hybrid IC including two terminals, wherein the semiconductor chip includes a plurality of circuit elements therein, at least one of the circuit elements having a metal-insulating film-metal (MIM) configuration. A hybrid IC which is a MIM capacitor having the above-mentioned insulating film made of a high dielectric material. 2. The hybrid IC according to claim 1, further comprising at least one matching circuit that matches an input signal to the circuit element inside the semiconductor chip, and the matching circuit includes at least one inductor. 3. A wiring pattern is formed of a single metal layer on each surface of the substrate, and the wiring patterns on each surface of the substrate are connected to each other by through holes. 3. The hybrid IC according to claim 2, wherein the inductor included in the matching circuit is formed in the wiring pattern on one surface of the substrate. 4. The hybrid IC according to claim 2, wherein said matching circuit comprises only an inductor, and includes at least one series inductor and at least one parallel inductor. 5. The hybrid IC according to claim 4, wherein said parallel inductor included in said matching circuit is a spiral inductor, and an outermost peripheral line of a spiral portion of said spiral inductor is grounded. 6. The hybrid IC according to claim 2, wherein the inductor forming the matching circuit is a spiral inductor or a meander inductor. 7. The hybrid I according to claim 2, wherein said matching circuit comprises an inductor and a capacitor, and said capacitor is formed inside said semiconductor chip.
C. 8. The hybrid IC according to claim 7, wherein the inductor forming the matching circuit is a spiral inductor or a meander inductor. 9. The terminal is at least an RF terminal that is an input terminal for an RF signal and an L terminal that is an input terminal for an LO signal.
The hybrid IC according to claim 1, further comprising an O terminal, an IF terminal serving as an output terminal of the IF signal, a ground terminal, and a power supply terminal. 10. The hybrid IC according to claim 9, wherein among the terminals, a terminal adjacent to the RF terminal, the LO terminal and the IF terminal is the ground terminal or the power supply terminal. 11. The semiconductor chip, comprising: an RF amplifier that amplifies an RF signal input from the RF terminal; an LO amplifier that amplifies an LO signal input from the LO terminal; The hybrid IC according to claim 9, further comprising: a mixer that generates an IF signal based on the amplified LO signal. 12. An RF input matching circuit connected between the RF terminal and the RF amplifier to match the RF signal to the RF amplifier; and an RF input matching circuit connected between the LO terminal and the LO amplifier. The hybrid IC according to claim 11, further comprising: a LO input matching circuit that matches a LO signal to the LO amplifier, wherein the RF input matching circuit and the LO input matching circuit each include at least one inductor. 13. The hybrid I according to claim 12, wherein a line width of an inductor included in the RF input matching circuit is larger than a line width of an inductor included in the LO input matching circuit.
C. 14. The RF input matching circuit includes at least one spiral inductor formed on one surface of the substrate, a central portion of the spiral inductor being connected to a through hole and the through hole. 13. The hybrid IC according to claim 12, wherein the hybrid IC is connected to the RF terminal by a wiring formed on the other surface of the substrate. 15. An LC resonance circuit or a quarter-wave line connected to a coupling portion between the RF amplifier and the mixer and a coupling portion between the LO amplifier and the mixer, respectively. 13. The hybrid IC according to claim 12, wherein the quarter wavelength line includes a high-frequency grounding capacitor, wherein the capacitor is formed inside the semiconductor chip. 16. The RF input matching circuit, the LO input matching circuit, a coupling portion between the RF amplifier and the mixer, and the LC resonance circuit or the 1/1 provided in the coupling portion between the LO amplifier and the mixer, respectively. 16. The hybrid IC according to claim 15, wherein the four-wavelength lines are provided on the substrate, respectively, and the output matching circuit corresponding to the mixer is not provided on the substrate. 17. The hybrid IC according to claim 1, wherein a ground electrode is disposed on a surface of said substrate at a position corresponding to a mounting position of said semiconductor chip. 18. The hybrid IC according to claim 1, wherein a line width of the power supply wiring on the substrate is equal to a minimum line width in the substrate. 19. The terminal includes at least one power supply terminal, a plurality of inductors are connected to the same power supply terminal, and a line width of a wiring connecting the plurality of inductors is:
The hybrid IC according to claim 1, which has a value equivalent to the minimum line width in the substrate. 20. The hybrid IC according to claim 1, wherein said inductor on said substrate is provided with a short-circuit conductor between adjacent conductors for short-circuiting them. 21. The hybrid IC according to claim 1, wherein a plurality of materials having different dielectric constants are used as the high dielectric material. 22. The hybrid IC according to claim 1, wherein the semiconductor chip is mounted on the substrate using a flip chip bonding technique by a micro bump bonding (MBB) method or a stud bump bonding (SBB) method. 23. The hybrid IC according to claim 1, wherein the semiconductor chip is fixed to the substrate with a resin. 24. The hybrid IC according to claim 1, wherein the terminal has a concave shape with respect to a side surface of the substrate. 25. The terminal is formed by forming a through hole at a portion corresponding to the terminal when processing the substrate, coating at least an inner surface of the through hole with a metal film, and then cutting the through hole. Claim 1
Hybrid IC. 26. The hybrid IC according to claim 25, wherein the shape of the metal film associated with the terminal on the surface of the substrate is polygonal or circular. 27. A power supply electrode and a ground electrode, which are provided on one surface of the substrate and connected to the semiconductor chip, are further provided, and at least one of the power supply electrode and the ground electrode is the other of the substrate. 2. The hybrid IC according to claim 1, wherein the hybrid IC is connected to the power supply electrode and the ground electrode arranged on the surface of the substrate through a plurality of through holes. 28. At least one of the terminals is:
The substrate is provided at one of the four corners of the substrate.
Hybrid IC. 29. The hybrid IC according to claim 1, wherein the substrate is formed of a material having a high dielectric constant. 30. The hybrid IC according to claim 29, wherein the substrate is a ceramic substrate. 31. The hybrid IC according to claim 1, wherein said substrate is formed of a material having a low dielectric constant. 32. The hybrid IC according to claim 31, wherein said substrate is a glass epoxy substrate. 33. The hybrid IC according to claim 1, further comprising a pin electrode made of a conductive material, the pin electrode having a shape extending outward from the substrate, the pin electrode being connected to each of the terminals. 34. The MI chip is provided inside the semiconductor chip.
The hybrid IC according to claim 1, wherein a plurality of M capacitors are provided, and lower electrodes included in the plurality of MIM capacitors are connected to each other. 35. Of the plurality of circuit elements included in the semiconductor chip, a first type circuit element involved in a high voltage signal is not adjacent to each other at an outer edge portion of the semiconductor chip. 2. The hybrid IC according to claim 1, wherein a second type circuit element that is arranged and is involved in a small voltage signal is arranged between the first type circuit elements. 36. Among the plurality of circuit elements included in the semiconductor chip, a first type of circuit element having a high characteristic impedance is arranged at an outer edge of the semiconductor chip so as not to be adjacent to each other, 2. The hybrid IC according to claim 1, wherein a second type of circuit element having a low characteristic impedance is disposed between said first type of circuit element. 37. The semiconductor device according to claim 37, further comprising a resin layer having a flat upper surface covering a surface of the substrate on which the semiconductor chip is disposed,
The hybrid IC according to claim 1, wherein the semiconductor chip is covered with the resin layer.