JPH0831810A - Method for forming element isolation film - Google Patents

Method for forming element isolation film

Info

Publication number
JPH0831810A
JPH0831810A JP16348394A JP16348394A JPH0831810A JP H0831810 A JPH0831810 A JP H0831810A JP 16348394 A JP16348394 A JP 16348394A JP 16348394 A JP16348394 A JP 16348394A JP H0831810 A JPH0831810 A JP H0831810A
Authority
JP
Japan
Prior art keywords
oxide film
film
locos
element isolation
locos oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16348394A
Other languages
Japanese (ja)
Inventor
Hiroshi Takahashi
洋 高橋
Takashi Noguchi
隆 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16348394A priority Critical patent/JPH0831810A/en
Publication of JPH0831810A publication Critical patent/JPH0831810A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a method for forming a element isolation film wherein degeneration of a bird's beak and drop of Vth are prevented and the flatness is improved. CONSTITUTION:On a silicon substrate 21, a LOCOS oxide film 26 is formed, and after an SiN film, etc., is removed, the LOCOS oxide film 26 is flattened with HF, and then, by performing CMP polishing, the height of the silicon substrate 21 and that of the LOCOS oxide film 26 are equalized. By this, the shoulder parts of the silicon substrate 21 do not protrude itself, so that, electric field concentration is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、素子分離膜の形成方
法に関し、さらに詳しくは、LOCOS酸化膜のバーズ
ビークの縮退化を防止する技術に係る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation film, and more particularly to a technique for preventing degeneracy of bird's beak of a LOCOS oxide film.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】従来、
素子分離に用いられるLOCOS酸化膜では、バーズビ
ークによる寸法変換差が大きいことが知られている。図
3は、所謂ポリパッドLOCOSと称される素子分離膜
の説明図である。同図中1はシリコン基板上に形成され
たSiO2膜であり、この膜の上にポリシリコン膜2、
SiN膜3を堆積させてLOCOS形成領域のポリシリ
コン膜2を露出させた状態を示している。このポリシリ
コン膜2を熱酸化することにより図中4で示すLOCO
S酸化膜が形成できる。この熱酸化により、LOCOS
酸化膜4は横方向に成長しバーズビークを形成する。こ
のバーズビークの長さ△x1、△x2の和が寸法変換差で
あり、この方法で形成されたLOCOS酸化膜では、寸
法変換差が0.35μm世代が限界といわれている。ま
た、この方法で形成されたLOCOSでは、基板表面に
突出する酸化膜の段差が大きいという問題がある。とこ
ろで、このLOCOS酸化膜の分離能力の評価基準とし
て、素子分離の下を流れる電流値が少ないほうがよいこ
とが上げられる。そのために必要な条件は、図4に示す
ような、基板表面からの素子分離の深さ△dが大きいほ
うがよい。この△dの大きさは、一般的に上記したポリ
パッドLOCOS<埋め込みLOCOS<トレンチ素子
分離という関係がある。
2. Description of the Related Art Conventionally, the problems to be solved by the invention
It is known that the LOCOS oxide film used for element isolation has a large dimensional conversion difference due to bird's beak. FIG. 3 is an illustration of an element isolation film called a so-called poly pad LOCOS. In the figure, 1 is a SiO 2 film formed on a silicon substrate, on which a polysilicon film 2,
The figure shows a state in which the SiN film 3 is deposited to expose the polysilicon film 2 in the LOCOS formation region. The polysilicon film 2 is thermally oxidized to form a LOCO 4 shown in the figure.
An S oxide film can be formed. Due to this thermal oxidation, LOCOS
The oxide film 4 grows laterally to form bird's beaks. The sum of the lengths of the bird's beaks Δx 1 and Δx 2 is the dimensional conversion difference, and the LOCOS oxide film formed by this method is said to have a dimensional conversion difference of 0.35 μm generation limit. In addition, the LOCOS formed by this method has a problem that the level difference of the oxide film protruding on the substrate surface is large. By the way, as an evaluation criterion of the separation ability of the LOCOS oxide film, it is better that the current value flowing under the element separation is smaller. The condition necessary therefor is that the depth Δd of element isolation from the substrate surface is preferably large as shown in FIG. The magnitude of this Δd is generally related to the above polypad LOCOS <buried LOCOS <trench element isolation.

【0003】また、上記したように、△dが不足してい
る場合、分離能力を高める目的でチャネルストップ注入
の濃度を上げる必要がある。ところが、LOCOSの下
の不純物の濃度を上げると、拡散によってゲート下の反
転層の濃度も上がるため、線幅が細いほど(チャネル幅
が狭いほど)トランジスタがオンしにくくなってしも
う。これを狭チャネル効果という。狭チャネル効果の抑
制には、分離能力の高い素子分離の形成が不可欠であ
る。
Further, as described above, when Δd is insufficient, it is necessary to increase the concentration of channel stop implantation for the purpose of enhancing the separation ability. However, if the concentration of impurities under the LOCOS is increased, the concentration of the inversion layer under the gate is also increased by diffusion, so that the transistor becomes harder to turn on as the line width becomes narrower (channel width narrower). This is called the narrow channel effect. In order to suppress the narrow channel effect, formation of element isolation with high isolation capability is essential.

【0004】また、従来のLOCOS形成方法として
は、所謂埋め込みLOCOSと称されるものがある。図
5は、この形成方法を示す工程断面図である。まず、図
5(A)に示すように、シリコン基板7の表面にSiO
2膜8、SiN膜9を形成し、LOCOS形成領域に溝
10を形成し、その後熱酸化により図5(B)に示すよ
うなLOCOS酸化膜11を形成する。そして、SiN
膜9を剥離してHFで処理して図5(C)に示すような
平坦な素子分離を形成するという技術である。この方法
は、基板中に深く酸化膜を形成するため、バーズビーク
をHFにより除去しても十分な分離能力を維持できる。
しかし、HFによってシリコン基板7の肩部7Aが露出
した場所に電界集中が起こりトランジスタがオンしゃす
くなってしまう現象(逆狭チャネル効果)が生じてしま
う問題がある。このように、シリコン基板の肩部7Aを
露出していると、図6及び図7に示すように、肩部7A
の上をゲート12が覆うように形成されてしまうので、
ゲート12の電圧を上げると肩部7Aが反転しやすくな
ってしまう問題がある。チャネル幅が狭くなる程、肩部
7Aの影響が大きくなり、反転電圧が下がってしまうこ
とから、逆狭チャネル効果と呼ばれている。また、この
ような、埋め込みLOCOSの場合、酸化時のストレス
が大きいので結晶欠陥を生じ易い問題がある。
As a conventional LOCOS forming method, there is a so-called embedded LOCOS method. 5A to 5D are process sectional views showing this forming method. First, as shown in FIG. 5A, SiO 2 is formed on the surface of the silicon substrate 7.
The 2 film 8 and the SiN film 9 are formed, the groove 10 is formed in the LOCOS formation region, and then the LOCOS oxide film 11 as shown in FIG. 5B is formed by thermal oxidation. And SiN
This is a technique in which the film 9 is peeled off and treated with HF to form a flat element isolation as shown in FIG. According to this method, an oxide film is deeply formed in the substrate, so that even if the bird's beak is removed by HF, a sufficient separation ability can be maintained.
However, there is a problem that HF causes a phenomenon in which electric field concentration occurs at a position where the shoulder portion 7A of the silicon substrate 7 is exposed and the transistor is turned on (reverse narrow channel effect). Thus, when the shoulder portion 7A of the silicon substrate is exposed, as shown in FIGS. 6 and 7, the shoulder portion 7A is exposed.
Since the gate 12 is formed so as to cover the above,
If the voltage of the gate 12 is increased, there is a problem that the shoulder portion 7A tends to be inverted. The narrower the channel width is, the larger the influence of the shoulder portion 7A becomes, and the inversion voltage is lowered. Therefore, it is called an inverse narrow channel effect. Further, in the case of such embedded LOCOS, there is a problem that crystal defects are likely to occur because the stress during oxidation is large.

【0005】さらに、従来のLOCOS形成方法として
は、トレンチ素子分離が知られている。図8(A)及び
(B)はその形成方法を示したものである。この方法
は、図8(A)に示すように、シリコン基板13にトレ
ンチ13Aを形成し、SiO2膜14を堆積させ、図8
(B)に示すように、SiO膜14を例えばエッチバッ
クして、除去している。この方法は、分離能力、寸法変
換差の点では最も有利であるが、SiO2の除去工程の
安定性、均一性などの点で問題があり、実用には至って
いない。SiO2を除去しすぎると、シリコン基板の肩
部が露出して、上記した逆狭チャネル効果が起こり、S
iO2の除去が不十分であると、素子形成領域中にSi
2のアイランドが残って不良となる。また、酸化膜の
研磨は、シリコン基板にダメージを与えやすい上に、膜
厚均一性の面でも問題点が残っている。
Further, as a conventional LOCOS forming method, trench element isolation is known. 8 (A) and 8 (B) show the forming method. In this method, as shown in FIG. 8A, a trench 13A is formed in a silicon substrate 13, a SiO 2 film 14 is deposited, and
As shown in (B), the SiO film 14 is removed by, for example, etching back. This method is most advantageous in terms of separation ability and dimensional conversion difference, but has problems in terms of stability and uniformity of the SiO 2 removal process, and has not been put to practical use. If SiO 2 is removed too much, the shoulder portion of the silicon substrate is exposed and the above-mentioned reverse narrow channel effect occurs, and S
If the removal of iO 2 is insufficient, Si is not formed in the device formation region.
O 2 islands remain and become defective. Further, the polishing of the oxide film is likely to damage the silicon substrate, and there are still problems in terms of film thickness uniformity.

【0006】そしてまた、図9に示すようなLOCOS
酸化膜15の場合、酸化膜端部の結晶欠陥(転位、積層
欠陥)は、SiN膜16のストレスなどによって発生す
る。これは、基板のごく表面付近(〜50nm)に存在
する欠陥である。
Further, the LOCOS as shown in FIG.
In the case of the oxide film 15, crystal defects (dislocations, stacking faults) at the oxide film end are generated by stress of the SiN film 16 or the like. This is a defect existing near the surface of the substrate (up to 50 nm).

【0007】この発明が解決しようとする課題は、バー
ズビークの縮退化とそれに伴うしきい値電圧(Vth)
の低下を防止でき、平坦性を向上できる素子分離膜の形
成方法を得るにはどのような手段を講じればよいかとい
う点にある。
The problem to be solved by the present invention is to reduce the degeneration of the bird's beak and the accompanying threshold voltage (Vth).
The problem lies in what kind of means should be taken to obtain a method for forming an element isolation film that can prevent the deterioration of the film thickness and improve the flatness.

【0008】[0008]

【課題を解決するための手段】そこで、この発明は、半
導体基板にLOCOS酸化膜を形成した後、該LOCO
S酸化膜を平坦化し、CMP研磨によって半導体基板と
LOCOS酸化膜との高さが略同一となるようにするこ
とを、解決手段としている。また、前記CMP研磨は、
前記半導体基板表面の欠陥層の除去し、且つLOCOS
酸化膜端部の酸化侵食部を除去するに充分な量に制御す
ることを特徴としている。さらに、前記LOCOS酸化
膜は、半導体基板に形成した溝内を酸化することにより
形成されることを特徴としている。
Therefore, according to the present invention, after forming a LOCOS oxide film on a semiconductor substrate, the LOCOS oxide film is formed.
The solution is to flatten the S oxide film and make the height of the semiconductor substrate and that of the LOCOS oxide film substantially the same by CMP polishing. Further, the CMP polishing is
Removal of a defect layer on the surface of the semiconductor substrate, and LOCOS
The feature is that the amount is controlled to be sufficient to remove the oxidatively eroded portion at the end portion of the oxide film. Further, the LOCOS oxide film is formed by oxidizing the inside of the groove formed in the semiconductor substrate.

【0009】[0009]

【作用】この発明においては、バーズビークの縮退化
と、それに伴うVthの低下を防止する作用を有する。
また、素子分離膜の平坦性が向上するため、露光の際の
焦点深度のマージンに対して余裕ができる作用がある。
さらに、シリコン表面層を除去するので、LOCOS端
部に生ずる基板表面の欠陥層を除去することができる。
According to the present invention, the bird's beak is degenerated and the Vth is prevented from being lowered.
Further, since the flatness of the element isolation film is improved, there is an effect that a margin of the depth of focus at the time of exposure can be afforded.
Further, since the silicon surface layer is removed, it is possible to remove the defect layer on the substrate surface generated at the LOCOS end portion.

【0010】[0010]

【実施例】以下、この発明に係る素子分離膜の形成方法
の詳細を実施例に基づいて説明する。図1(A)〜
(C)及び図2(A)〜(C)は、本実施例の形成工程
を示している。
EXAMPLES The details of the method for forming an element isolation film according to the present invention will be described below with reference to examples. FIG. 1 (A)-
(C) and FIGS. 2A to 2C show the forming process of this embodiment.

【0011】まず、図1(A)に示すように、シリコン
基板21の上に例えば膜厚20nmのSiO2膜22を
形成し、その上に200nmの膜厚のSiN膜23をC
VD法にて形成する。そして、リソグラフィー技術及び
異方性エッチング技術にてLOCOS用マスクとしての
SiN膜23をパターニングする。その再度SiN膜を
堆積させた後、エッチバックを行って、前記SiN膜2
3の側壁にSiNサイドウォール24を形成する。
First, as shown in FIG. 1A, a SiO 2 film 22 having a thickness of 20 nm is formed on a silicon substrate 21, and a SiN film 23 having a thickness of 200 nm is formed on the SiO 2 film 22.
It is formed by the VD method. Then, the SiN film 23 as a LOCOS mask is patterned by the lithography technique and the anisotropic etching technique. After depositing the SiN film again, etching back is performed to remove the SiN film 2
The SiN side wall 24 is formed on the side wall of No. 3.

【0012】次に、図1(B)に示すように、SiN膜
23及びSiNサイドウォール24をマスクとして反応
性イオンエッチングを行って、溝25を形成する。その
後、熱酸化を行って図1(C)に示すようなLOCOS
酸化膜26を形成する。
Next, as shown in FIG. 1B, reactive ion etching is performed using the SiN film 23 and the SiN sidewall 24 as a mask to form a groove 25. Then, thermal oxidation is performed to perform LOCOS as shown in FIG.
The oxide film 26 is formed.

【0013】次に、図2(A)に示すように、SiN膜
23及びSiNサイドウォール24を除去した後、図2
(B)にて示すようにフッ酸(HF)で処理してLOC
OS酸化膜26を平坦にする。この処理によって、LO
COS酸化膜26のバーズビークが除去されて、寸法変
換差を小さくすることができる。しかし、この状態で
は、シリコン基板21の肩部21Aが露出しており、こ
の部分で電界集中が起きてしまうので、以下のCMP研
磨工程を行う。
Next, as shown in FIG. 2A, after removing the SiN film 23 and the SiN sidewalls 24,
LOC after treatment with hydrofluoric acid (HF) as shown in (B)
The OS oxide film 26 is flattened. By this process, LO
The bird's beak of the COS oxide film 26 is removed, and the dimensional conversion difference can be reduced. However, in this state, the shoulder portion 21A of the silicon substrate 21 is exposed and electric field concentration occurs in this portion, so the following CMP polishing step is performed.

【0014】そして、最後に、通常のシリコンミラー仕
上げ研磨に用いられるコロイダルシリカ(アルカリ性の
もの)を用いて、研磨を行う。このコロイダルシリカ
は、粒径が10〜20nmのもので、研磨液として、K
OHやアミンでアルカリ性(PH10〜11)の調製液
を用いる。このCMP研磨は、主にシリコンを選択除去
する研磨である。最終工程をシリコンの仕上げ研磨にす
ることで、単にシリコン層を除くだけでなく、表面のダ
メージや結晶欠陥も除去することができる。このよう
に、埋め込みLOCOSで問題となっている、シリコン
の肩部の露出は、SiO2とSiとをほぼ同じ程度にな
るまで研磨すればこの問題は解決する。ここで重要なこ
とは、SiO2がほとんど削れない研磨剤を使用するた
め、除去すべきSiの表面は、HFによって完全に露出
していなければならないという点にある。上記したHF
での処理での酸化膜除去量の制御性が最終的な仕上げ形
状に影響するのである。この後、洗浄液を加えた後、通
常のプロセスに戻せばよい。
Finally, polishing is carried out using colloidal silica (alkaline) which is used for ordinary polishing of silicon mirrors. This colloidal silica has a particle size of 10 to 20 nm and is used as a polishing liquid with K
An alkaline (PH10-11) preparation liquid is used with OH or amine. This CMP polishing is a polishing mainly for selectively removing silicon. By performing final polishing of silicon in the final step, not only the silicon layer is removed, but also surface damage and crystal defects can be removed. Thus, the exposure of the shoulder portion of silicon, which is a problem in the embedded LOCOS, can be solved by polishing SiO 2 and Si to almost the same degree. What is important here is that the surface of Si to be removed must be completely exposed by HF, because an abrasive that does not substantially remove SiO 2 is used. HF mentioned above
The controllability of the amount of oxide film removed in the process of 1) affects the final finish shape. After that, after adding a cleaning liquid, the process may be returned to a normal process.

【0015】以上、実施例について説明したが、この発
明はこれに限定されるものではなく、構成の要旨に付随
する各種の設計変更が可能である。
Although the embodiment has been described above, the present invention is not limited to this, and various design changes associated with the gist of the configuration can be made.

【0016】[0016]

【発明の効果】以上の説明から明らかなように、この発
明によれば、バーズビークの縮退化と、それに伴うVt
hの低下を防止する効果を奏する。また、素子分離膜の
平坦性が向上するため、露光の際の焦点深度のマージン
に対して余裕ができる効果がある。さらに、シリコン表
面層を除去するので、LOCOS端部に生ずる基板表面
の欠陥層を除去することができる。
As is apparent from the above description, according to the present invention, degeneration of bird's beaks and the accompanying Vt.
This has the effect of preventing a decrease in h. Further, since the flatness of the element isolation film is improved, there is an effect that a margin of the depth of focus at the time of exposure can be afforded. Further, since the silicon surface layer is removed, it is possible to remove the defect layer on the substrate surface generated at the LOCOS end portion.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)〜(C)は本発明の実施例の工程を示す
断面図。
1A to 1C are cross-sectional views showing the steps of an embodiment of the present invention.

【図2】(A)〜(C)は本発明の実施例の工程を示す
断面図。
2A to 2C are cross-sectional views showing a process of an embodiment of the present invention.

【図3】従来例を示す断面説明図。FIG. 3 is an explanatory sectional view showing a conventional example.

【図4】従来例を示す断面説明図。FIG. 4 is a sectional explanatory view showing a conventional example.

【図5】(A)〜(C)は従来例の工程を示す断面図。5A to 5C are cross-sectional views showing steps of a conventional example.

【図6】従来例の平面図。FIG. 6 is a plan view of a conventional example.

【図7】従来例の断面説明図。FIG. 7 is a sectional explanatory view of a conventional example.

【図8】(A)及び(B)は従来例の工程を示す断面
図。
8A and 8B are cross-sectional views showing steps of a conventional example.

【図9】従来例の工程を示す断面図。FIG. 9 is a sectional view showing a process of a conventional example.

【符号の説明】[Explanation of symbols]

21…シリコン基板 22…SiO2膜 23…SiN膜 24…SiNサイドウォール 25…溝 26…LOCOS酸化膜21 ... Silicon substrate 22 ... SiO 2 film 23 ... SiN film 24 ... SiN sidewall 25 ... Groove 26 ... LOCOS oxide film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板にLOCOS酸化膜を形成し
た後、該LOCOS酸化膜を平坦化し、CMP研磨によ
って半導体基板とLOCOS酸化膜との高さが略同一と
なるようにすることを特徴とする素子分離膜の形成方
法。
1. A LOCOS oxide film is formed on a semiconductor substrate, the LOCOS oxide film is planarized, and the height of the semiconductor substrate and that of the LOCOS oxide film are made substantially the same by CMP polishing. Method for forming element isolation film.
【請求項2】 前記CMP研磨は、前記半導体基板表面
の欠陥層の除去し、且つLOCOS酸化膜端部の酸化侵
食部を除去するに充分な量に制御する請求項1記載の素
子分離膜の形成方法。
2. The element isolation film according to claim 1, wherein the CMP polishing is controlled to an amount sufficient to remove a defective layer on the surface of the semiconductor substrate and to remove an oxidative erosion portion at an end portion of the LOCOS oxide film. Forming method.
【請求項3】 前記LOCOS酸化膜は、半導体基板に
形成した溝内を酸化することにより形成される請求項1
記載の素子分離膜の形成方法。
3. The LOCOS oxide film is formed by oxidizing a groove formed in a semiconductor substrate.
A method for forming an element isolation film as described above.
JP16348394A 1994-07-15 1994-07-15 Method for forming element isolation film Pending JPH0831810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16348394A JPH0831810A (en) 1994-07-15 1994-07-15 Method for forming element isolation film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16348394A JPH0831810A (en) 1994-07-15 1994-07-15 Method for forming element isolation film

Publications (1)

Publication Number Publication Date
JPH0831810A true JPH0831810A (en) 1996-02-02

Family

ID=15774736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16348394A Pending JPH0831810A (en) 1994-07-15 1994-07-15 Method for forming element isolation film

Country Status (1)

Country Link
JP (1) JPH0831810A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851362B2 (en) 2008-02-11 2010-12-14 Infineon Technologies Ag Method for reducing an unevenness of a surface and method for making a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851362B2 (en) 2008-02-11 2010-12-14 Infineon Technologies Ag Method for reducing an unevenness of a surface and method for making a semiconductor device
DE102008063332B4 (en) * 2008-02-11 2012-10-11 Infineon Technologies Ag A method of reducing surface unevenness and a method of fabricating a semiconductor device

Similar Documents

Publication Publication Date Title
US5956598A (en) Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit
US6326283B1 (en) Trench-diffusion corner rounding in a shallow-trench (STI) process
KR960016502B1 (en) Integrated circuit isolation method
EP0407047B9 (en) Method of planarization of topologies in integrated circuit structures
US6121110A (en) Trench isolation method for semiconductor device
US6537914B1 (en) Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing
JPH06302684A (en) Forming method for field oxide film in semiconductor element
US6828213B2 (en) Method to improve STI nano gap fill and moat nitride pull back
KR20010046153A (en) Method of manufacturing trench type isolation layer in semiconductor device
JPH0831810A (en) Method for forming element isolation film
US6410405B2 (en) Method for forming a field oxide film on a semiconductor device including mask spacer and rounding edge
JPH11121609A (en) Manufacture of semiconductor device
JPH11340315A (en) Manufacture of semiconductor device
JP2003197734A (en) Formation of isolation film of semiconductor device
JP2009123890A (en) Semiconductor device and manufacturing method thereof
JPH09289245A (en) Fabrication method of semiconductor device
KR100305077B1 (en) Method for forming isolation layer of a semiconductor device
KR100588646B1 (en) Method for fabricating isolation of semiconductor device
JP3365114B2 (en) Method of forming field oxide film in semiconductor device, and method of forming field oxide film and trench isolation region
KR100429555B1 (en) Method for forming trench type isolation layer in semiconductor device
KR100561524B1 (en) Method for fabricating shallow trench isolation
KR100561974B1 (en) A Manufacturing Method of Semiconductor Element
KR100419873B1 (en) method for isolating semiconductor device
KR20000045908A (en) Method for forming device isolation layer of trench structure of semiconductor device
KR20080001340A (en) Method for forming isolation layer in semiconductor device