JPH08316432A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To eliminate production of crystal defect of a semiconductor substrate and enable simultaneously eliminating a silicon nitride film and a silicon oxide film. CONSTITUTION: In a manufacturing method of a semiconductor device of a recessed array structure having a memory cell, the following are performed; a process wherein a poly silicon film 32 is formed on a silicon substrate 31, a process wherein the polysilicon film 32 is processed and a memory cell region is formed, a process wherein the polysilicon film 32 and the silicon substrate 31 are simultaneously oxidized and a silicon film 33 is formed, and a process wherein the silicon film 33 is all eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor substrate having a recessed array structure.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, (1) “K. Sagara, et al. "A
0.72 μm ² RECESSED STC (RSTC)
TECHNOLOGY FOR 256Mbit D
RAMs USING QUARTER-MICRON
PHASE-SHIFT LITHOGRAPH
Y ”” and (2) “Toshiomi Yamashita et al.“ Recess array DRAM cell junction leakage current reduction by IG heat treatment ””.

In recent years, due to the demand for high integration, DRAM memory cells must obtain sufficient storage capacity with a small area. Therefore, a method of forming memory cells three-dimensionally is used. As a result, the height of the memory cell region becomes higher than that of the peripheral circuit region, which causes a problem that the focus margin at the time of lithography of the upper layer wiring is reduced.

In order to solve this problem, a method is used in which a concave portion is formed in advance in the memory cell region to enlarge the focus margin during photolithography. FIG. 2 is a side sectional view of a DRAM having a recessed array structure in which the memory cell region is previously formed as a recess. FIG. 3 is a cross-sectional view of manufacturing steps of such a conventional silicon substrate having a recessed array structure.

In FIG. 2, reference numeral 11 is a memory cell area in which a recess is formed in advance (recessed array), and 12 is a peripheral circuit area thereof. The memory cell region 11 is a LOCO in which an active region is opened on the silicon substrate 1.
The S oxide film 2 is formed, and the gate electrode 3, the bit line 4, the interlayer insulating film 5, the storage electrode 6, the interlayer insulating film 7, the wiring layer 8, and the protective film 9 are formed.

A method of manufacturing the conventional silicon substrate having a recessed array will be described below. (1) First, as shown in FIG. 3A, as a method of forming a recess in a silicon substrate, a silicon oxide film 22 is formed on a silicon substrate 21, and a silicon nitride film 23 is formed on the silicon oxide film 22. accumulate.

(2) Next, as shown in FIG. 3B, the silicon nitride film 23 is processed by a photolithographic etching method to form a memory cell region. (3) Next, as shown in FIG. 3C, the silicon substrate 21 is selectively oxidized to form a silicon oxide film 24. (4) Next, as shown in FIG. 3D, the silicon nitride film 23 [see FIG. 2C] is removed with phosphoric acid.

(5) Next, as shown in FIG.
The silicon oxide film 24 (see FIG. 2D) was removed with hydrofluoric acid.

[0009]

However, in the above-mentioned conventional method for manufacturing a silicon substrate having a recessed array structure, since the silicon substrate is oxidized in the presence of the hard silicon nitride film, the semiconductor is thermally stressed. A defect that crystal defects occur on the substrate occurred. There is also a problem that the silicon nitride film and the silicon oxide film cannot be removed at the same time.

It is an object of the present invention to provide a method of manufacturing a semiconductor device which eliminates the above problems, eliminates the occurrence of crystal defects in a semiconductor substrate, and can simultaneously remove a silicon nitride film and a silicon oxide film. And

[0011]

In order to achieve the above object, the present invention provides: (1) In a method of manufacturing a semiconductor device having a recessed array structure including memory cells, a first oxidative film is formed on a semiconductor substrate. And a step of forming the memory cell region by processing the first oxidizable film, and a step of simultaneously oxidizing the first oxidizable film and the semiconductor substrate to form a second oxidizable film. Then, a step of removing all of the second oxidative film is performed.

(2) In the method of manufacturing a semiconductor device described in (1) above, the first oxidizable film is formed of two or more layers of different kinds of materials. (3) In the method of manufacturing a semiconductor device according to (1) or (2) above, the first oxidizable film is formed by tapering it. Here, the oxide film means a film that is not an oxidation resistant film, and includes not only an oxide film but also a polysilicon film or the like.

[0013]

(1) According to the method of manufacturing a semiconductor device of claim 1,
Since the hard silicon nitride film is not used as in the conventional method, it is possible to avoid occurrence of crystal defects in the semiconductor substrate due to thermal stress during oxidation, as compared with the conventional method. In addition, the film removal after oxidation can be performed at one time, and the semiconductor device can be manufactured in a small number of steps.

(2) In the method of manufacturing a semiconductor device according to the second aspect, the silicon oxide film is formed between the polysilicon film and the silicon substrate, so that the polysilicon film is selectively etched at the time of etching the polysilicon. It can be etched and damage to the silicon substrate can be eliminated. Since the etching damage to the silicon substrate acts as a nucleus for the generation of crystal defects, by suppressing this damage, the occurrence of crystal defects in the semiconductor substrate due to thermal stress during oxidation is further avoided as compared with the case of (1) above. be able to.

(3) According to the method of manufacturing a semiconductor device of claim 3, a silicon oxide film is formed between the polysilicon film and the silicon substrate, and a polysilicon film having a taper is selected at the time of etching the polysilicon. Since it can be etched selectively, damage to the silicon substrate can be eliminated, and since a gentle taper is formed between the convex portion and the concave portion, it is possible to improve the step coverage of the upper wiring. It is possible to eliminate etching residue and the like at the time of photolithography / etching of the wiring in the step portion.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 1A to 1D are sectional views of a semiconductor device in a manufacturing process showing a first embodiment of the present invention. (1) First, as shown in FIG. 1 (A), a polysilicon film 32 is formed on a P-type silicon substrate 31 by a CVD method at 5000Å.
accumulate.

(2) Next, as shown in FIG. 1B, the polysilicon film 32 is processed by the photolithographic etching method to form a memory cell region. (3) Next, as shown in FIG. 1C, the polysilicon film 32 is oxidized at 1000 ° C. in a wet O ₂ atmosphere.
All of [see FIG. 1B] and part of the P-type silicon substrate 31 are oxidized to deposit a silicon oxide film 33.

(4) Then, as shown in FIG.
By removing all the silicon oxide film 33 with 5% hydrofluoric acid, it is possible to form a recess in the P-type silicon substrate 31. That is, the memory cell area 34 and the peripheral circuit area 35
Can be formed. Thus, unlike the conventional method, the hard silicon nitride film is not used, so that it is possible to avoid generation of crystal defects in the semiconductor substrate due to thermal stress during oxidation, as compared with the conventional method.

In addition, the film removal after the oxidation can be performed at once, and the semiconductor device having the recessed array structure can be manufactured by a small number of steps. Next, a second embodiment of the present invention will be described. FIG. 4 is a sectional view of a semiconductor device manufacturing process showing the second embodiment of the present invention. (1) First, as shown in FIG. 4 (A), the P-type silicon substrate 41 is oxidized at 850 ° C. in a wet O ₂ atmosphere to form a silicon oxide film 42 of 300 Å. A polysilicon film 43 is deposited thereon by the CVD method at 5000 Å.

(2) Next, as shown in FIG.
The polysilicon film 43 is processed by photolithography and anisotropic etching to form a memory cell region. (3) After that, as shown in FIG.
Oxidation is performed in a wet atmosphere to oxidize the entire polysilicon film 43 and part of the P-type silicon substrate 41 to form a silicon oxide film 44.

(4) After that, as shown in FIG. 4D, the silicon oxide film 44 is completely removed with 5% hydrofluoric acid to form a recess in the P-type silicon substrate 41. That is, the memory cell area 45 and the peripheral circuit area 4
6 can be formed. In this way, by forming the silicon oxide film between the polysilicon film and the silicon substrate, the polysilicon can be selectively etched during the etching of the polysilicon film, and damage to the silicon substrate can be eliminated. . Since the etching damage to the silicon substrate acts as a nucleus for the generation of crystal defects, by suppressing this damage, the generation of crystal defects in the semiconductor substrate due to thermal stress during oxidation is further avoided as compared with the case of the first embodiment. be able to.

Next, a third embodiment of the present invention will be described. (1) First, as shown in FIG. 5A, the P-type silicon substrate 51 is oxidized in a wet O ₂ atmosphere at 850 ° C. to form a silicon oxide film 52 of 300 Å. A polysilicon film 53 is deposited thereon by the CVD method at 5000 Å. (2) Next, as shown in FIG. 5B, the taper 53a is formed by photolithography and isotropic etching.
The polysilicon film 53 having (for example, a taper of 45 degrees) is processed to form a memory cell region.

(3) After that, as shown in FIG.
Oxidation is performed at 950 ° C. in a wet atmosphere to oxidize all of the polysilicon film 53 and part of the P-type silicon substrate 51 to form a silicon oxide film 54. (4) After that, as shown in FIG. 5D, the silicon oxide film 54 is completely removed with 5% hydrofluoric acid to provide a P-type silicon substrate 51 in which a concave portion having a gentle taper 51a is formed. be able to. That is, the peripheral circuit region 56 having the memory cell region 55 and the gentle taper 51a can be formed.

In this way, the silicon oxide film can be formed between the polysilicon film and the silicon substrate, and the polysilicon film having the taper can be selectively etched during the polysilicon etching, and the silicon substrate can be selectively etched. Since it is possible to eliminate damage and a gentle taper is formed between the convex and concave parts,
It is possible to improve the step coverage of the upper layer wiring and eliminate etching residue of the wiring in the step portion during photolithography / etching.

Although the P-type silicon substrate has been described above as an example, the same effect can be obtained by using an N-type silicon substrate or a semiconductor other than silicon. Although polysilicon is used in each of the embodiments, it is needless to say that the same effect can be obtained as long as the material is not oxidation resistant. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0026]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention described in claim 1, since a hard silicon nitride film is not used unlike the conventional method, it is possible to avoid occurrence of crystal defects in the semiconductor substrate due to thermal stress during oxidation, as compared with the conventional method. You can

Moreover, the film removal after oxidation can be performed at once, and the semiconductor device can be manufactured in a small number of steps. (2) According to the second aspect of the invention, by forming a silicon oxide film between the polysilicon film and the silicon substrate, the polysilicon can be selectively etched during the polysilicon etching. Can eliminate damage to. Since etching damage to a silicon substrate acts as a nucleus of crystal defect generation, by suppressing this damage, it is possible to further prevent crystal defects from being generated in a semiconductor substrate due to thermal stress during oxidation, as compared with the above (1) invention. You can

(3) According to the third aspect of the present invention, a silicon oxide film is formed between the polysilicon film and the silicon substrate, and the tapered polysilicon is selectively etched when the polysilicon film is etched. As a result, damage to the silicon substrate can be eliminated, and since a gentle taper is formed between the convex portion and the concave portion, it is possible to improve the step coverage in the upper layer wiring, and at the same time, in the step portion, It is possible to eliminate etching residue and the like during photolithography and etching of wiring.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a side sectional view of a DRAM having a recessed array structure in which a memory cell region is previously recessed.

FIG. 3 is a cross-sectional view of a manufacturing process of a conventional silicon substrate having a recessed array structure.

FIG. 4 is a sectional view of a semiconductor device in the manufacturing process showing the second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device manufacturing process showing the third embodiment of the present invention.

[Explanation of symbols]

 31, 41, 51 P-type silicon substrate 32, 43, 53 Polysilicon film 33, 42, 44, 52, 54 Silicon oxide film 34, 45, 55 Memory cell area 35, 46, 56 Peripheral circuit area 53a Taper

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a recessed array structure including memory cells, comprising: (a) forming a first oxidizable film on a semiconductor substrate; and (b) processing the first oxidizable film. And forming a memory cell region,
(C) having a step of simultaneously oxidizing the first oxidizable film and the semiconductor substrate to form a second oxidizable film, and (d) a step of removing all of the second oxidizable film. A method for manufacturing a characteristic semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first oxidizable film is formed of two or more layers of different kinds of materials. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first oxidizable film is formed by tapering.